I2C Master IP Core Michael Lawlor IT Carlow

Introduction This project implemented a parameterizable I2C IP core on the

Smartfusion 2 SoC FPGA chip which included an ARM Cortex

M3. Configurable FIFOs were used to create a microprocessor

friendly IP core which would allow for the transmission and

reception of data to and from the I2C bus without the use of any

interrupts. This hardware platform combined with a firmware

driver created a custom I2C master IP core that fully adhered to

the I2C bus specification. This system allowed for read and write

operations to occur in both standard mode (100 Kb/s) and fast

mode (400 Kb/s).

Test, Verification and Interoperability In order to ensure that the hardware is operating as

required a method of testing the functionality of the

HDL is needed. In industry this is done through the

use of simulation that allows for both functional and

temporal analysis. Testbenches are used in

conjunction with simulation tools for the verification

of hardware. Here an Opencore I2C slave HDL

model was used to verify interoperability during the

simulation process. Finally a demonstration platform

containing two I2C slaves from Philips and Maxim

were used as a final interoperability test platform

(FIG 4). FIG 5 and FIG 6 show PicoScope read and

write transactions between the Master IP core and

multiple slaves.

Conclusion The partitioning of the Hardware and Software made

the I2C IP core efficient and processor friendly. In

terms of the overall design the decision to make the

FIFOs configurable proved to be great success. This

allowed for the FIFOs to be informed by software

about a predetermined number of bytes that were

required to be sent to or received from the bus. This

method of design then allowed the FIFOs to tell the

hardware when they were full or empty in order to

initialise and terminate data transfers. By doing this a

certain level of autonomy was achieved as once the

microcontroller supplied the hardware with the

predetermined number of bytes no more interactions

were required between the two until it was the

microcontroller that wanted to contact the hardware

again.

Design Methodology By using top-down and bottom-up approaches in conjunction

with one another the design and verification process appeared

to be almost accordion like. First the design would move from

the context diagram through each layer defining the blocks and

interconnects. Once the bottom layer was reached extra

signals may be required to implement the correct functionality.

These changes would then ripple back up through the layers of

the design. This method of design allows for a project to be

defined in a structured manner which leads to a greater

success rate in terms of design functionality implementation.

APB_Interface Holds APB

addressable resgister

FIFO.TX.RX Holds read

and write FIFO Configurable Full and Empty

flags used to control I2C master

I2C_bus Implements

I2C protocol

Clock_gen Generates

derived clock from PCLK

Clock used for hold time counters

Also used to generate SCL

PREADYPCLK

PENABLEPRESETn

PSELPWRITE

PWDATA[7:0]PADDR[7:0]

Hold_startClock_start

Timer_setClk_tickInt_clk

Wrfifo_fullWrfifo_empty

rdfifo_full

wrFifo_data[7:0]rdFifo_data[7:0]

Byte_cmpack

rdfifo_enablewrfifo_enable

SDA

SCL

Wrfifo_data[7:0]Transfer_size

rdfifo_data[7:0]Write_ptr[7:0]Read_ptr[7:0]

Write_enSft_reset

Read_enable

Status[7:0]Ackcount[7:0]

New signalsClk_div[3:0]: used to choose prescaler for PCLKWrite_en: Used to enable data writes into the fifoTimer_start: Used to start and stop hold time counterint_clk: this is used as the output signal through SCLAck/nack: used to increment the ackcount register when ack received.status: Feeds the current status of the master to the status registerRead_en: allows reading of data from write_fifowrFifo_data: data to be sent out on SDARdFifo_data: data received from SDA line

APB_

MAS

TER

I2C_

PERI

PHER

ALS

Address[7:0]Transfer_size[7:0]

Rw_bitStart_bit

FIG 5 – PicoScope Protocol Analyser write transaction

FIG 4 – Interoperability Demonstration Platform

FIG 1 – Block Level HDL design

FIG 3 – SmartFusion 2 FPGA Architecture

FIG 2 –Top Level Fletcher Diagram

FIG 6 – PicoScope Protocol Analyser read transaction