THE AMD OPTERON PROCESSORFOR MULTIPROCESSOR SERVERS
Chetana N. KeltcherKevin J. McGrathArdsher Ahmed
Pat ConwayAdvanced Micro Devices
Outline Introduction Terminology and problem definition
. AMD 64 bit architecture. Core microarchitecture. AMD Different HT link Configuration.
Problem Definition The main approach
. HT link Configuration application. Algorithm Conclusion
IntroductionAMD 64 bit architecture
AMD Opteron Architecture
Terminology AMD 64 bit architecture
Programmer’s model for the x86-64 architecture.
Terminology Core microarchitecture •three integer execution units, •three address generation units, •three floating point and multimedia
units,and •two loads/stores to the data cache.The CPU Instruction (MMX, 3Dnow,SSE, and
SSE 2) to enhance the multimedia, Internet and graph.
Terminology Core microarchitecture
Processor core block diagram.
Terminology AMDDifferent HT link Configuration
Problem Definition the AMD HT link table the Only support to one
link table in the BIOS core. the User can not random remove whatever AMD CPU. It will make the BIOS power on fail in HT link table.
The main approach. AMDDifferent HT link Configuration.
Standard CPU HT Configuration
cHT 16x16
HT 16x16 HT 16x16
BIOS Start
HT Table
INT 19
Remove CPU
0
12
The main approach. HT link Configuration application.
Standard CPU HT Configuration
cHT 16x16
HT 16x16 HT 16x16
0
1
2
0
HT Table
INT 19
BIOS Start
BIOS Hang
The main approach. HT link Configuration application.
Tow-way CPU configuration HT application (Support 3 HT Table)
CPU1 CPU0
IOIO
CPU1 CPU0
IOIO
Dummy CPU0
IOIO
CPU1 Dummy
IOIO
The main approach. HT link Configuration application.
Four-way CPU configuration HT application
CPU 3 CPU 2
CPU 1 CPU 0
IO IO
The main approach. HT link Configuration application.
CPU 3 CPU 2
CPU 1 CPU 0
IO IO
NELL CPU 2
CPU 1 CPU 0
IO IO
CPU 3 NELL
CPU 1 CPU 0
IO IO
CPU 3 CPU 2
Dummy CPU 0
IO IO
CPU 3 CPU 2
CPU 1 Dummy
IO IO
NULL NULL
CPU 1 CPU 0
IO IO
NULL NULL
Dummy CPU 0
IO IO
CPU 3 CPU 2
CPU 1 Dummy
IO IO
CPU 3 CPU 2
Dummy Dummy
IO IO
Dummy CPU 2
Dummy Dummy
IO IO
CPU 3 Dummy
Dummy Dummy
IO IO
CPU 3 Dummy
CPU 1 Dummy
IO IO
Dummy CPU 2
Dummy CPU 0
IO IO
Null CPU 2
CPU 1 Dummy
IO IO
CPU 3 NULL
Dummy CPU 0
IO IO
Four-way CPU configuration HT application (Support 15 HT Table)
BIOS Start
DetectCPU
Detect HT Table(Count 15)
NO
INT 19
Yes
The main approach. HT link Configuration application.
BIOS Start
DetectCPU
Detect HT Table(Count 63)
NO
INT 19
Yes
Eight-way CPU configuration HT application (Support 63 HT Table)
Algorithm
Two-way HT table Four-way HT table Eight-way HT table
一 1 = Y
X = CPU Y = HT table total
Multi-HyperTransport Link Table Algorithm
Conclusion
Our goal is to eliminate the AMD fixed CPU architecture, I can use The BIOS detect HT tables for the CPU architecture, We must help customer reduce the production cost.
References PhoenixBIOS 4.0 Release 6.1 AMIBIOS8 eKERNEL Implementation Guide 08/22/2
001 Version 2.2 AMI CPU MODULE Interface Description V1.0 BIOS and Kernel Developer’s Guide(BKDG) For AM
D Family 10h Processors Advanced Micro Devices 31116 Rev 3.01 - September 06, 2007
Keywords
MMX (Multi Media Extended) SSE 、 SSE2 (Streaming-Single instru
ction multiple data-Extensions 2) GPRs (general-purpose registers) BIOS (basic input-output system )
Nootbook MMX ( Multi Media Extended ) SSE(Streaming SIMD Extensions) SIMD = SIMD 就是指 Single Instruction Multiple Data. SSE2(Streaming-Single instruction multiple data-Extensions 2 ) general-purpose registers (GPRs) 3DNow 等都是 CPU 的 ? 展指令集,分別增強了 CPU 的多媒体、圖形圖象和 Internet 等的處理能力
ALU 算術邏輯單位和一般暫存器的控制部分 MTLU 乘法指令 AGU 三個地址產生單元 (AGU) 可以採用一套靈活的尋址模 式在一個指令執行週期內完成一個或兩個 ( 針對 DSP MAC 類指令 ) 數據記憶體的讀取和一個數據記憶體寫入作業 FADD (雙精度浮點加法 ) FMUL (Floationg Point Multiplication ,浮點乘 ) FMISC 存儲器是在單元上執行的
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