Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 1
The 2005 ITRS
Assembly and Packaging
Roadmap
The 2005 ITRS
Assembly and Packaging
Roadmap
About ITRSAbout ITRS
ITRS = International Technology Roadmap for SemiconductorsCombined effort by semiconductor industries
worldwideMajor revisions in odd numbered years with updates in even numbered years2005 revision published in December 2005 Assembly and Packaging (A&P) is one of 14 chaptersurl: http://public.itrs.net
Santa Clara Valley Chapter, CPMT Society
www.cpmt.org/scv/
March 23, 2006
Page 2
ITRS A&P Chapter OrganizationITRS A&P Chapter Organization
ScopeDifficult ChallengesTechnical RequirementsInfrastructure ChallengesPotential SolutionsTables
Assembly and Packaging Roadmap Participants 2005
Assembly and Packaging Roadmap Participants 2005
Shigeki UedaCoen Tak
Max Juergen WolfAkira YoshidaTakashi TakataBernd Roemer
Eiji Yoshida Shigeru UtsumiNobuo FutawatariKlaus Pressel
Hisao KasugaHajime TomokageFumihiko HayanoGilles Poupon
Kazuo NishiyamaRyo Haruta Hirofumi NakajimaLuu Nguyen
Shuya HaruguchiMike HungSergio CameloKeith Newman
Mahadevan K. IyerCarl ChenGeorge HarmanStan Mihelcic
John T. Fisher
Bob Pfahl
Henry Utsunomiya
Shoji Uegaki
Zhiping Yang.
Voya Markovich
Ralf Plieninger
Michitaka Kimura
Joe Adam
Chi-Shih Chang
Shyi-Ching Liau
Masanao Yano
Lei Mercado
Debendra Mallik
Abhay Maheshwari
Rongshen Lee
William Chen Co-Chair
W. R. Bottoms Chair
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 3
Assembly and Packaging Roadmap 2005
Assembly and Packaging Roadmap 2005
Packaging has become the limiting element in system cost and performance The Assembly and packaging role is expanding to include system level integration functions.As traditional Moore’s law scaling become more difficult innovation in assembly and packaging innovation can take up the slack.
The Consumerization of Electronics has arrived
The Consumerization of Electronics has arrived
…and there are many implications…and there are many implications
Golfball with Wireless Sensor Node
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 4
Computing System performance increase continues
Example: Game Consolefrom this…
Computing System performance increase continues
Example: Game Consolefrom this…
Mini Football video gameCirca: 1990s
to this…to this…
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 5
Consumer Market Imperatives…….Consumer Market Imperatives…….
PowerPower
WeightWeight
SizeSize
CostFunctionality & Reliability
Assembly and Packaging Emerging as Limiting Factor for Cost and Performance
Assembly and Packaging Emerging as Limiting Factor for Cost and Performance
Consumers now drive more than half of integrated circuit revenueAssembly and Packaging technology is a primary differentiator for consumer electronicsThese factors are driving an unprecedented pace of innovation in:– New materials – New Technologies– New Systems integration
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 6
What’s New for 2005What’s New for 2005
Expanded Coverage– System in Package– Wafer level packaging– Materials
New Technologies– Wafer thinning– 3D Packaging and Systems Integration– Embedded and integrated components– Infrastructure– Flexible packaging – Medical and Biochip Packaging
What’s New for 2005---Continued
What’s New for 2005---Continued
New Tables– Package Substrate Physical Properties– Medical and Biochips– Package Substrate Design Parameters– Package Level System Integration– Processes used for SiP– System-in-a-Package Requirements– Thinned Silicon Wafer Thickness
200mm/300mmMajor Revisions to Existing Tables
– Die size– Pin count– Junction temperature
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 7
New MaterialsNew Materials
Cu interconnectUltra Low k dielectricsHigh k dielectricsOrganic semiconductorsGreen Materials
– Pb free– Halogen free– other
New Packaging TechnologiesNew Packaging TechnologiesThinned wafers3D systems integrationWafer level packagingBio-chipsIntegrated opticsEmbedded/integrated active and passive devicesMEMSPrintable circuits
– Semiconductors– Light emitters– RF– Interconnect
Flexible (wearable) electronics
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 8
Thinned Wafers/DieThinned Wafers/Die
(a) Rolled Wafer
(b) Light Transparency
1010µµm Thickness Waferm Thickness Wafer
Source: Shinko Electric Industry,
Printable ElectronicsPrintable Electronics
Inter-chip wiring by ink jet printingLED wiring by ink jet printing
Source: SiP Consortium
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 9
System IntegrationSystem Integration
Cos
t/ fu
nctio
nTi
me
to m
arke
t
System complexity
System on Chip
SiP and 3D PackagingMEMS
Bio-InterfacePower supply
Source: Fraunhofer IZM
SiP in the Cellular PhoneSiP in the Cellular Phone
Source: T. Sakurai, University of Tokyo
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 10
Systems Integration in the Cellular PhoneIt is not only integrated circuits
Systems Integration in the Cellular PhoneIt is not only integrated circuits
Tx、Rx Circuit•Smaller & lower power consumption of analog circuit•Decrease of # of mounted components
Camera Circuit•Smaller•Lower power consumption•One unit of lens and control circuit
DSP・CPU・BB•Dual CPU: Transmission /Application
Memory Circuit•Memory area for downloaded software•Higher memory capacity
Outer Interface Circuit•Bluetooth, USB interface
•MP3, GPS interface•Memory Card interface
LCD Circuit•Larger display, Color display•Lower power consumption•Higher resolution
Plug In Memory Card•Smaller, thinner
•Higher memory capacity
Power Supply Circuit
•Smaller Size
Embedded Antenna•Smaller・Stability of signal
•Influence on the human body
Source: H.Ueda JEITA
Categories of SiPCategories of SiP
Horizontal Placement
StackedStructure
Interposer Type
Interposer-less Type
Wire Bonding Type Flip Chip Type
Wire Bonding TypeWire Bonding +Flip Chip Type Flip Chip Type
Terminal Through Via Type
Source: 20030710 K. Nishi, Hitachi, JEITA, Revised by H. Utsunomiya
Embedded StructureChip (WLP) Embedded + Chip on Surface Type
3D Chip EmbeddedType
WLP Embedded + Chip on Surface Type
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
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SiP- Multi level system IntegrationSiP- Multi level system Integration
Source: Fraunhofer IZM
system partitioning in sub-system packages (SiP‘s)stackable thin packages containing passives and active chipstestability of each package before stackingcomplete systems or sub-systems containing functional layerswith embedded components
Cross section of a single stack packagevia to board metallization
solder ball
filled through
holeembedded chip
and via to chip pad
build-up layer
0.5mm FR4 board
Stack of 4 singlepackages
Realization of a Stackable Chip Package Chip in Polymer
Realization of a Stackable Chip Package Chip in Polymer
Source: Fraunhofer IZM
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 12
Difficult Challenges Near TermDifficult Challenges Near Term
• Fine Pitch Packages• 3D Packaging• Flexible system Packaging • High current density packages•Thinned die packaging•Wafer Level Packaging
•Impact of new materials•Package substrate requirements•Embedded components
•Design tools and simulators for chip, package and substrate co-design
0
50
100
150
200
250
2005 2010 2015 2020
POW
ER (W
atts
)PO
WER
(Wat
ts)
Source : 2005 ITRS
Cost-Performance
ITRS Power dissipation trends
With increased awareness, power increases are at a slower rate.
With increased awareness, power increases are at a slower rate.
High Performance
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 13
Difficult Challenges Long TermDifficult Challenges Long Term
Package cost not scaling with die costSmall Die with High Pad Count and/or High Power Density High frequency die
Emerging Device Types (Organic, Nanostructures, Biological) that require New Packaging Technologies
System-level Design Capabilityfor Integrated Chips, Passives, and Substrates
SystemsSystemsFacilitiesFacilities
Heat SinksHeat SinksPackagesPackages
SiliconSilicon
Architectural improvements in Silicon process & designArchitectural improvements in Silicon process & designEnhance Heat Spreading (Package)Enhance Heat Spreading (Package)Increase Power handling (Heatsinks)Increase Power handling (Heatsinks)Expand System Thermal Envelopes & optimize thermalsExpand System Thermal Envelopes & optimize thermals
Address the “Total System”…Address the “Total System”…
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 14
Some requirements have no known solution
Some requirements have no known solution
150150150150150150125Harsh
88813710515684045472363782910223282High-performance (for differential-pair point-to-point nets)
1200120012001200120010001000Cost-performance (for multi-drop nets)
150/1200150/1200150/1200150/1200150/1200125/1000125/1000Logic/memory
Performance: Chip-to-Board for Peripheral Buses (MHz) [7]
2020201920182017201620152014Year of Production
Some requirements have no known solution
Some requirements have no known solution
2020201920182017201620152014Year of Production
0.0050.0050.0050.0050.0050.0050.005Ceramics Structure0.00010.00010.00010.00010.00010.00010.0001Tape Structure
0.0020.0020.0020.0020.0020.0020.002Buildup 0.0060.0060.0060.0060.0060.0060.006Rigid Structure
Dielectric Loss (at 1 GHz)
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 15
Some requirements have no known solution
Some requirements have no known solution
2020201920182017201620152014Year of Production
200x100200x100200x100200x100200x100200x100200x100Minimum component size (microns)
101099988High performance (# die / SiP)
18171716161515Low cost/handheld (# die / SiP)
7766655High performance (# die / stack)
17161615151414Low cost/handheld (# die / stack)
Some requirements have potential solutions identified but not provenSome requirements have potential solutions identified but not proven
2020201920182017201620152014Year of Production
70707080808080Flip chip area array pitch (micron)
35353535353535Flying lead pitch (micron)
20202020202020Wire bond—wedge pitch (micron)
35353535353535Three tier pitch pitch (micron)
353535353535352-row staggered pitch (micron)
20202020202020Wire bond pitch—single in-line (micron)
Santa Clara Valley Chapter, CPMT Society
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March 23, 2006
Page 16
ConclusionsConclusionsScaling for conventional planar ICs is nearing its practical limitsAssembly and packaging is bridging the gap by enabling economic use of the 3rd dimensionSystem level integration is emerging as a driver of assembly and packaging solutions replacing single chip packaging A majority of materials used in packages in 2003 will be replaced before the end of this decade. Improved tools for co-design and simulation will be necessary to meet Roadmap requirements Cost is the greatest challenge for assembly and packaging
Thank You!
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