• Get together and head count
• General overview of firmware requirements
• Working environment and collaboration
• Functionalities and rough partitioning
• Work sharing and time schedule
Today
• Firmware development for the TEL62 must be a collaborative effort: Pisa will drive it, but contribution by at least 1 person per sub-detector is essential (need not be a firmware expert, but somebody willing to devote time to this)
• Mostly centered on TDC-daughtercard operation (but identify common blocks usable for LKr/L0 operation)
• Any sub-detector could be (in principle) L0-triggering or not
• Firmware will likely be (slightly) different for different sub-detectors: strictly confine sub-detector differences in few well-identified blocks.
Generalities
• Use a common development environment• Firmware must be centrally stored, consistent, modular, scalable and understantable to others besides the author• Strict name-space and memory-space constraints• Documentation is not an optional feature to be provided “later”, it must come with the code• Each firmware module must be simulated and should come together with its own test bench code• Live testing and diagnostic features should be incorporated
General principles
• The firmware is to be controlled – initialized – monitored from the CCPC (access during data taking possible)• Use only low-level libraries from LHCb (JTAG, glue, I2C, …) with frozen source code• Command-line control program (with scripting and macros) made available by Pisa: - tightly linked to firmware version- to be customized for sub-detector firmware versions- to be used both for test/monitoring and real data-taking- initialization via XML files • Scientific Linux version: to be frozen
• TEL62 firmware loading requires JAM-file player: existing LHCb version not working: to be solved – Perugia
Software
PP0
PP1
PP2
PP3
SL
CCPC(CPU)GLUE
TTCrx
Quad GbE
QDR
DDR
DDR
DDR
DDR
AUX
Daughtercard
(TDCB)
Daughtercard
(TDCB)
Daughtercard
(TDCB)
Daughtercard
(TDCB)
TEL62
DDR control
Data formatter and writer
Data extraction
Trigger handling
Trigger primitivegenerator
Core services & monitoring Inter-PP
communication
Dau
gh
terc
ard
co
mm
Dau
gh
terc
ard
DDR
Prev PP Next PP
SL
PP-FPGA
Dat
a co
rrec
tio
n
QDR control
Data formatter and writer
Gbithandling
TTCrx & trigger
handling
Core services & monitoring
AUX boardcommunication
PP
0 P
P1
PP
2 P
P3
QDR
TTCrx
SL-FPGA
Dat
a m
erg
er
Tri
gg
er
pri
mit
ive
mer
ger
Trigger primitivehandling
Gbit
Prev TEL62 Next TEL62
Run under Windows
• Use SVN with remote (CERN?) repository
• Choose tool versions and freeze to them
Software tools
Mentor GraphicsHDL Designer
Same tools as LHCb (newer versions):
AlteraQuartus II (v. 11 needed)
HDL Designer
• Steep learning curve(reading the manual might help)
• Interfaces to other tools (e.g. Modelsim simulator, Quartus)
• Hybrid graphical and VHDL (and Verilog) programming
• Allows simulation of the entire board (several FPGAs + other modules)
• Integrated versioning system (CVS, SVN, etc.)
PP-FPGA
SL-FPGA
Sub-detector specific versions later:pp_rich, pp_lav, etc.
Sub-detector specific versions (if needed) later: sl_rich, sl_lav, etc.
DDR control
Data formatter and writer
Data extraction
Trigger handling
Trigger primitivegenerator
Core services & monitoring Inter-PP
communication
Dau
gh
terc
ard
co
mm
Dau
gh
terc
ard
DDR
Prev PP Next PP
SL
PP-FPGA
Pisa
Perugia
Unassigned
(*)
(*) RICH version
Dat
a co
rrec
tio
n
QDR control
Data formatter and writer
Gbithandling
TTCrx & trigger
handling
Core services & monitoring
AUX boardcommunication
PP
0 P
P1
PP
2 P
P3
QDR
TTCrx
SL-FPGA
Dat
a m
erg
er
Tri
gg
er
pri
mit
ive
mer
ger
Trigger primitivehandling
Gbit
Prev TEL62 Next TEL62
Pisa
Perugia
Unassigned
PP
PP
PP
PP
SL
DD
RD
DR
DD
RD
DR
TDC
TDC
TDC
TDC
Gbit
QD
R
TTCrx
CCPCGLUE(ECS)
Simulation blocks
Pisa
Pisa
Pisa
Pisa
Pisa
Item Notes LHCb? Who Status
Core & monitoring Registers, memories, clocks, spy
YES/NO Pisa Started
Live test blocks Data transfer tests NO Pisa Started
Daughter-card comm For TDCB NO Pisa Started
Data correction Offsets, data manipolation NO
Data formatter/writer Time framing, counting NO Pisa
DDR control Burst writing/reading, arbitration NO Pisa Started
Data extraction Timestamp translation, framing NO Pisa
Trigger handling Trigger type handling, arbitration YES/NO Pisa
Trigger primitive gen RICH version (time multiplicity) Can be different for other SD
NO Perugia Started
Inter-PP comm Trigger primitive exchange NO
PP-FPGA FIRMWARE BLOCKS
Item Notes LHCb? Who Status
Core & monitoring Registers, memories, clocks, spy
YES/NO Pisa Started
Live test blocks Data transfer tests NO Pisa
Data merger Merge 4 PP data YES
Data formatter/writer Multi-event packets YES
Gigabit control Ethernet (as in TELL1 + receiver)
YES/NO
QDR control Burst writing/reading, arbitration YES Pisa
Trig primitive merger Merge 4 PP trigger data NO
Trig primitive handling
Merge other board trigger data,format, send to Gbit
NO
TTCrx handling Timestamps, trigger type, resets YES/NO Pisa
AUX-board handling Inter-board communication NO
SL-FPGA FIRMWARE BLOCKS
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