SystemEvolutionwith100GSerialIO
AliGhiasiGhiasi QuantumLLC
100Gb/s/LaneNEAMeetingNewOrleans
May24th,2017
Overviewq Since10GBASE-KRsupersetASICSerDes havesupportedC2M,C2M,andbackplane
applications– AddingKR/CRcapabilityprovidedasolutiontosupportCuDACandbackplanesmallpowerpenalty– ThesupersetKR/CRSerDes supportedC2Mpluggableoptics
q At112Gneedtoreconsiderourhistoricalarchitecturetomakesurethesystemiscostandenergyefficient
q Expect112GsignalingtobebasedonPAM4forfollowingreasons:– HigherordermodulationsuchasPAM8,PAM12,PAM16requirestrongerFECwithhigherlatencyandeco-
cancellerduetodiscontinuityinthechannels– MorecomplexFECandeco-cancellercan’tbeintegratedintolargeASICs– Anychip-to-modulesignalingotherthanPAM4requireaconvertorchipfor100GBASE-DRand400GBASE-DR4– AnyFECotherthanRS(544,514)requireFECterminationandinitiationinthemodulefor100GBASE-DRand
400GBASE-DR4withsignificantlatencyimpactq Consideringeco-systemrequirementthiscontributiononlyconsidersPAM4withKP4FECfor
112Gapplications!
A.Ghiasi 2NEAMeeting
The50G/laneInterconnectEcosystemsq OIFhasdefinedbothNRZandPAM4forMR,VSR,XSR,andUSRq IEEEP802.3bsandP802.3cdaredefiningPAM4signalingfor50G/laneChip-to-chip,chip-to-
module,CuDAC,andbackplane
A.Ghiasi 3
DefinedinIEEEandOIF
DefinedinOIF
1.OIFXSRdefinitionlikelytooshortforanypracticalOBOimplementation!
2.OIFVSR10cmreachassumes10cmmid-gradePCBbuttypicalimplementationusesMeg6/Tachyon100with~25cm!
NEAMeeting
Application Standard Modulation Reach LossBall-ball
LossBump-bump
Chip-to-OE(MCM) OIF-56G-USR NRZ <1cm 2dB@28GHz NA
Chip-to-nearbyOE(noconnector)
OIF-56G-XSR NRZ/PAM4
<7.5cm1 [email protected]@14GHz
[email protected]@14GHz
Chip-to-module(oneconnector)
OIF-56G-VSRIEEECDAUI-8
NRZ/PAM4PAM4
<10cm2<20cm
18dB@[email protected]
26dB@[email protected]
Chip-to-chip(oneconnector)
OIF-56G-MRIEEECDAUI-8
NRZ/PAM4PAM4
<50cm<50cm
35.8dB@[email protected]
47.8dB@[email protected]
Backplane(twoconnectors)
OIF-56-LRIEEE200G-KR4
PAM4PAM4
<100cm<100cm
[email protected]@13.3GHz
[email protected]@13.3GHz
3.Include2x6dBforpackagelossbut47.8dBseembeyondequalizationcapability4.Include2x3.5dBforpackageloss.
The100G/laneEco-Systemwillbefollow50GEco-system
q Withestimatedlossof18dBC2MspecificationisinlinewithourdefinitionofC2C– BumptobumplosscalculatedbyassumingASICpackagewith6dBlossandsmallCDRpackagehaving2dBloss– 6dBASICpackageassumes30mmtraceandrequiresmaterialbetterthanGZ41– PCBreachesbelowassumesTachyon100/Megtron 7– C2Mwith18dBlossismoreinlinewithcurrentC2CSerDes– ShouldweconsiderdefiningOBOand/orMCMapplications?
A.Ghiasi 4
Application Standard Modulation Reach Ball-BallLoss
Bump-BumpLoss
Chip-to-OE(MCM)
TBD PAM4 <1cm NA 2dB
Chip-to-nearbyOE(noconnector)
TBD PAM4 <10cm* 5dB
12dB
Chip-to-module(oneconnector)
OIF-112G-VSR
PAM4 <25cm 18dB 26dB
Chip-to-chip(oneconnector)
TBD PAM4 <38cm 20dB
32dB
CabledBackplane(twoconnectors)
TBD PAM4 <50cm 24dB 36dB
FocusofIEEE
OIFhasdefinedUSR/XSRbutwithlittletractionsofar!
PossiblyC2Ccanbemetwith24dBSerDes
*PracticalOBOimplementationrequires10cm!
NEAMeeting
ConventionalBackplanenoLongerFeasibleat100Gb/s!
q TEWhisper40”conventionalbackplaneat100Gb/sPAM4Nyquist hasalossof~65dB*q 1mcabledbackplaneisviablewithshortdaughter-card,ineffecteverylaneneedsaretimers!
A.Ghiasi 5
Even
HighPo
wer10G
Base-T
EQCan
equ
alize
theCh
anne
l
TEWhisperConventionalBackplane40”withMeg6HVLP*
100Gb
/sPAM
4
4”DCTraceEM-8887.7”DCTraceMeg6
TEWhisper1mCabledBackplane**
*TEWhisperchannel,http://www.ieee802.org/3/cd/public/channel/Reference_document_for_TE_Connectivity_Backplane_S-Parameter_Channels_07_28_16.pdf**Achieving100Gb/sChannels,DavidHesterTEConnectivity,OIF2016100Gb/sWorkshop.
NEAMeeting
Whendoweneed100Gsignaling?q Productbasedon112G/laneareexpectedtobedeployedby2021
A.Ghiasi 6
1"
10"
100"
1000"
1995" 2000" 2005" 2010" 2015" 2020" 2025"
Signa
ling"R
ate"o
n"Backp
lane"(
Gb/s)"
Year"
Serial'Bitrate'
1Gb
E_NRZ
XAUI-N
RZ
11G-NRZ 28
G-NRZ 56G-PA
M4
112G
/lan
e
224G
/lan
e
AddTXPre-emphasis
AddTXPre-emphasis
+CTLE&RX~5TapDFE
AddmoreDFETaps~12+LTEEQ**
**LTEEQ=LongTailEqualizerisalowfrequencyCTLEinadditiontoCTLEtobettercompensateforlowfrequencyconductorloss.
DSPImple.with
LongerFFE
10GBase-TTHPre-codingLDPCFEC
40”Megtron 7NotPractical!Viableoptions:
UsecableBackplaneOropticalbackplane
ReplaceWithcoaxcabled
BackplaneOropticalbackplane
TheendofConventionalBackplane
NEAMeeting
112GC2MChannels
q ConnectorassumedisYamachi CFP2whichiscapableof53GBd operationotherconnectorspotentiallycouldbeimprove– VSRchannellossinvestigatedwithfollowingmaterial
408HR,Megtron 6HVLP,TachyonHVLPfor5.5mil½oz stripline
– Tostaywith56G-VSRlosslimitof10.5dBthehostPCBtracewillbe<75mmandevenwithultralowlossmaterialtheendtoendlosswillbe~19.5dB(7dBforhostASICand2.0dBCDR)!
– CTLEreceiverisnolongeranoption– BettertouseC2Creceiverandgolittlelonger
forPHYless design– With~18dBloss125-250mmofhostPCBcan
besupportedwithend-endlossof27dB• Inlinewith50GC2Cdefinition.
A.Ghiasi 7
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0 5 10 15 20 25 30 35 40 45 50
Loss(d
B)
Frequency(GHz)
Connector
408HR_3in
408HR_10in
Meg6_3in
Meg6_10in
Tach_3in
Tach_10in
10”Trace
3”Trace
50Gbp
sPAM
4
100Gb
psPA
M4
Connector
NEAMeeting
ExtendingCuDACOperationfrom50to100Gbpsq Constructionofthehypothetical100Gb/sCuDAC
– De-embedMolexzQSFP cableresponsethenbuildahypotheticalDACwithYamaichiCFP2connector– Hypothetical2mCuDACwith10”tracehasend-endlossof~54dB(assuming2x~7dBASICpackage)– Insteada3”hostTachyon100with2mcablehasend-endlossof~37dB(assuming2x~7dBASICpackage)– AhighendDSPretimer couldprovideapassiveCuDACsolutionfor2mwith<3”hostbutwillbecostlyandhighpower– Abettersolutionistogowith<10”PCB(PHY-less)andinsteadreplacepassiveDACwithactiveDACorAOC.
A.Ghiasi 8
50Gb/sK
P4RS(54
4,51
4)
FECNyquist=13.27
5GH
z
11.3dB
14.2dB
100Gb
/sKP4
RS(54
4,51
4)
FECNyquist=26.55
GHz
ConnectorRelated
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
Loss(d
B)
Frequency(GHz)
Connector
408HR_3in
408HR_10in
Meg6_3in
Meg6_10in
Tach_3in
Tach_10in
2mCable
100Gbps PAM4Support2mWith3”HostPCB
50Gbps PAM4Support2-3mWith10”HostPCB
*zQSFP cabledata,http://www.ieee802.org/3/50G/public/Jan16/roth_50GE_NGOATH_01a_0116.pdf**CFP2connector,http://www.ieee802.org/3/400GSG/public/13_05/nishimura_400_01a_0513.pdf
NEAMeeting
EvolutionofFrontPanelPorts
q OptionI– PHYlessdesign– Doesn’tsupportpassiveCuDAC– Switchdirectlydrivespluggablemodule,activeCuDAC,orAOC– Support10”ofMegtron 7/TachyonPCB– Offersimprovepowerandcost– Betteroverallchoiceasindustrytransitiontowardfibercentric
q OptionII– RequirePHYclosetoeverymodule– SupportspassiveCuDAC,activeDAC,andAOCSupport3”of
Megtron 7/TachyonPCB• FlyovercablecanextendthePHYtomoduledistancebutaddscost
andmanufacturabilityissues– SupportsActiveCuDACandopticalmodules– Retimer addssignificantcostandpower.
A.Ghiasi 9
q PHYlessdesign– whatweareusedto– SupportspassiveCuDAC– Switchdirectlydrivesopticalmodules– Switchdirectlydrives3mofCuDAC
– Offersoptimumpowerandcost.
Pluggableat25Gb/sand50Gb/s Pluggableat100Gb/s
NEAMeeting
1RU/TORImplementationq GiventhatopticalPMDs/AOCuseretimer adding2nd retimer/CDRonthehost
portaddunnecessarypower
A.Ghiasi NEAMeeting 10
SwitchC2M~10”
~4”
SwitchC2M~10”
~4”CDR
CDRCDR
NotPreferred! Preferred!
ChassisImplementationq Tosupportapractical
sizechassismostlinkwouldrequirearetimer/CDR
q InthetimeframeofconsiderationweshouldnotruleoutOBOandopticalbackplanes!
A.Ghiasi 11
Port ASIC
Port ASIC
Optical Backplane
Fabric ASIC
Fabric ASICC2O
BO
Port ASIC*
Port ASIC*
Cu Backplane
~10-
25 c
m
OSFP/QSFP-DD
Fabric ASIC
Fabric ASIC
C2M
OSFP/QSFP-DD
C2M
OBO
C2O
BO
OBO COBO
OBO
OBO
OBO
*Retimer/CDR
R*
R*
NEAMeeting
Summaryq The100G/lanewilloffermoreefficientASICinterfacebydoublingtheswitchBW
– OSFP/QSFP-dd orQSFP112with100Gb/s/lanesignalingcoulddeliver14.4-25.6Tb/sfrontpanelBW– Thedownsideof100G/laneIOarelackof10kmPMDand850nmMMFPMDssupportasthesePMDsmayrequire
operationat50Gb/s/lanewithinverseMuxq Giventhatat100Gb/s/lanesupportingconventional1mbackplaneor3mpassivecablenolonger
feasibleonemustfirstconsiderthearchitecturalimpact– Conventionalbackplanelikelywillbereplacedwithcabledbackplane,useMegtron 7/Tachyon100onashort
backplane<50cmlinecard tofabric,addextraretimer toextendthereach,oruseopticalbackplane– Weneedtofocusonanenergyefficient,costeffective,synergisticsolution– PLEASENO100GBASET!– InsteadoftryingdefineaheroicpassiveCuDACsolution,itwouldbesimplerandmoreeconomicaltouseactiveCu
DACorAOCq Giventhat100GBASE-DRand400GBASE-DR4arebasedonPAM4withKP4FECanyothersignalingand/or
FECwouldrequirePHYlayeraddingcomplexityandlatency– PotentiallyactiveCuDACmayuseinternallyothersignaling
q Thetransitiontoserial100G/lanewillnotbesmoothlike50G/lanetransition– EvenwithmateriallikeMegtron 7orTachyon100C2Mlosswillbe~18dBrequiringaC2Clikeequalizer– Wecan’trollruleoutOBOorco-packageat100Gb/s/lane– ShouldweconsiderdefiningC2OBOinterface
q Whathasworkedat25G/50Gmaynotbetheoptimumsystem/ASICpartitionat100G/lane!A.Ghiasi 12NEAMeeting
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