STM32: Peripherals
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November 28, 2019
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STM32 System Architecture
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STM32 System Architecture
S0: I-bus: This bus connects the Instruction bus of theCortex-M4 core to the BusMatrix. This bus is used by the coreto fetch instructions. The targets of this bus are the internalFlash memory, the SRAM and the Core Cupled Memory(CCM) RAM.
S1: D-bus: This bus connects the DCode bus of theCortex-M4 core to the BusMatrix. The targets of this bus arethe internal Flash memory, the SRAM and the CCM RAM.
S2: S-bus: This bus connects the system bus of theCortex-M4 core to the BusMatrix. This bus is used to accessdata located in the peripheral or SRAM area. The targets ofthis bus are the SRAM, the AHB to APB1/APB2 bridges, theAHB IO port and the ADC.
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STM32 System Architecture
S3, S4: DMA-bus: This bus connects the AHB masterinterface of the DMA to the BusMatrix which manages theaccess of di�erent Masters to Flash, SRAM and peripherals.
The DMA (Direct Memory Access) is a peripheral thattransfer data between peripherals and memories withoutinvolving the CPU.
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Memory map
Peripherals are memory mapped
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Memory map
General purpose input/output
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Memory map
Reset and clock control (RCC)
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Memory map
External Interrupt
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Memory map
The SRAM represents only a "tiny" part of the memorymapping!
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Reset and clock control (RCC)
System clock (SYSCLK) selection (three di�erent clocksources):I HSI 8 MHZ RC oscillator clockI HSE oscillator clockI PLL clock
RCC registers allow to enable the use of a particular peripheralI When the peripheral clock is not active, the peripheral register
values may not be readable by software and the returned value
is always 0x0.
RCC_AHBENR, RCC_APB1RSTR, RCC_APB2RSTR
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Interrupts
Programs are executed sequentially (one instruction after theother). But a computer that can only execute a prede�nedprogram is not very usefulI We need to introduce the possibility to interact with the
external world
The interaction is obtained introducing the concept ofinterrupt
Interrupts are external (or internal) events that modify theexecution �ow of the program
Many examples that we use every day:I TouchscreenI KeyboardI Temperature controlI ...
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Interrupts
Interrupts are associated to special events
When these events occur, the CPU stops executing its mainprogram and starts executing a speci�c Interrupt ServiceRoutine (ISR) associated to the speci�c interrupt
When the ISR terminates its execution, the main program isresumed from where it was left
Interrupt Service Routines are quite similar to functions, butthey also have big di�erences:I They are always associated to a speci�c interrupt. Each
interrupt has its own ISR.I They are executed only if the associated interrupt occurs.I The addresses of all the ISRs are stored inside the Interrupt
Vector Table
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Interrupts
They can be synchronous or asynchronous:I Synchronous interrupt: it is triggered by the software.
Example: illegal instruction, division by 0.I Asynchronous interrupt: it is triggered by an external event.
For this reason, it can interrupt the execution of the codewithout waiting that the current instruction ends its execution.Example: external reset, push-button.
They can be maskable or unmaskable:I Maskable interrupts: they can be enabled/disabled by
software.I Unmaskable interrupts: they cannot be disabled by software.
Example: external reset, system failure.
Each interrupt has a priority level: if a high priority interruptis triggered while the ISR of a low priority interrupt is beingexecuted, this stops its execution and the higher priority ISR isexecuted.
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Managing peripherals
Peripherals can be managed resorting to two strategies:I InterruptI Polling
In the interrupt approach the CPU waits for the peripheral tosend an interrupt and notify that something happened
In the polling approach, the CPU continuously checks ifsomething new happened on the peripheral (massive usage ofloops)
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Polling VS InterruptINTERRUPT POLLING
BasicDevice notify CPU
that it needs CPU attention.
CPU constantly checksdevice status whether
it needs CPU's attention.
MechanismAn interrupt is a
hardware mechanism.Polling is a Protocol.
ServicingInterrupt handler
services the Device.CPU services the device.
IndicationInterrupt-request lineindicates that deviceneeds servicing.
Comand-ready bit indicatesthe device needs servicing.
CPUCPU is disturbed only
when a device needs servicing,which saves CPU cycles.
CPU has to wait and check whether adevice needs servicing whichwastes lots of CPU cycles.
OccurrenceAn interrupt canoccur at any time.
CPU polls the devicesat regular interval.
E�ciency
Interrupt becomes ine�cientwhen devices keep
on interrupting the CPUrepeatedly.
Polling becomes ine�cientwhen CPU rarely �nds adevice ready for service.
ExampleLet the bell ring
then open the door tocheck who has come.
Constantly keep on openingthe door to check whether
anybody has come.
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Example: Using user button on STM32 in polling
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Example: Using user button on STM32 in polling
Once the button activated, the CPU has to verify periodicallywhether the button was pressed or not.I Create a function which reads the state of the GPIO port input
data register (GPIO_IDR)I Invoke the function periodicallyI if you �nd a speci�c value, then it means that the button was
pressed and a speci�c action can be performed (e.g., you canswitch on/o� a led)
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Interrupts scheme
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Interrupts
Nested vectored interrupt controller (NVIC) main featuresI 74 maskable interrupt channelsI A programmable priority level of 0-15 for each interrupt. A
higher level corresponds to a lower priority, so level 0 is thehighest interrupt priority
I Low-latency exception and interrupt handling
The NVIC and the processor core interface are closely coupledI this enables low latency interrupt processing and e�cient
processing of late arriving interrupts.
All interrupts including the core exceptions are managed by theNVIC.
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Interrupt Vector Table
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EXTI
Extended interrupts and events controller (EXTI)
Manages the external and internal asynchronousevents/interrupts and generates the event request to theCPU/Interrupt Controller and a wake-up request to the PowerManager.
An interrupt could be left pending;I for external interrupts, a status register indicates the source of
the interrupt;I for internal interrupts, the pending status is assured by the
generating peripheral, thus no need for a speci�c �ag.
Each input line can be masked independently.
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External and internal interrupt/event line mapping
36 interrupt/event lines areavailable: 8 lines are internal(including the reserved ones); theremaining 28 lines are external.
The GPIOs are connected to the 16external interrupt/event lines in thefollowing manner:
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Con�guring Interrupts
For the external interrupt lines the interrupt line should becon�gured and enabled.I This is done by enabling the interrupt request by writing a "1"
to the corresponding bit in the interrupt mask register(IMR).
When the external interrupt line receives a signal, an interruptrequest is generated and the corresponding pending bit is alsoset.
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Con�guring Interrupts
In practice, to con�gure a line as interrupt source, use thefollowing procedure:I Con�gure the system controller to manage the external
interrupt line connection to the GPIOsI Con�gure the corresponding mask bit in the EXTI_IMR
register.I Con�gure the Trigger Selection bits of the Interrupt line
(EXTI_RTSR and EXTI_FTSR).I Write the Interrupt Service Routine.I Clear the pending request.
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External and internal interrupt/event line mapping
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External and internal interrupt/event line mapping
Enable SYSCFG clock
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External and internal interrupt/event line mapping
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Con�guring Interrupts
Con�gure the corresponding mask bit in the EXTI_IMRregister:
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Con�guring Interrupts
Con�gure the Rising Trigger Selection bits of the Interruptline (EXTI_RTSR)
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Con�guring Interrupts
Con�gure the Falling Trigger Selection bits of the Interruptline (EXTI_FTSR)
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Con�guring Interrupts
Write theInterruptService Routine(Vector Table)
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Con�guring Interrupts
Con�gure the NVIC Interrupt set enable register (NVIC_ISER)to activate the interrupt
This will "wake up" (interrupt) the processor, asking it toserve the request
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Con�guring Interrupts
Find the Name of the Interrupt service routine (ISR)
Write your ISR with the same name to perform an action.
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Con�guring Interrupts
Clear the pending request.
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