Stability Measurement of 3 CSOs with Tracking DDSs and Two-Sample COV
10 GHz CSOs • 2×10–16…10–15 ADEV
at 1…105 s• Not tested at 100 MHz
C. E. Calosso1, F. Vernotte2,3, V. Giordano2,3, C. Fluhr4, B. Dubois4, E. Rubiola1,2,3
1 INRIM, Torino, Italy, 2 Besançon Observatory, France 3 FEMTO-ST Institute, France, 4 FEMTO Engineering, France
TDDS •2×10–14/τ ADEV
at 100 MHz•Statistical limit?
Motivations and Outline
Let’s put all things together and play
Statistics •Scalable•Challenging instrument
and oscillators
http://rubiola.org1
French and Italian National Research Councils
Liquid-He Sapphire Oscillator
• 3 units in Besancon (one is transportable, stability & noise validated after roundtrip)• Others: 1 at ESA, Malargue, 3 at a US GOV lab • µHz-resolution synthesis
2
T2>T1
T1 nESR
nESR
Cr3+ Fe3+ dopedAl2O3 mono crystalϕ ≈ 5 cm, H ≈ 3 cm
nESR
frequencyT
Magnetic Susceptibility
0.1 ppm
0.2 ppm
20
10
0
30
∆ƒ, Hz
40
WGH16,0,0 mode at 11.565 GHz
5 6 7 8
temperature, K
Whispering Gallery H mode
HE
Paramagnetic temperature compensation
10 GHz resonanceQ ≈ 2×109 at 5–7 K
Pound-Galani Oscillator
• Pound frequency lock to the cavity• The same cavity is used in the VCO
ƒm
control
out
PM
oscillator loop
powerdetector
ν0 Q
VCO
V ~ ν–ν0
conductance
supporting rods
copper
braids
Temperature
stabilised plateGold plated
cavity
Top flange
Cold head
4K stage
low thermal
70K stage
Mechanical & Thermal EngineeringLow-vibe cryogenerator
< 2 µm displacement @ 1Hz
Cold finger temperature stability 100 mK pkThermal ballast
Low acceleration sensitivity
3
First generation: 6kW three-phaseCurrent generation: 3 kW mono-phase
Frequency Synthesis 4
10 GHz
10±3 MHz
DC
÷20
LPx4 BP
÷4 ÷10
÷10
LP
100 MHzoutputs
5 MHzoutputs
10 GHzoutputs
Directoutput
CSO9.99 GHz
input
LP
2.5 GHz
DRO 10 GHz
DDS250 MHzword
DDS control
10 GHz
LP
5 MHz
100 MHz
10 GHz–10±3 MHz
HF/
VHF
out
heterodyne PLL
48 bit DDS9x10–17 resolution 0.9 µHz at 10 GHz
Key points • Resonator engineering
10 GHz – 10 MHz ±3 MHz• Small frequency offset
DDS is OK• Uneven frequencies
No crosstalk
Tracking DDS —> Digital PLL 5
b–1 = –110 dBrad 2
b0 = –154 dBrad2/Hz
Mixer, Amplifier, and ADC
Clock distribution
AD9912
TDDS —> M. Calligaris, G. A. Costanzo, C. E. Calosso, Proc 2015 IFCS pp.681-683
Noise budget at 100 MHz
DDS Noise —> C. E. Calosso, Y. Gruson, E. Rubiola, Proc 2012 IFCS p.777-782
Trivial estimator forslow sampling (ƒs = 10 Hz)
x(t)^
DDSφ control
estimator
ADC'
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E.Rubiola, 2019
clock
phasecontrol
phase time
in
x̂<latexit sha1_base64="lFgBw3JF8CZU79CB4oaVZ2Yip/4=">AAAB+nicZVDLSsNAFL3xWeur6sKFm8FWcFFKErHalQU3LivYVmhKmUwn7eBMEmYmYon5GV2JuvMz/AH/wk8wSSv4ODDM4dx7ufccN+RMadP8MObmFxaXlgsrxdW19Y3N0tZ2RwWRJLRNAh7IaxcryplP25ppTq9DSbFwOe26N+dZvXtLpWKBf6UnIe0LPPKZxwjWqTQo7VacMdax44rYEViPlRffJUlSGZTKZs3MgX6QY9Nq1C1kzZTy2SfkaA1K784wIJGgviYcK9WzzFD3Yyw1I5wmRSdSNMTkBo9oL6U+FlT149xAgg5SZYi8QKbP1yhXf07EWKjsumr6Zx0qI2oi3KorqllBKk/92aG9037M/DDS1CfTFV7EkQ5QlgMaMkmJ5pOUYCJZeiUiYywx0Wlaxdx+o2Hb9SP0n3zb79g166hmX9rlpj3NAQqwB/twCBacQBMuoAVtIJDAI7zAq3FvPBhPxvO0dc6YzezALxhvXzHVlmA=</latexit>
'̂<latexit sha1_base64="1SBlzFdPSB0rJQrj+HWNOo2g64s=">AAAB93icZVDbSsNAEJ14rfVWL2++LLaCD6UkES99suCLjxVsK5hQNttNu3Q3CbubQgz9Fn0S9c3/8Af8Cz/BJFXwcmCYw5kZZuZ4EWdKm+a7MTe/sLi0XFopr66tb2xWtra7KowloR0S8lDeeFhRzgLa0UxzehNJioXHac8bX+T13oRKxcLgWicRdQUeBsxnBOtM6ld2a84I69TxROpMsIxGbDqt9StVs2EWQD/IsWk1TyxkfSnV8w8o0O5X3pxBSGJBA004VurWMiPtplhqRjidlp1Y0QiTMR7S24wGWFDlpsX1U3SQKQPkhzKLQKNC/TmRYqEE1qN6lvMOlROVCK/uiXpekMpXf3Zo/8xNWRDFmgZktsKPOdIhyk1AAyYp0TzJCCaSZVciMsISE51ZVS7ebzZt++QI/Sff73fthnXUsK/sasue+QAl2IN9OAQLTqEFl9CGDhC4gwd4hhcjMe6NR+Np1jpnfM3swC8Yr5+N15TZ</latexit>
÷ D
FPGA
700 fs jitterσ
y(τ)=1.5×10 -14
@ 1 s, ƒH = 5 Hz
x-type PM noise
Flicker: √k-1 = 5 fs
AD9912 DDS: Time-Type Noise at ≥ 5 MHz 6
C. E. Calosso, E. Rubiola, Phase Noise and Jitter in Digital Electronics, arXiv:1701.00094 [physics.ins-det]DDS Noise —> C. E. Calosso, Y. Gruson, E. Rubiola, Proc 2012 IFCS p.777-782
Trivial estimator forslow sampling (ƒs = 10 Hz)
x(t)^
DDSφ control
estimator
ADC'
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E.Rubiola, 2019
clock
phasecontrol
phase time
in
x̂<latexit sha1_base64="lFgBw3JF8CZU79CB4oaVZ2Yip/4=">AAAB+nicZVDLSsNAFL3xWeur6sKFm8FWcFFKErHalQU3LivYVmhKmUwn7eBMEmYmYon5GV2JuvMz/AH/wk8wSSv4ODDM4dx7ufccN+RMadP8MObmFxaXlgsrxdW19Y3N0tZ2RwWRJLRNAh7IaxcryplP25ppTq9DSbFwOe26N+dZvXtLpWKBf6UnIe0LPPKZxwjWqTQo7VacMdax44rYEViPlRffJUlSGZTKZs3MgX6QY9Nq1C1kzZTy2SfkaA1K784wIJGgviYcK9WzzFD3Yyw1I5wmRSdSNMTkBo9oL6U+FlT149xAgg5SZYi8QKbP1yhXf07EWKjsumr6Zx0qI2oi3KorqllBKk/92aG9037M/DDS1CfTFV7EkQ5QlgMaMkmJ5pOUYCJZeiUiYywx0Wlaxdx+o2Hb9SP0n3zb79g166hmX9rlpj3NAQqwB/twCBacQBMuoAVtIJDAI7zAq3FvPBhPxvO0dc6YzezALxhvXzHVlmA=</latexit>
'̂<latexit sha1_base64="1SBlzFdPSB0rJQrj+HWNOo2g64s=">AAAB93icZVDbSsNAEJ14rfVWL2++LLaCD6UkES99suCLjxVsK5hQNttNu3Q3CbubQgz9Fn0S9c3/8Af8Cz/BJFXwcmCYw5kZZuZ4EWdKm+a7MTe/sLi0XFopr66tb2xWtra7KowloR0S8lDeeFhRzgLa0UxzehNJioXHac8bX+T13oRKxcLgWicRdQUeBsxnBOtM6ld2a84I69TxROpMsIxGbDqt9StVs2EWQD/IsWk1TyxkfSnV8w8o0O5X3pxBSGJBA004VurWMiPtplhqRjidlp1Y0QiTMR7S24wGWFDlpsX1U3SQKQPkhzKLQKNC/TmRYqEE1qN6lvMOlROVCK/uiXpekMpXf3Zo/8xNWRDFmgZktsKPOdIhyk1AAyYp0TzJCCaSZVciMsISE51ZVS7ebzZt++QI/Sff73fthnXUsK/sasue+QAl2IN9OAQLTqEFl9CGDhC4gwd4hhcjMe6NR+Np1jpnfM3swC8Yr5+N15TZ</latexit>
÷ D
FPGA
The 6-Channel TDDS 7
DDS
Clock
Cyclone III FPGA
VoCore2 Linux computer (back side)
DC/DC & voltage regulator
Thermally symmetric design
12 V, 10 W supply
Mixer
SMA input connectors
6 TDDSs, control unit, and interface in a small instrument
Ethernet
RS-232
Thermal Image 8
Small dissipation and thermal symmetry improve phase stability
Statistics
TIC /ϕM12
TIC /ϕM34
TIC /ϕM56
A
B
C
x12
x34
x562
)()(),( ττ
−−≡
tytytz
tttyd)(d)( x
=
02)()(
πυ
ϕ tt =x
][E)(, AByy zzBA
=τσ
2-Sample COV
Bx 2xBAx 21x 21nx
By 2yBAy 21y 21ny
Bz 2zBAz 21z 21nz
2Bσ
2BAσ
AB,σ
21σ
221σ 2
21nσ
Oscillator Instrument
Single DeltaOutputSingle Delta
Noi
se
9
AVAR][E)( 22 zy =τσ
Time Interval Counters
Statistical ToolsTIC /ϕM
12
TIC /ϕM34
TIC /ϕM56
A
B
C
x12
x34
x56 ⎪⎩
⎪⎨
⎧
=
=
=
][E][E][E
256
2
234
2
212
2
zzz
CA
BC
AB
σ
σ
σ
23421 ][E Bzz σ=
3-Cornered Hat
2-Sample COV
][E21 2
56234
212
2 zzzB −+=⇒σ
3-cornered hat with noise-free instruments
Noisy Instruments
][21][E
21 2
56n243n
212n
2256
234
212 σσσσ −++=−+ Bzzz
10
At 100 MHz the Time Interval Counter is not an option
background noise —> 0
1
2
3
4
5
6
x1
x6
x2
x3
x4
x56-
chan
nel
Trac
king
DD
S
A
B
C
2-Sample COV with TDDS 11
2kj
ijkizz
zz+
−=←
Channels remapping ][E 45322 zzB =σ
][E 5641232 zzB =σ
][E21
5631245641232 zzzzB +=σ
First improvement
Second improvement
• Expand all terms • Look at convergence laws • Room for improvement
We use this —>
x1
x6
x2
x3
x4
x5
6-ch
anne
l Tr
acki
ng D
DS
A
B
C
• Lange / K&K counters• 10 GHz outputs• Different beat notes
prevent crosstalk
Synt
h.Sy
nth.
Synt
h.
Cou
nter
ϕAB
ϕBC
ϕCA
12
• INRIM 6-Ch TDDS• 100 MHz outputs• 2-sample covariance
3-cornered hat classical)
2-sample COV (new)
Experiment
13
Time Domain and ADEV 14
TDDS
CSOs drift
not re
moved
CSOsdrift removed
correlated thermal effects
2-COV vs 3-CH 15
100 MHz outputs 6-Ch TDDS2COV Algorithm
≈10 GHz outputs HF beat notes (1…10 MHz)Lange/K&K Counters3CH Algorithm
10GHz —> 100 MHz synthesizer affects short-term (≤100 s) stability
2COV algorithm and 3CH give the same result
Conclusions (1) 16
Achieved • Full validation of the 100
MHz output• 5–400 MHz TDDS range
New TDDS in progress • 12 channels•Composite clock, 2×10–14/τ
DDS limit•Cable-length compensation
at the output
ABCC (neg)
averaging limit 8×10 –16/τ 3/4
Ove
rlapp
ed A
DEV
A
B C B
AC
B
AB
2.1×10 –14/τ, two channels
τ, s
100 MHz carrier
Conclusions (2)
♇☿♁
♃̧
♄☾ ̦ ♆⛢
semi-major axes
1-m
G s
hift
at g
nd le
vel
ABCC (neg)
8×10 –16/τ 3/4Ove
rlapp
ed A
DEV
A
B C B
AC
B
AB
2.1×10 –14/τ, two channels
17
τ, s
100 MHz carrier Oscillator • A probe for the Solar
System and for Fundamental Science• A (traveling) standard of
ADEV
TDDS • Defines the state of the
art in the measurement of ADEV
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