8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part1
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
LOW DROP OUT REGULATOR DESIGN (PART-1)
Objective:
Open Loop Amplifier circuit design with gain of 50-60 dB and basic feedback analysis of LDO
circuit.
Schematic:
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
Maximum current to the load=50 mA
Reason for Using PMOS buffer and PMOS pass transistor:
PMOS Buffer:
PMOS buffer is used because there will be better matching between the cascade amplifier stageand the Buffer stage.PMOS buffer is preferred as substrate and source are at same potential and
in NMOS source and bulk are at different potential.
Pass Transistor
PMOS pass transistor is used since Vin and Vreg vary by small amount (.25V) and NMOS
cannot be used as gate voltage (2.25+Vtn) needed for this purpose have to be greater than
maximum voltage available i.e. 2.5V and it requires a charge pump.
DC biasing of the amplifier and theoretical calculation of AC gain is shown in the next page.
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
AC analysis:
As observed from the above plot, the low frequency small signal gain is 56.02 dB and the 3 dB
bandwidth is 817.8 KHz.
8/13/2019 Srikanth Reddy Paramaiahgari 1206321047 Project Part1
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
Rin:
Rout:
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
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EEE 591: Analog Integrated Circuits Srikanth Paramaiahgari ASU ID# 1206321047
Simulation Vs Hand Analysis:
AC analysis:
Gain Rin Rout Bandwidth
Hand Analysis 57.01 dB 6.39 M Ohms 156 KHz
simulation 56.02 dB 1.4 G Ohms 6 M Ohms 817 KHz
Differences in simulations when compared to theoretical calculations are due to approximations made
in the Gain, Rout and Cout Equations. And also the body effect and channel length modulation effects
are ignored.
Some optimizations were made in the circuit to achieve the gain of 56 dB. The cascode stage transistors
Veff was decreased from 100 mV to 80 mV so as to increase the gain.
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