Real-Time Simulation: Applications to More Electric Aircrafts
EmbraerMarch 10, 2010
Christian Dufour, Ph.D. Senior Simulation Specialist, Power Systems and Drives
Lecture Plan
2
About More Electric Aircraft
Real-Time Simulator Technology update
Onboard Ship Power System example.
Power Electronic Simulation on RT-LAB
Tools for Electric System Simulation
Conclusions
Test Automation and Sequencer
3
About more electric aircrafts
4
Why More Electric Aircrafts?
Efficiency Bleedless engine design can provide for
energy saving during flight. Not so obvious: MEA is heavier than
normal plane
5
Classic airplane power distribution (A320)
Propulsion (trust): 20MW Electrical (200kW)
Avionics, lights, fans, In-flight entertainment Pneumatic 1.2MW
Cabin pressurization, Air conditioning, Icing protection
Hydraulics (240 kW, at peaks) Surface actuation, landing gear operation,
braking, doors Mechanical
Fuel and oil pump local engine
6
Example of a More Electric Aircraft: Boeing 787
Boeing 787 All onboard systems are electric: APU, Brakes,
Cabin pressurization, Wing ice protection With 4 primary 230 VAC, 3ph, variable
frequency Generators with 230/115V AC and 28 VDC busses.
Bleedless engines
7
Possible all-DC Bus MEA
Highly redundant configuration Composed of many power converters
Source: Virginia Polytechnic
8
Real-time simulation basics
Real-Time Simulation : Introduction
Free Running Simulation
Faster than real-time
Slower than real-time
Time
Computationf(t) Time
tn-1 tn
f(tn+1)
tn+1
f(tn)
Time
Computationf(t)
tn-1 tn
f(tn+1)
tn+1
f(tn) Time
9
Real-Time Simulation : Introduction
Real-Time Simulation
Data Posting
TimeClock
Computationf(t) Time
tn-1 tn
f(tn+1)
tn+1
f(tn)
10
Sine equa none conditions for real-time algorithms
Non-iterative
Fixed –step (disqualify Spice-type or Saber simulation algorithm for example)
IMPORTANT DISTINCTION
In real-time simulation, ALL time step must complete below Ts
Consequently, even if the total calculation time is smaller than the real time to compute, it may not meet real-time criteria
Controlled Process: a plant and its controller
Main Real-Time Simulation Applications: RCP and HIL
RCP: the controller is implemented using a Real-Time Simulator HIL: the controller is tested with a plant model on a Real-Time Simulator
RT-LAB
+ -
Controller
Rapid Control PrototypingHardware-in-the-Loop
+-
Motor
RT-LAB
Evolution of Real-Time Simulator Technology
13
1960 1970 1980 1990 2000
Digital COTSSimulators
Digital COTSSimulators
COTSSim-On-Chip
COTSSim-On-Chip
Digital CustomSimulators
Digital CustomSimulators
AnalogSimulators
AnalogSimulators
Model Based Design
Hybrid (Analog/Digital)Simulators
Hybrid (Analog/Digital)Simulators
197530000 square feet Hybrid Simulator
RT-LAB
2009: 1 cabinet, 3 PC with 24 core in total
32 to 64 cores would be required to simulate the detailed HQ network
Controller Model Design
(Simulink Block Diagram)
Generate Software from
Model
Upload Software to Real-Time Simulation
Platform
Correct Design Iteratively
About the Concept of Model-based Design (simplified)
14
Test
Motorized WheelsDeliver Traction effort
AlternatorGenerates the electrical power
AC Control GroupControls engine load and power flow
Chopper AssemblyDissipates superfluous energy during breaking
Example #1: Off-Highway Vehicle (GE-OHV)
I/O
Example #1: Off-Highway Vehicle (GE-OHV)
RT-LAB TestDrive (LabView Based Interface)
Actual ECU
Truck model include: Dynamics Inverters Motors Drives (IM) Alternator DC-bus DC-bus choppers Etc..
PCMNV acload
PCMNV dcload
PCMVitalload
PCMVitalload
PCMNV dcload
PCMNV acload
PGMPCM
PCM
PCM NV acload
PCM NV dcload
EPM M
PCM NV dcload
PCM NV acload
EPM M
Port Bus
Starboard Bus
Generator Group
Load Group1 on Port Side
Load Group1 on Starboard Side
Load Group2 on Port Side
Load Group2 on Starboard Side
Zone 1
Load Group 1 on Port Side
Load Group 2 on Port Side
GeneratorGroup
Load Group 1 on Starboard Side
Load Group 2 on Starboard Side
Zone 2
Load Group 1 on Port Side
Load Group 2 on Port Side
GeneratorGroup
Load Group 1 on Starboard Side
Load Group 2 on Starboard Side
Zone 3
Load Group 1 on Port Side
Load Group 2 on Port Side
GeneratorGroup
Load Group 1 on Starboard Side
Load Group 2 on Starboard Side
Zone 4
SW
-G1
SW-P1S
W-G
2
SW-S1
SW-P2
SW-S2
SW-P3
SW-S3
Fault Location 1
Fault Location 2
17
Example #2: All electric ship
Yanhui Xie Seenumani, G. Jing Sun Yifei Liu Zhen Li , “A PC-Cluster Based Real-Time Simulator for All-Electric Ship Integrated Power Systems Analysis and Optimization”, Electric Ship Technologies Symposium, 2007. ESTS '07. IEEE , Arlington, VA., 21-23 May 2007 pp. 396 - 401
Characteristics: Highly redundant reconfigurable power system Composed of many drives including propulsion Many power converters and switches
PCMNV acload
PCMNV dcload
PCMVitalload
PCMVitalload
PCMNV dcload
PCMNV acload
PGMPCM
PCM
PCM NV acload
PCM NV dcload
EPM M
PCM NV dcload
PCM NV acload
EPM M
Port Bus
Starboard Bus
Generator Group
Load Group1 on Port Side
Load Group1 on Starboard Side
Load Group2 on Port Side
Load Group2 on Starboard Side
Zone 1
Load Group 1 on Port Side
Load Group 2 on Port Side
GeneratorGroup
Load Group 1 on Starboard Side
Load Group 2 on Starboard Side
Zone 2
Load Group 1 on Port Side
Load Group 2 on Port Side
GeneratorGroup
Load Group 1 on Starboard Side
Load Group 2 on Starboard Side
Zone 3
Load Group 1 on Port Side
Load Group 2 on Port Side
GeneratorGroup
Load Group 1 on Starboard Side
Load Group 2 on Starboard Side
Zone 4
SW
-G1
SW-P1
SW
-G2
SW-S1
SW-P2
SW-S2
SW-P3
SW-S3
Fault Location 1
Fault Location 2
18
Test case: ZONE 1 - PORT BUS - DC FAULT
Starboard Bus
ZONE 1
Fault applied from t = 0.1s to t = 0.4s
Port Bus ZONE 1 ZONE 2
19
All-Electric Ship Real-time Simulation Performance
Zone 1Load
Group 1
Shared Memory
Zone 1Generator
Group
Zone 1Load
Group 2
Zone 2Load
Group 1
Zone 2Generator
Group
Zone 2Load
Group 2
CPU1 CPU2 CPU3
CPU4 CPU5 CPU6
Target 1
Zone 3Load
Group 1
Shared Memory
Zone 3Generator
Group
Zone 3Load
Group 2
Zone 4Load
Group 1
Zone 4Generator
Group
Zone 4Load
Group 2
CPU1 CPU2 CPU3
CPU4 CPU5 CPU6
Target 2
PC
I E
xpre
ss
Test 1:
2 Zone AES1 eMEGAsim target6 (of 8) processor cores usedMinimum achievable Ts = 32 μs
Ts = 50 μs
Test 2:
4 Zone AES2 eMEGAsim targetsDolphin PCI-SCI comm. link12 (of 16) processor cores usedMinimum achievable Ts = 33 μs
20
Components of a real-time simulator
Real-time simulator components
Applications
Real-Time Platform
Processing
Communication
Inputs/Outputs
Solvers
Models
Sequencer
RT-LAB
RT-LAB solutions for power systems
OPAL-RT provides various tools for the simulation of power systems, motor drives and power electronic converter are provided
ARTEMiS: Real-time enabler for SimPowerSystems RTeDRIVE: Power Electronics and motor drives toolbox
21
MATLABSimulink
Simulink
SimPowerSystems
ARTEMiSRTeDRIVE
Sequencer
22
Opal-RT Toolboxes for electric system simulation
ARTEMiS Plug-in to SimPowerSystems Makes pre-computation of circuit modes to
allow real-time performance Increase stability and precision
23
Opal-RT Toolboxes for electric system simulation
RTeDRIVE A specialized library of IGBT/GTO/MOSFET
inverters/choppers (2- and 3-level) Use interpolated switching functions Compatible with SPS or Simulink only
24
RT-LAB features
HILBox PC1HILBox PC1
PC
I E
XP
RE
SS
PC
I E
XP
RE
SS
CPUCPU
SimulinkModel
SimulinkModel
Single-, Dual-, or
Quad-Core
Single-, Dual-, or
Quad-Core
RT-LAB eMEGAsim Simulator Hardware Architecture
2525
CPUCPU
Sh.Mem.Sh.Mem.
SimulinkModel
SimulinkModel
Host/Target Architecture Windows QNX & RT-Linux RTOS SIMULINK/RTW based Multi-core support
PC
I
P
CI
HILBox PC1HILBox PC1
PC
I E
XP
RE
SS
PC
I E
XP
RE
SS
CPUCPU
SimulinkModel
SimulinkModel
Single-, Dual-, or
Quad-Core
Single-, Dual-, or
Quad-Core
RT-LAB eMEGAsim Simulator Hardware Architecture
2626
CPUCPU
Sh.Mem.Sh.Mem.
SimulinkModel
SimulinkModel
Host/Target Architecture Windows QNX & RT-Linux RTOS SIMULINK/RTW based
Multi-core Processors Shared-Memory Multi-CPU board
PC
I
P
CI
RS-232, CAN, TCP/IP
IEC61850, LoadRunner
PCI PCIe Extension User has the possibility
to add PCI cards to the simulator with standard Protocol like TCP/IP, UDP/IP, RS-232
Or to develop and study advanced protocols (ex: IEC-6185)
HILBox PC1HILBox PC1
PC
I E
XP
RE
SS
PC
I E
XP
RE
SS
CPUCPU
FastComFastCom
CPUCPU
Sh.Mem.Sh.Mem.
PCI Express
RT-LAB eMEGAsim Simulator Hardware Architecture
2727
Host/Target Architecture Windows QNX & RT-Linux RTOS SIMULINK/RTW based
Multi-core processors Shared-Memory Multi-CPU board
16 AO16 AO 16 AI16 AI
Carrier w (op511x)Carrier w (op511x)
16 DO16 DO 16 DI16 DI
Carrier (op5210)Carrier (op5210)
FP
GA
(o
p51
42)
FP
GA
(o
p51
42)
16 DO16 DO 16 DI16 DI
Carrier (op5210)Carrier (op5210)
16 AO16 AO 16 AI16 AI
Carrier w (op511x)Carrier w (op511x)
Digital IO requirements
For power Electronics Must be capable of
sampling Thyristor/ IGBT/GTO/MOSFET gate with great accuracy
The latency must also be very low so it does not to slow down the simulation (PCI Express)
Sampling of fast PWM gate signals
28
For this purpose, PWM pulse are captured on the FPGA card by 100MHz counters
Normalized ratio (Time stamp) is send to the inverter models on the CPU
The model on the CPU use the Time Stamps to compute interpolated voltages
Simulator clock (50 s)
To wind generator model& Time Stamped Bridge
logic=1stamp=0.625
count at transition time= 3125max count =5000
FPGA counter card 10 ns clock (100 MHz)
External controller
Fiber optic cable
opto-isolator
Real-time simulator
Firing pulse unit
I/O
Pentium
Control algorithms
IGBT
Effect of switch gate sampling and interpolation
RTeDRIVE inverter model use the time stamps to produce very accurate results
Example: a simple DC chopper (PWM=10kHz, Ts=10µs) Bad sampling (like if we use regular SPS) causes
important non-linearity in the input-output characteristic But very linear caracteristic with RTeDrive TSB inverters
Tcarrier/Ts=10
SimPowerSystemsEMTP, PLECS
TSB
Effect of switch gate sampling and interpolation
Precise enough to take into account deadtime effect smaller that the sample Time
Below is the effect of dead time increment of 2 µs (with a sample time of 10µs!)
HILBox PC1HILBox PC1
PC
I E
XP
RE
SS
PC
I E
XP
RE
SS
CPUCPU
FastComFastCom
CPUCPU
Sh.Mem.Sh.Mem.
PCI Express
Hardware Architecture (FPGA models)
3131
Host/Target Architecture Windows QNX & RT-Linux RTOS SIMULINK/RTW based
Multi-core processors Shared-Memory, Multi-CPU board
16 AO16 AO 16 AI16 AI
Carrier w (op511x)Carrier w (op511x)
16 DO16 DO 16 DI16 DI
Carrier (op5210)Carrier (op5210)
FP
GA
(o
p51
42)
FP
GA
(o
p51
42)
16 DO16 DO 16 DI16 DI
Carrier (op5210)Carrier (op5210)
16 AO16 AO 16 AI16 AI
Carrier w (op511x)Carrier w (op511x)
Xilinx System Generator Blockset
Model
Xilinx System Generator Blockset
Model
Xilinx SG model
Models with 10 ns sample rate can be coded on this card!
FPGA user programmabilityfor advanced model design
The FPGA card can be programmed by the user using Xilinx System Generator
No VHDL language skill required. It is a Simulink blockset
HILBox PC2HILBox PC2DolphinDolphin
PC
IP
CI
Expandability FireWire INFINIBAND switch DOLPHIN SCI /PCIe
(2 to 5 us latency)
HILBox PC1HILBox PC1
PC
I E
XP
RE
SS
PC
I E
XP
RE
SS
CPUCPU
Simulator Hardware Architecture (Expandability)
3232
16 AO16 AO 16 AI16 AI
Carrier w (op511x)Carrier w (op511x)
16 DO16 DO 16 DI16 DI
Carrier (op5210)Carrier (op5210)
DolphinDolphin
CPUCPU
Sh.Mem.Sh.Mem.
Host/Target Architecture Windows QNX & RT-Linux RTOS SIMULINK/RTW based
Multi-core processors Shared-Memory Multi-CPU board
FP
GA
(o
p51
42)
FP
GA
(o
p51
42)
16 DO16 DO 16 DI16 DI
Carrier (op5210)Carrier (op5210)
16 AO16 AO 16 AI16 AI
Carrier w (op511x)Carrier w (op511x)PCI Express
33
About the necessity for testing
Real-Time Solvers for Power Systems
34
Simulation solvers for power systems
Key characteristics of power systems Contains a wide range of frequency modes
Requires ‘stiff’ fixed-step solvers. Stiff solver remains stable even with mode above the simulation Nyquist limit.
Contains a lot of PWM-driven power electronics The simulator must avoid sampling effect when
computing IGBT pulse ‘events’ internally or when reading PWM pulses from its I/Os
Stiff solvers methods for power system simulation
Simulation methods electric systems: State-Space (SimPowerSystems) Switching-function (Power Electronics &
converters) FPGA-based methods
Stiff solvers methods for power system simulation
State-Space approach of SimPowerSystems We can also find the exact state-space solution
With k, matrix set index for switch permutations This can be discretized with the trapezoidal method like in
SimPowerSystems for Simulink Trapezoidal method: order 2.
It can also be discretized by higher order methods Higher order methods (order 5) implemented in
ARTEMiS, a solver package of eMEGAsim.
uDxCyuBxAx kkkk
Stiff solvers methods for power system simulation
State-Space approach Continuous time state-space expression
Solution for time step T:
How to compute the ‘matrix exponential’ eAT ? Trapezoidal method (order 2)
ARTEMiS art5 method (order 5)
uBxAx kk
t
Tt
tAn
ATn dBuexex )()(
1
2/
2/
ATI
ATIeAT
36012
203
53
2201
52
)()(
)(
ATATATI
ATATIeAT
...!
...!5!4!3!2!1
5432
n
ATATATATATATIe
nAT
TALYOREXPENSION
Effect of higher order discretization
Artemis ART5 solver more precise than Trapezoidal solver at 100 us
Simple case of RLC circuit energization
Numerical stability issues
Discretized systems is not guarantied to be stable It depends on how Laplace poles are ‘mapped’ in the z
domain. Ex: Forward Euler has poor stability A-stability (Stiff stability) (ex: trapeze method) guaranty
discrete stability (for linear systems)
y’=ly
Re{l}
Im{l}
-2/T
Forward EulerStability Region
RLC network Euler T=0.01µs
Laplace pole (s) mappingRLC network Trapeze T=100µs
TrapezeStability Region
Numerical stability issues with trapezoidal integration
Even if it is stable, the trapezoidal rule (tustin) is prone to numerical oscillations The z-domain mapping is stable
but oscillatory for high frequency Laplace poles
Numerical stability issues with trapezoidal integration
A-stable methods can be highly oscillatory How are mapped high frequency poles? It depends on the ‘stability function’ again
y’=ly
Re{l}
Im{l}
Laplace map
y(n+1)=zy(n)
Re{z}
Im{z}Z- domain map
X -1X
12/
2/lim
ATI
ATIAT
Trapeze (A-stable)
X
0)()(
)(lim
36012
203
53
2201
52
ATATATI
ATATIAT
ARTEMiS art5 (L-stable)
z mapping near -1 means oscillations
***
* V_load near zero for positive I_load by lower anti-parallel diode action if both GIBT are turned off
Gup Glow
RTeDRIVE approach: interpolated switching function
Switching function approach A special solver method for power electronic system
using high-frequency PWM. It is a ‘simple’ controlled voltage source! Interpolation methods are used to obtain high accuracy
in the Opal-RT RTeDRIVE package High impedance mode supported now.
~100V
~0
0
1gate
V_load
V_load
Effect of switch gate sampling and interpolation
RTeDRIVE inverter model use the time stamps to produce very accurate results
Example: a simple DC chopper (PWM=10kHz, Ts=10µs) Bad sampling (like if we use regular SPS) causes
important non-linearity in the input-output characteristic But very linear caracteristic with RTeDrive TSB inverters
Tcarrier/Ts=10
SimPowerSystemsEMTP, PLECS
TSB
Effect of switch gate sampling and interpolation
Precise enough to take into account deadtime effect smaller that the sample Time
Below is the effect of dead time increment of 2 µs (with a sample time of 10µs!)
Interpolated switching functions: example case 1
Mitsubishi Electric CoJapan, 2004ARTEMiS used for rectifier sideRTeDRIVE used for inverter
45
© Opal-RT © Opal-RT MITSUBISHI
0 0.003 0.006 0.009 0.012-20
-10
0
10
20
Motor Current [A]
Time [sec]
0 0.003 0.006 0.009 0.012-20
-10
0
10
20
Motor Current [A]
Time [sec]
0 0.003 0.006 0.009 0.012-20
-10
0
10
20
Motor Current [A]
Time [sec]
0 0.003 0.006 0.009 0.012-20
-10
0
10
20
Motor Current [A]
Time [sec]
0 0.003 0.006 0.009 0.012-20
-10
0
10
20
Motor Current [A]
Time [sec]
0 0.003 0.006 0.009 0.012-20
-10
0
10
20
Motor Current [A]
Time [sec]
HIL Simulation Physical System
PWM9kHz
PWM4.5kHz
PWM2.25kHz
permanentmagnet motor
Currents
External controller (sampling rate =55 s)
3-phasesource
reactor
dioderectifier
x6 x6
PWMinverter
N
S
Tload
IGBTpulses
Quadratureencoder signals
CPU 1: (Ts= 80 us) CPU 2: (Ts= 10 us)
(Fpwm =9 kHz)
RT-LAB Electric Drive SimulatorRT-LAB Electric Drive Simulator
Example 2 – Industrial Motor Drives
46
Multi Level Inverter DriveCONVERTEAM-ALSTOM (France)
line voltage wave form
1200V
M3~~
PEC CONTROLLER
PRECHARGE
HV NETWORK
~LV NETWORK
12-PULSERECTIFIER
3-LEVEL NEUTRAL CLAMPEDBRIDGE
dV/dtFILTER
INDUCTION MOTOR12MW-6600V
This Controller is connectedExternally to the Simulator
Example 3 – Industrial Motor Drives
47
Multi Level Inverter DriveCONVERTEAM-ALSTOM (France)
M3~~
PEC CONTROLLER
PRECHARGE
HV NETWORK
~LV NETWORK
12-PULSERECTIFIER
3-LEVEL NEUTRAL CLAMPEDBRIDGE
dV/dtFILTER
INDUCTION MOTOR12MW-6600V
Motor Acceleration Emergency Pulse shutdown
Pulse shutdown modeled with the help of Converteam
Required the design of an hybrid switching-function with high-impedance capability
Results of Hardware-In-the-Loop Tests
Importance of Interpolation (again)
Interpolation is important because the Real-Time Simulator is a sampled system
The above figure shows the typical effect of neglecting ‘interpolation’ during the simulation.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-2
-1
0
1
2x 10
5 Electromagnetic Torque
Tor
que
in N
.m
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-1500
-1000
-500
0
500
1000
1500Inverter Currents
Cur
rent
in A
Time in s
EM Torque
Currents
C. Bordas, C. Dufour, O. Rudloff, “A 3-Level Neutral-Clamped Inverter Model with Natural Switching Mode Support for the Real-Time Simulation of Variable Speed Drives”, Proceedings of the 8th International Symposium on Advanced Electromechanical Motion Systems (ELECTROMOTION-2009), Lille, France, July 1-3, 2009
Converteam case Ts=40us Deadtime=20us Fpwm=400Hz Interpolation disabled
@ 1 second
DEAD-TIME
WITH INTERPOLATION WITHOUT INTERPOLATION
3-level STATCOM with 72 IGBT (Mitsubishi Electric)
Interpolated switching functions: how high can you get?
20 µs, 3 CPU with the controller 1000 time faster than conventional
simulation software Actual diode/IGBT count: 10*6*3=180
Reference model In EMTP/RV (3us)
vs Simulink/SPS/ RT-LAB (50 us)
IPST 2009, Kyoto - Japan 49
RT-LAB XSG permits to use Xilinx System Generator models inside RT-LAB frame work
Enables complex model to run on the FPGA of RT-LAB
Examples: PMSM motor IGBT inverter, PWM modulator Power electronics
Subsystem #2 Simulink
Rate=50s
Subsystem #1 Simulink
Rate=10s Subsystem #3Xilinx System Generator
Rate= 10 ns
DIO
AIO
RTW XSGRT-LAB
Simulink Model
Code Generation
Distributed Real-Time Model
DIO
AIO
Single/dual multi-core CPU PC FPGA card with embedded IO
Host PC
SW
lin
k
Eth
ern
et
lin
k
Simulation On Chip (FPGA)
No need to know VHDL language But you need to know fixed-point arithmetic
Real-life example: Rotary Variable Differential Transformer (RVDT) designed for Embraer in one week using XSG!
Simulation On Chip (FPGA)
A typical XSG model in RT-LAB
Simulation On Chip (FPGA) Example: PMSM Drive
PMSM drive built on FPGA using only XSG PMSM, BLDC and FEA-Based PMSM Include: test modulator, quad enc., resolver
*C. Dufour et al. “Real-Time Simulation of Finite-Element Analysis Permanent Magnet Synchronous Machine Drives on a FPGA card”, Proceedings of 2007 European Conference on Power Electronics and Applications (EPE-07) , Aalborg, Danemark , Sept 2007
Permanent
magnet motor N
S
rotor & Vsource Phase shift of Vsource
internal 3-phase voltage source modulator
F mod :10-200 kHz
shift
Modulation index
upper IGBT pulses
lower IGBT pulses
Internal PWM test source
IGBT gate source selection
Analog Outputs i abc
External Digital Inputs
Dead time
IGBT inverter
abcabcabc
abc IdtRIdt
dVL )(][ 1
53
Test sequencer
Test sequencer
54
Test sequencer: a key part of real-time simulator
Test sequencer requirement Capability to launch test
automatically Capability to record and
analyze data Capability to manage
models
Use the full power of MATLAB and Python languages
Test sequencer: a key part of real-time simulator
Usage case: Monte-Carlo testing How to dimension correctly some power system
component considering switching surges?
55
Test Automation with Python script
56
Test algorithm coded in Python
Fault application and breaker reclosing are randomized
57
Test sequencer: a key part of real-time simulator
By making automated randomized tests (Monte-Carlo), we can obtain probabilistic characteristics of overvoltages.
1.8 2 2.2 2.4 2.6 2.8 30
20
40
60
80
100
120
0
0.2
0.4
0.6
0.8
1
Num
ber
of o
ccur
ence
s
Cum
ulat
ive
prob
abili
ty (
CD
F)
Voltage peak during fault (pu)
A-G
ND
FA
ULT
0 0.05 0.1 0.15
-2
-1
0
1
2
Vol
tage
(pu
)
time (s)
Phase APhase BPhase C
A-GND2000 runs
58
PHIL
Power Hardware-In-the-Loop
62
Example of PHIL testing (L2EP, Lilles)
Distributed Energy Storage Systems Application Used for frequency control on islanded network Real power electronic device connected to a
simulated grid!
H. Fakham, A. Doniec, F. Colas, X. Guillaud, “A Multi-agents System for a Distributed Power Management of Micro Turbine Generators Connected to a Grid”, Conference on Control Methodologies and Technologies for Energy Efficiency (CMTEE 2010) Vilamoura, Portugal http://www.cmtee.org/
63
Frequency regulation tests
The higher the energy storage capacity, the lower the frequency deviation during fault
Impact of ultracapacitor-based DESS on the frequency response of an isolated power system after a major generation loss
Key References
University of Alberta Power Systems Laboratorybased on RT-LAB L.-F. Pak, O. Faruque, X. Nie, V. Dinavahi, “A Versatile Cluster-Based Real-
Time Digital Simulator for Power Engineering Research”, IEEE Transactions on Power Systems, Vol. 21, No. 2, pp. 455-465, May 2006.
Power Hardware-In-The-Loop Testing of Grid Systems D. Ocnasu, S. Bacha, I. Munteanu, C. Dufour, D. Roye, “Real-Time Power-
Hardware-In-the-Loop Facility for Shunt and Serial Power Electronics Benchmarking”, Proceedings of the 13th European Conference on Power Electronics and Applications (EPE-2009), Barcelona, Spain, Sept. 8-10, 2009
Advanced Motor Drive Simulation M. Harakawa, C. Dufour, S. Nishimura, T.Nagano, “Real-Time Simulation of a
PMSM Drive in Faulty Modes with Validation Against an Actual Drive System”, Proceedings of the 13th European Conference on Power Electronics and Applications (EPE-2009), Barcelona, Spain, Sept. 8-10, 2009
RT-LAB application booklet with over 30 applications explained from motor drives and power electronics to large power systems.
Opal-RT Technologies 652006.09.28
Opal-RT Partial Customer List
66
Opal-RT Clients involved in Electric Motor Drive and Power Grid Studies
Ford
68
Appendix 1: How to use RT-LAB for power system applications?
How to use RT-LAB for power system applications?
69
1- Design your model in Simulink and SimPowerSystems
2- Identify natural delay in your model (ex: transmission lines)
3- Make top-level groups in your Simulink model, these will be assigned to different CPUs of the simulator
4- Add I/O block in the model if necessary
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1- Design your model in Simulink and SimPowerSystems We choose here a SPS demo named: power_PSS.mdl
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2- Identify power line to make parallel distributed simulation
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3- Choose a task separation and make Subsystems
CPU #1 CPU #2
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4- Some optimizations: put controllers in a separate CPU because it can run at slower rate
Also put monitoring in a separate subsystem
Controls Monitoring
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You can put your own ‘C’ code in any of the cores You just have to use a S-function ‘wrapper’
int main() { printf("hello, world");printf(“I want to do real-time simulations");return 0; }
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5- Adding I/Os Let’s add an analog output from the RT-LAB library
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Let’s output the Alternator Excitation voltage
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The alternator excitation voltage can now be read on the front panel of the simulator
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Most commercial I/O cards can be supported
Opal can supply the source code of communication driver examples to enable users to implement their own protocols through Ethernet for Internet