Short Course, International SOI Conference, 2005
Sandip Tiwari [email protected]
Potential, Characteristics and Issues of 3D SOI:3D-SOI Opportunities
Sandip Tiwari; Cornell University 2Short Course, International SOI Conference, 2005
Silicon Landscape
Architecture (Cores, threads, workloads, …)
Suitable devices, interconnects, caches, memory, I/O, …
while addressing
power, die area, thermal, design methodology, system scalability and programming models
Digital: higher Ops/WattAnalog/RF:
higher f, S/N & lower power, footprint
Smaller structures &
Lower voltages
Information Manipulation: Devices
Information Flow: Interconnects
Information Processing: Energy and Time
Sandip Tiwari; Cornell University 3Short Course, International SOI Conference, 2005
Chip I/O Density
Source: E. Beyne (IMEC)Now imagine continuing decrease in device size and increasing system integration
Sandip Tiwari; Cornell University 4Short Course, International SOI Conference, 2005
Off-Chip Interconnects: MCM
Source: E. Beyne (IMEC)
1 cm long lineZ0 = 50 Ω, Cu
Going off-chip, at the least, has latency and power penalties
Sandip Tiwari; Cornell University 5Short Course, International SOI Conference, 2005
3D: Packaged & Integrated
Evolutionary and relatively well-characterized technology Addresses interconnect gap near-termEnables above IC processing and high quality passivesUses known good diesAllows high density interposers
A major change and still in development If effective, makes possible large changes densities, integration, cost, power, performance and footprint
Level 4
Level 3
Level 2
Level 1
Si
SiO2
SiO2
SiO2
Packaged IntegratedS. K. Kim (2005)A. Matsuzawa (2005)
Sandip Tiwari; Cornell University 6Short Course, International SOI Conference, 2005
Integration
Source: D. Radack (DARPA)
System integration and scaling as device size approaches limits
No.
Tra
nsis
tors
/chi
p //
Per
form
ance
/Fun
ctio
nalit
y
Continuing System Scaling
DeviceScaling
Limit!3D!
Time
No.
Tra
nsis
tors
per
cm
3in
sys
tem
12-15 years
2D (CMOS C’s)
3D Packaging
3D Integrated
End-of-Moore’s Law!
Sandip Tiwari; Cornell University 7Short Course, International SOI Conference, 2005
3D
High Frequency Mixed-Signal Applications
Mixed Materials Integration
Mixed Process Technologies
Higher circuit interconnectivity
Shorter vertical interconnections between layers
Low digital system power
SOI 3D (SOI)
Advanced Imaging
Heterogeneous Function
Integration
High BW µP
Compact Mobile Applications
P = C V2 f
Ultrafast Signal Processing: FFTs, Radars, Pixel-based
Computation
System on
Chip
Sandip Tiwari; Cornell University 8Short Course, International SOI Conference, 2005
Overview
Benefits:Shorter global wires and elimination of repeatersIncreased logic span of controlLower power, cross-talk, I/Os, and packagingImproved functionalityHigher packing density and smaller footprintHeterogeneous integration
Issues:Design and architecture optimizationTechnologyHeat dissipation and power, bulk-SOI interactions, …Cost (Yield, Testing, Pin Count)
Device layers
SubstrateWires
connecting between
device layers
Interconnectlayers (IL)
3-D ICs: Integration of planar device layers with short, vertical interconnections
Sandip Tiwari; Cornell University 9Short Course, International SOI Conference, 2005
Outline
2D: SOIKey digital and Mixed-Signal oriented attributes with implications for 3DInterconnects and the issues of power
3D: A more complex SOI TechnologiesDesign Implications of multi-layered structures
Signals, Heats, Interconnectivity, … Application implications
Microprocessors: Logic-Memory interactions and heat-aware placementMemoriesMixed-signalProgrammable New technologies
Synopsis
Sandip Tiwari; Cornell University 10Short Course, International SOI Conference, 2005
3D as a Complex SOI
Low leakage, specially at higher temperatures
Lower body factor
Lower bit line and other capacitances
Lower voltage and lower power
Dielectric isolation between device layers
Radiation hard, lower soft-error rates
Reduced cross-talk through high resistivity substrate – low loss high Q inductors
Silicon Substrate
Sandip Tiwari; Cornell University 11Short Course, International SOI Conference, 2005
SOI MOSFET
⎥⎦⎤
⎢⎣⎡ −−= 2
2
1)( DDThGoxD nVVVV
L
WCI µ
n: body factor that emphasizes the strength of gate to channel coupling
221 )( ThGL
WoxnDSat VVCI −= µ
)10(lnq
kTnS =
L
W
nI
C
I
g
D
ox
D
m µ2=
Current:
Saturation Current:
Subthreshold Swing:
Transconductance:
Sandip Tiwari; Cornell University 12Short Course, International SOI Conference, 2005
Body Factor: Strength of Gate to Channel Coupling
Body factor for different designs – partially depleted, body contacted, dual gates, … varies, but all lead to reduction
Reduced junction capacitances with SOI
Judicious SOI design leveraging these two important consequences of insulator underneath permit reduced power for similar speeds (reduced voltage, ..)
Cox
CSi
Cox
CSi
CBox
Bulk: n ~ 1.5 Fully Depleted: n ~ 1.1
Gate
Source Drain
Sandip Tiwari; Cornell University 13Short Course, International SOI Conference, 2005
SOI: Characteristics
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
-0.5 0 0.5 1 1.5 2
Dra
in c
urre
nt (
A/µ
m)
Gate-to-source voltage (V)
NMOSFETDrawn length: 0.25 µm
Vds
= 0.1 V
Dashed line: fully-depleted Tsi
= 35 nm
Solid line: partially-depleted Tsi
= 100 nm
Vds
= 1.8 V
80 mV/decade
68 mV/decade
0
50
100
150
200
250
300
0 0.5 1 1.5 2
Dra
in c
urre
nt (
µA
/µm
)
Drain-to-source voltage (V)
Dashed line: fully-depletedSolid line: partially-depleted
Vgs
- Vt ( V)
1
0.4
0.1
0.7
Kink effect
Source: O. Faynot
Bias, time and frequency dependence from floating body + bipolaractivation via generated charge
Weaker in fully depleted
Design techniques exist for time dependence
Heating effects from poor thermal conductivity (κ)
Sandip Tiwari; Cornell University 14Short Course, International SOI Conference, 2005
SOI: Characteristics
Floating body and bipolar activation via generated chargeBias-dependent effectsTime-dependent effectsFrequency-dependent effectsFully depleted structures have smaller effects
Frequency dependence is a bigger problem
Heating effects from poor thermal conductivity (κ)Source: O. Faynot and Y C Tseng
Sandip Tiwari; Cornell University 15Short Course, International SOI Conference, 2005
Interconnects: 2D
Technology scaling occurs with increasing average interconnect length and routing density and increased interconnect aspect ratio
Interconnects grow linearly with cells in ordered arrays (memories, e.g.)
Interconnects grow as the square of the elements in random logic
Local (intra-block) wires scale with block size, but global (inter-block) wires do not. Global wiring and increasing buffers become an increasingly problem
Wire Length (unit of die-size)
Pro
babi
lity
0.5
Local
Global
Fringing & Coupling
Capacitances
Sandip Tiwari; Cornell University 16Short Course, International SOI Conference, 2005
Throughput & Power Dissipation in Buffers
Use of repeaters means more power, and absence means increased delays with global delays more dominantIn 65 nm high speed designs, the # of buffers is ~850K
More area, power and congestion
Source: Deodhar et al.180 nm technology
Driver Receiver
Sandip Tiwari; Cornell University 17Short Course, International SOI Conference, 2005
Clock Span
Increasing fclk and speedReduced logic span
Higher electromagnetic coupling: capacitive coupling inductive bounce
Source: Saraswat
Short Course, International SOI Conference, 2005
Technologies
Device properties
Interconnectivity attributes
Technology impact on integration
Sandip Tiwari; Cornell University 19Short Course, International SOI Conference, 2005
A Broad Classification: Sequential & Parallel
Sequentially Processed
Additional Si layers formed and processed sequentially
Vertical interconnectivity higher
Lower layers are exposed to additional thermal cycle
Sequential processing constraints on metallurgies allowed
Parallel Processed
Separately processed layers stacked in parallel
Vertical interconnectivity lower
Lower thermal processing constraints
Stress/Strain and run-out issues from bonding techniques employed
Si
Si
Sandip Tiwari; Cornell University 20Short Course, International SOI Conference, 2005
3D Fabrication Approaches
Still experimental
Variety of characteristics
Bonding transfer of single crystal Si
A complex SOI
High mobility
Subsequent device processing exposes lower layers to additional thermal cycling
Digital and analog circuits demonstrated
Silicon LayerTransfer
Bonding of processed wafers
All devices are exposed to similar temperatures
Deeper via interconnects needed
Alignment tolerances limit vertical interconnects to global wiring
Circuits demonstrated
Processed Wafer Bonding
Seeded recrystallization
Larger grain sizes
Contamination and interfaces still an issue
Subsequent device processing exposes lower layers to additional thermal cycling
Devices demonstrated
Epitaxial growth of single crystal Si
High temperature growth affects lower layer devices
Loss of area to seed regions
Simple integration demonstrated
Crystallization of deposited films
(makes TFTs)
Larger VT variations
Usually low mobilities
SRAMsdemonstrated
Solid Phase Crystallization
Silicon EpitaxyEnergetic Beam Recrystallization
Sandip Tiwari; Cornell University 21Short Course, International SOI Conference, 2005
Energetic Beam Recrystallization
Poor mobilitiesImpurity incorporation during annealingStatistical variations from grain boundariesTemperature consequences on lower layers from upper layer processing
Examples: T. Kunio et al. (1989)T. Kamins IEDM 420(1982)
Sandip Tiwari; Cornell University 22Short Course, International SOI Conference, 2005
Silicon Epitaxy
Single crystal epitaxy at ~800 CHigh temperature effects
Devices
Metallurgy
Area loss to seed growth
Limits to number of levels
Source: IBM (1970’s), Purdue, Samsung, …
Recess Creation
Seed Window
Epitaxy
Polishing
seeddevices
devices
Sandip Tiwari; Cornell University 23Short Course, International SOI Conference, 2005
Solid Phase Recrystallization
Seeded recrystallization (Ni, Ge, silicides, …) at <650 C for long time followed by higher temperature annealing
High via density
Large grains
Contamination from seeds
Grain boundary effects
Larger variations at small size from grain boundaries
Effect on lower level devices from upper layer processing
Source: S. Jagar (1999)
Si Substrate
Buried Oxide
Ni
Sandip Tiwari; Cornell University 24Short Course, International SOI Conference, 2005
Silicon Layer Transfer
Smart-cut like process to transfer single-crystal silicon film
High mobilities, SOI-like structure
High via densities
But
Effect on lower level devices from upper layer processing
Short to medium distance buried interconnects (polysilicon and tungsten)
Si donor wafer
H+ / H2+
H implanted region
Si host wafer
LTO
Si host wafer
Si donor waferH implanted region
oxide
Si host wafer
Layered SOI
Si donor wafer
Source: L. Xue et al. (2000)
Sandip Tiwari; Cornell University 25Short Course, International SOI Conference, 2005
Processed Wafer Transfer: Example 1
Transfer of processed wafers through thermal bond using precision grinding
Large density of buried in-plane interconnects
Compatible with heterogeneous materials
But
Alignment
Bond strength
Stress/Strain
Large aspect ratio vertical via’s
Thermal conductivity
Source: K. W. Guarini (2002)
Sandip Tiwari; Cornell University 26Short Course, International SOI Conference, 2005
Processed Wafer Transfer: Example 2
Transfer of processed wafers through polymer bond
Low temperature
Large density of buried in-plane interconnects
Compatible with heterogeneous materials
But
Alignment
Stress/Strain
Large aspect ratio vertical via’s
Thermal conductivity
HostWafer
Donor Layer
BondInterface
Glass Wafer
BOX
Polymer AdhesivePolymer Adhesive
Host Si Bulk
BOX
BCB Dielectric
Donor Si Bulk
Glass Wafer
BOX
Polymer AdhesivePolymer Adhesive
Glass Wafer
BOX
Host Si Bulk
BOX
BCB Dielectric
Source: S. K. Kim (2004)
Sandip Tiwari; Cornell University 27Short Course, International SOI Conference, 2005
Eutectic Contact Bonding
Wafer bonding with polymer film and interconnectivity through eutectic (Au/In) bond
Precision grinding and selective stop
Alignment
Bond strength
Stress/Strain
Large aspect ratio vertical via’s
Thermal conductivity
Source: Y. Hayashi et al., IEDM (1991)
Sandip Tiwari; Cornell University 28Short Course, International SOI Conference, 2005
Copper Contact Bonding
Interconnectivity through Cu-Cu bondPrecision grinding and selective stopAlignmentBond strengthStress/StrainThermal conductivityThermal stress at bond interfaceMetal bonding compatibility with wafer-to-wafer bonding
Source: R. Reif, ISQED (2002)
Sandip Tiwari; Cornell University 29Short Course, International SOI Conference, 2005
Multi-Layers; Front-Front & Back
Front-FrontWafer Bond
Wafer-1
Wafer-2 Handle Silicon
Concentric 3D Via
IC2
Wafer-1 Handle Silicon
IC2
Wafer-1 Handle Silicon
IC3
IC2
Wafer-1 Handle Silicon
IC3
Multi-layer structures with front-front and back-to frontFront-front bonding provides shortest distances and high connectivityPrecision grinding and selective stopAlignmentBond strengthStress/StrainThermal conductivityLarge vias from top-most layers (~3 µm)
Source: C. Keast (Lincoln Labs)
Short Course, International SOI Conference, 2005
Challenges in 3D
Heat removal
Blockage: Interconnects, Via Density and Parasitics (RLC)
Design Tools: Floor Planning, Heat, Timing, Automated Layout, …
Yield/Cost/Performance Synergy
Technology <-> Design
Short Course, International SOI Conference, 2005
Thermal Dissipation
Increased temperatures lead to reduced mobility & reduced current in steady-state
Frequency-dependent output conductance and transconductance
Sandip Tiwari; Cornell University 32Short Course, International SOI Conference, 2005
Thermal Constraints
~1.35
~0.1-1
SiO2
Polymers
Inter-layer Dielectric
~174
~398
~237
Tungsten
Copper
Aluminum
Interconnects
~58Single-crystal SiSOI Device Layer*
~148Single-crystal SiSubstrate
Thermal Conductivity (W/m*K)
Material
* doping and thickness dependent
Sandip Tiwari; Cornell University 33Short Course, International SOI Conference, 2005
Thermal Effects: Clock Driver as an Example
Source: C. C. Liu et al. (2002)
Power dissipation on chip is extremely non-uniform.Example:
3-D chip on 2nd layer,Assume 4% via density between layers at 1 µm separation.
3-D heat dissipation needs to be analyzed at local level.
100 W95 W
5 W
∆T=0.14 oC ∆T=14 oC
Sandip Tiwari; Cornell University 34Short Course, International SOI Conference, 2005
Interconnects as heat pipes
Source: C. C. Liu et al. (2002)
1 10 10060
80
100
120
140
160
180
200
Temp. of clock driver on SOI (400 nm BOX)
Thermal conductivity of SiO2
Temp. of clock driver on SOI (200 nm BOX)
Ma
x. te
mpe
ratu
re (
o C)
Length of horizontal wire (µm)
Vertical wiring density 1% 4% 7% 10%
Depends heavily on the density of vertical wires and length of horizontal wiresKey point is: Freedom to control the interconnect density underneath a large power sourceInterconnects not only propagates electric signals but also function as heat pipes
Sandip Tiwari; Cornell University 35Short Course, International SOI Conference, 2005
Thermal Effects: Example of Clock Drivers
103 104 105
50
60
70
80
90
100
110
120
130 3D: 5µm SOI: 200nm BOX 3D: 1µm under driver
and 5µm elsewhere Bulk CMOS
Te
mp
era
ture
(oC
)
Power density (W/cm2)
10050
60
70
80
90
100
110
120
130
140
150
160
50 500T
em
pe
ratu
re (
oC
)Driver pitch (µm)
Source: C. C. LiuDimensionality of heat flow Interconnect content of the interlayer dielectric
Sandip Tiwari; Cornell University 36Short Course, International SOI Conference, 2005
103
104
105
106
50
100
150
Local power/unit area of clock driver (W/cm2)
Ma
xim
um
te
mp
era
ture
(oC
)
bulk CMOS SOI CMOS 3d-CMOS: 3 µ m 3d-CMOS: 5 µ m 3d-CMOS: 10 µm
Temperature vs. Clock Power
SOI Bulk
3DI
Source: C.C. Liu
Thermal effects are strong in 3DDemands synergistic design
Sandip Tiwari; Cornell University 37Short Course, International SOI Conference, 2005
3DI Thermal Issues
0.5 1 1.5 2 2.5 3 3.550
100
150
200
250
Buried interconnect layer thickness (µm)
Ma
xim
um
te
mp
era
ture
(oC
)
15 µm 10 µm 7.5 µm5 µm 3 µm 1 µm
Source: C.C. Liu
Sandip Tiwari; Cornell University 38Short Course, International SOI Conference, 2005
Thermal Transients
0 50 100 150 200 250 30050607080
Clock driver on upper layer
0 50 100 150 200 250 30050
52
54Lower (bulk) device layer directly below driver
0 50 100 150 200 250 30050
50.5
Temperature (
o C)
5.9 µm directly below driver
0 50 100 150 200 250 30050
50.5
Time (ns)
5.8 µm in-plane from driver (upper device layer)
Devices in one plane affected by devices from another plane Source: C.C. Liu
Short Course, International SOI Conference, 2005
Circuits
Issues similar to that of SOI
Thermal effects because of higher volume density of increasing concern
Bulk-SOI co-existence provides new opportunities
Sandip Tiwari; Cornell University 40Short Course, International SOI Conference, 2005
Leakage in Dynamic Circuits in 3D/SOI
Parasitic bipolar (floating body) and leakage effect on noise margin
When width of m7 pull-up is 0.4 um, the circuit fails under the PBE test!
Because of PBE, an SOI-based dynamic OR circuit has a reduced noise margin, compared to bulk CMOS
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
A B out m2#body m3#body
dynor_soi_tran2_fail (m7 width=0.4u)
Vol
tage
(V
)
Time (ns)
C.C. Liu TCAS II (2005)
In
SOI
Leakage currentdue to PBE
Width=0.4 µm
A
B
out
Sandip Tiwari; Cornell University 41Short Course, International SOI Conference, 2005
3D: Dynamic Circuits
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
A B out
dynor_msb1_tran2 (m7 width=0.4u)
Vo
ltag
e (V
)Time (ns)
3D design:Pre-charge, Evaluation: SOILogic: Bulk
Switching the logic transistors to bulk allows PBE to be avoided and circuit failure is eliminated!
C.C. Liu TCAS II (2005)
In
Logic transistors: BULK
Width=0.4 µm
A
B
out
Sandip Tiwari; Cornell University 42Short Course, International SOI Conference, 2005
Pass Transistor Logic: LEAP
0 20 40 60 80 10093.2
93.4
93.6
93.8
94.0
94.2
94.4
94.6
1.68
1.70
1.72
1.74
1.76
1.78
1.80
1.82
1.84
1.86
1.88
LEAP-Delay and body voltage for falling input
De
lay
(ps)
Time (ns)
Delay
Bo
dy v
olta
ge
(V) Body voltage
3D is much faster than bulk. Hysteresis for falling input transition varies only about 1 ps over 100 cycles (steady state after 20 cycles)
Delay constant after body voltage reaches steady state, which varies with device design (effects of generation vs. recombination currents)
Pass transistors: SOI
C.C. Liu TCAS II (2005)
In1
In2 outy
Sandip Tiwari; Cornell University 43Short Course, International SOI Conference, 2005
Analog Mixed SOI-Bulk Design
Kink-free analog operation requires remapping of biasing
Source: C. C. Liu
SN S
VBiasM0
M1 SN S
VBiasM0
M1
3-D design
=SOI, =bulk
Cascode Current-Cell:
0 1 2 3 4 5
0
20
40
60
I OU
T (
µA)
VOUT
(V)
VDD
=3.3 V, VGS|M1
=2.5 V
SOI: V
Bias=0.75 V
VBias
=1.0 V
VBias
=1.25 V
3-D: V
Bias=0.75 V
Short Course, International SOI Conference, 2005
Computation
High DensityLow Latency
Wide BandwidthFloor Planning and Synergistic Design accounting for
Thermal, Electromagnetic and Cost Issues
Sandip Tiwari; Cornell University 45Short Course, International SOI Conference, 2005
Mapping Designs with Heat and Cost Constraints
65 nm technology node with wire length, delay, energy, manufacturing cost, and temperature as design constraints
Minimize delay (D) and/or cost (C) while T<Tmax
Vertical pitch between device layers 10 µm, vertical via’s 2 µm x 2 µm, 8 levels of metal (23 masks), 2 bonding process steps, 300 mm wafer, clock period of 8 FO4’s (FO4=21.6 ps) with 20 ps clock overhead
[ ]BW
wafer
design
N
B
N
W
MNMNA
A
YYC ⋅−+⋅⋅⋅= − )( 1
11
∑ ∑= =
−− ⎥⎦
⎤⎢⎣
⎡⎟⎠
⎞⎜⎝
⎛=∆N
i
N
ikkiiD PRT
1)1(3
Cost based on masks, bonding steps, yield at wafer level
Temperature based on an effective thermal resistance model
)( maxTTCDobjective −++= γβα Global minimum by simulated annealing
Source: C. C. Liu et al., ISCAS-2005
Sandip Tiwari; Cornell University 46Short Course, International SOI Conference, 2005
Design Trade-offs: Multi-Window Display
P=8.0 WRSUBS=3.1 C/W TMAX=75.0 C Frequency=1/delay (delay: Logic, wire, setup delays) FO4=21.6 ps, SKEW=20 ps. YW=YB=95%
Low Power Application
Source: C. C. Liu et al., ISCAS-2005
2-D
3-D
RISC
MEM1
In
NR
SEBlend
HS1
VS1
HS2
VS2
Jug1
Jug2
MEM
2
MEM
3MEM4
layer 1
layer 2
layer 3RISC
MEM
1
In
NR
SE
Blend
HS2
VS2
HS1
VS1
Jug2
Jug1
MEM
2
MEM3
MEM
4Critical path
Critical path
2.95
3.40
3.30
2.49
8.14
Footprint [mm2]
3.69
4.03
3.94
4.17
3.48
Clock frequency [GHz]
3
3
3
4
1
# of circuit layers
79.01.890.8350.575No temp. constraint
3-D
2-D 50.01.001.001.00
1.49
1.72
1.66
Normalized cost
64.5
63.2
60.1
Maximum temp. [oC]
Normalized delay
Normalized wire length
0.9450.841Cost-oriented
0.864
0.885
0.694
0.713
Delay-oriented
Balanced
2.95
3.40
3.30
2.49
8.14
Footprint [mm2]
3.69
4.03
3.94
4.17
3.48
Clock frequency [GHz]
3
3
3
4
1
# of circuit layers
79.01.890.8350.575No temp. constraint
3-D
2-D 50.01.001.001.00
1.49
1.72
1.66
Normalized cost
64.5
63.2
60.1
Maximum temp. [oC]
Normalized delay
Normalized wire length
0.9450.841Cost-oriented
0.864
0.885
0.694
0.713
Delay-oriented
Balanced
Sandip Tiwari; Cornell University 47Short Course, International SOI Conference, 2005
Graphics Processor
High Performance Application
P=189 WRSUBS=0.26 C/W TMAX=100 C Frequency=1/delay(delay: Logic, wire, setup
delays) YW=YB=95%
Source: C. C. Liu et al., ISCAS-2005
Critical path
Critical path
2-D 3-D
63.6
77.6
65.1
47.8
183
Footprint [mm2]
1.39
1.66
1.45
1.67
0.989
Clock frequency [GHz]
3
3
3
4
1
# of circuit layers
1131.610.5930.410No temp. constraint
3-D
2-D 75.01.001.001.00
1.43
1.74
1.46
Normalized cost
95.9
89.8
94.2
Maximum temp. [oC]
Normalized delay
Normalized wire length
0.7100.599Cost-oriented
0.596
0.682
0.521
0.634
Delay-oriented
Balanced
63.6
77.6
65.1
47.8
183
Footprint [mm2]
1.39
1.66
1.45
1.67
0.989
Clock frequency [GHz]
3
3
3
4
1
# of circuit layers
1131.610.5930.410No temp. constraint
3-D
2-D 75.01.001.001.00
1.43
1.74
1.46
Normalized cost
95.9
89.8
94.2
Maximum temp. [oC]
Normalized delay
Normalized wire length
0.7100.599Cost-oriented
0.596
0.682
0.521
0.634
Delay-oriented
Balanced
Sandip Tiwari; Cornell University 48Short Course, International SOI Conference, 2005
3-D Microprocessors
Goal of improving logic-memory interactions and to compensate logic and memory performance divergence
Current designs exceedingly complex (-> power^ ) focused on
Superscalar (> 1 inst/cycle), out-of-order execution, instruction-level parallelism, hiding memory latency, …
3-D in µP: High density, low latency, large bandwidth
1−10 µm separationVertical connections throughout the design area
Sandip Tiwari; Cornell University 49Short Course, International SOI Conference, 2005
Latency and Bandwidth
2-D: Connections on the peripheryLong global connectionsCPU to off-chip main memory with latency and misses
3-D: Connections across the area
Connections short + vertical
Suitable for high-bandwidth and vector operations
No pin cost, large block access of data
CPU
Memory
CPU
Memory
The following example uses a baseline 2-D processor core representative of current technology3 GHz CPU, 750 MHz memory, 64 KB L1I, 64 KB L1D, 1 MB L2
Latency: Important for random access (servers, e.g.), single coreBandwidth: Multiple cores, multi-threads, graphics
Sandip Tiwari; Cornell University 50Short Course, International SOI Conference, 2005
Stacking L2 Cache and Main Memory
Floor-planning minimizes critical pathsEven if hypothetically L2 cache latency reduced from 11 to 9 cycles, the resulting speedup is minimal (Avg. < 1% improvement)Stacking main memory on top of the CPU (instead of stacking the existing L2 cache) provides a much larger performance boost
Source: C. C. Liu et al., D&T (2005)
SPEC2000 Integer programs Floating-point programs
bzi
p2
craf
ty
eon
gap
gcc
gzi
p
mcf
pa
rse
r
perlb
mk
two
lf
vort
ex
vpr
Int A
vg
0
20
40
60
80
100 111
%
Spe
edup
ove
r ba
selin
e 2-
D p
roce
ssor
(%
)
L2 latency=9 cycles DRAM-based DRAM macro (improved) DRAM-based DRAM macro, bus=8 B Logic-based DRAM macro (improved) DRAM-based DRAM macro, bus=64 B Perfect L2
126
%17
8%
144
0%
am
mp
appl
u
apsi art
equa
ke
mes
a
mgr
id
sixt
rack
swim
wu
pwis
e
Fp
Avg
0
50
100
150
200
385
%
392
%
Spe
edup
ove
r ba
selin
e 2
-D p
roce
sso
r (%
)
L2 latency=9 cycles DRAM-based DRAM macro (improved) DRAM-based DRAM macro, bus=8 B Logic-based DRAM macro (improved) DRAM-based DRAM macro, bus=64 B Perfect L2
427
%
Sandip Tiwari; Cornell University 51Short Course, International SOI Conference, 2005
Expanding L2 Cache
Performance peaks at 8 MB for integer programs with standard DRAM Example of trade-off between fitting the working data (4-16 MB for integer programs) into the cache (better performance) and increased access latency for larger caches (worse performance) Larger working data of floating-point programs continue to improve with cache size despite cache hit latency with large cache size
Source: C. C. Liu et al., D&T (2005)
SPEC2000 Integer programs Floating-point programs
2 MB 4 MB 8 MB 16 MB 32 MB 64 MB0
20
40
60
On-chip DRAMw/ 1 MB L2
Ave
rage
spe
edup
ove
rba
selin
e 2-
D p
roce
ssor
(%
)
L2 cache size
Standard DRAM Standard DRAM +
stream prefetch On-chip DRAM +
stream prefetch
Perfect L2
2 MB 4 MB 8 MB 16 MB 32 MB 64 MB0
20
40
60
80
100
120
140
On-chip DRAMw/ 1 MB L2
Ave
rage
spe
edup
ove
rba
selin
e 2-
D p
roce
ssor
(%
)
L2 cache size
Standard DRAM Standard DRAM + stream prefetch On-chip DRAM + stream prefetch
Perfect L2
Sandip Tiwari; Cornell University 52Short Course, International SOI Conference, 2005
L2/L3 Cache Sizing with Stream Prefetching
Performance within 8-10% of perfect L2Large speedups achievable with small L2/L3 cache combinations because of the significant reduction in main memory latencySmall L2/L3 caches implementable within the CPU die, followed by 3D implementations
Source: C. C. Liu et al., D&T (2005)
SPEC2000 Integer programs Floating-point programs
2 MB 4 MB 8 MB 16 MB 32 MB 64 MB
20
40
60
On-chip DRAM w/ 1 MB L2 (no L3)
On-chip DRAM +stream prefetch
Standard DRAM +stream prefetch
Ave
rage
spe
edup
ove
rba
selin
e 2-
D p
roce
ssor
(%
)
L3 cache size
L2 = 1 MB L2 = 2 MB L2 = 4 MB L2 = 8 MB
Standard DRAM
Perfect L2
2 MB 4 MB 8 MB 16 MB 32 MB 64 MB
20
40
60
80
100
120
140
On-chip DRAM w/ 1 MB L2 (no L3)
On-chip DRAM +stream prefetch
Standard DRAM +stream prefetch
Ave
rage
spe
edup
ove
rba
selin
e 2-
D p
roce
ssor
(%
)
L3 cache size
L2 = 1 MB L2 = 2 MB L2 = 4 MB L2 = 8 MB
Standard DRAM
Perfect L2
Sandip Tiwari; Cornell University 53Short Course, International SOI Conference, 2005
Floor-Planned 3D RC Mitigation: iA32 Architecture
2x density at constant footprint
Inter-block folding
Also, some intra-block interconnect reduction
Shorter clock network global wires, local wires, driver strength
Source: Nelson et al. (Intel)
Face-to-face with denser connectivity & standard packaging
Deep pipeline
25% of pipe stages eliminated
FP load latency reduced by 35%
…
15% reduction in power from elimination of 50% of repeaters, reduction in global wires, and 50% in clock wire lengths
Shallow pipeline (~1/3 branch penalty)
~30% global wire reduction
…
Short Course, International SOI Conference, 2005
Memories
Small Area and High Density
Integration of Large Arrays in Small Footprint
Sandip Tiwari; Cornell University 55Short Course, International SOI Conference, 2005
An Early Example: Poly-Si Load
Area efficiency
Poly-Si transistor loads first appeared in late 90’s
Leakage minimized through film and transistor design
Source: H. Kuriyama (1998)
Sandip Tiwari; Cornell University 56Short Course, International SOI Conference, 2005
A 2 Layer SRAM Example
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
50
60
70
80
90
100
110
120
130
140
150
Bitc
ell s
ize
rel
ativ
e to
m
inim
um-s
ized
bitc
ell o
n bu
lk C
MO
S (
%)
Width of driver transistor, Wdriver
(µm)
Bulk SOI 3-D Configuration 1 3-D Configuration 2
0.6 0.8 1.0 1.2 1.41
2
3
4 Bulk SOI 3-D Configuration 1 3-D Configuration 2
Del
ay fo
r ∆V
=10
0mV
on
bitli
ne (
ns)
Power supply voltage (V)
Lower Plane Upper Plane
C. C. Liu et al. (2002)
Lower bit line capacitances (smaller overlap capacitances with reduced area and insulators)
Time-domain effects make sense-amplifiers more difficult as in SOI (need body contacts or mixed-SOI-bulk design)
Sandip Tiwari; Cornell University 57Short Course, International SOI Conference, 2005
38.2
147
0.512
3-D
68.0
101
0.860
SOIBulk
1.67Delay (ns)
171Static noise margin (mV)
5.21Standby power (nW)
54%85%100%Circuit footprint
Load: M1 & M2, Access: M3 & M4, Driver: M5 & M6
M6
M2
M5
M1
M3 M4
M6
M2
M5
M1
M3 M4
=SOI,
=bulk
WL WL
BL BL BL BL
3-D
SRAMs
Sandip Tiwari; Cornell University 58Short Course, International SOI Conference, 2005
Samsung: 3 Layer SRAM
25 f2
All process temperatures <650 C after bulk device fabrication
Plasma oxidation for gate oxide
Single Co silicidation of all transistors
Ultra-compact
Source: S. M. Jung et al. (Samsung)
Short Course, International SOI Conference, 2005
Programmable Arrays
3D potentially provides additional layers of interconnects
Arrays allow increase in vertical interconnectivity for some of the technologies
Asynchronous methods allow reduction of power
Sandip Tiwari; Cornell University 60Short Course, International SOI Conference, 2005
Asynchronous FPGA
Asynchronous mapping of Xilinx Virtex
Island-style FPGA architecture
Pipelined logic and routingNo long wires in the architecture
Dataflow programming model
Statically configurable array
Benchmarks show strong improvement and asynchronous allows low voltage in addition to shorter wires
Performance RatioAFPGA / Xilinx
2.5x to 6x
Peng (2005), Fang (2005)
Sandip Tiwari; Cornell University 61Short Course, International SOI Conference, 2005
3D Asynchronous FPGA
Reduce long paths architecturallyMultiple AFPGA tiersExtend interconnect to 3D
Reduce long paths by increasing densityStack configuration bits and logicVertical AFPGA logic blockStack AFPGA logic block and switch-box
Potential benefits of 3D15% architectural improvement in mismatchMost benefit attained from 1->2 device layersArchitecture tolerates mismatch of up to 6with < 10% performance loss
0
2
4
6
8
10
12
14
16
18
2 3 4 5 6 7 8 9 10Length of Pipeline Mismatch
Nu
mb
er o
f In
stan
ces 2D: 1 Device Layer
3D: 2 Device Layer
3D: 5 Device Layer
Short Course, International SOI Conference, 2005
Cross-Talk & Mixed-Signal Applications
Reduced Capacitive CouplingShielding and Lower Inductive Bounce
Separation of Digital/Analog Device DesignSmaller Foot-Print
Heterogeneous Integration
Sandip Tiwari; Cornell University 63Short Course, International SOI Conference, 2005
Mixed Signal ICs
Digital noise impacts analog functionLdi/dt appears on analog ground
Reduced performance of RF stages, PLLs, etc.
3D allows separation of analog and digital Isolation through ground planes
Careful design of P/G system and 10s of dB of additional isolation through return paths
+-
Substrate
didt
didt
Analog Digital Core Off-chip drivers
LL
Sandip Tiwari; Cornell University 64Short Course, International SOI Conference, 2005
Heterogeneous, SOI and RF
3D provides a platform for integrating heterogeneously (SiGe, MEMS, optics, IIIV, …)
SOIDevices can be ultra-high frequency (320 GHz distributed amplifiers have been achieved)But designs need to take into account time and frequency effectsarising from floating body and parsitic bipolar, and heating
Source: J-A Plouchart (2005)
180 nm SOI
Sandip Tiwari; Cornell University 65Short Course, International SOI Conference, 2005
RF in 3D Structures(Ground-plane vs No Ground-plane)
• Excitation source into signal line = 6.25 GHz, 2.5V
Source: S. K. Kim (2002)
Freq (GHz)
(Vtransm)
(Vincid)
Sandip Tiwari; Cornell University 66Short Course, International SOI Conference, 2005
Crosstalk Reduction using Ground Planes
3D provides a very suitable platform for cross-talk reduction for mixed analog/digital designs
Gate
Source
Drain
Ground Plane
Excitation Line
3D nMOS
4.0 8.0 12 16 20-60
-55
-50
-45
-40
-35
Frequency (GHz)
S21
Cro
ss T
alk
(dB
)
Floating Gnd PlaneGrounded Gnd Plane
8dB of Crosstalk Isolation
Source: S. K. Kim (2005)
Sandip Tiwari; Cornell University 67Short Course, International SOI Conference, 2005
Crosstalk Reduction using Ground Planes
3D provides a very suitable platform for cross-talk reduction for mixed analog/digital designs
S. K. Kim (2005)
WithoutGround Plane
With Ground Plane
S
G D
Gndplane
Disturb In
Coupled Signal
Short Course, International SOI Conference, 2005
New Directions
Leveraging Heterogeneity (RF, Optical, THz, …)Short Distance Connectivity
Small FootprintRapid High Frequency Signal Down-Conversion for Digital
ProcessingReal time Massive Signal Processing and Broad Frequency
Range Applications
Sandip Tiwari; Cornell University 69Short Course, International SOI Conference, 2005
3D: New Directions
Matrix Corp.Write once archival memory
Array of Antifuse-Diode cellsBlowing the antifuse connects the diodes8 layers in 250 nm technology
High density through simple processing and small footprint
Source: www.matrixsemi.com
Sandip Tiwari; Cornell University 70Short Course, International SOI Conference, 2005
3D Imagers
Back illuminated pixel sensor array with fully parallel A/D conversion in a 2 layer processHigh fill factorFootprint and short distances criticalHeterogeneous
useful for focal plane arrays
Source: J. Burns, ISSCC (2001); Lincoln Labs
Sandip Tiwari; Cornell University 71Short Course, International SOI Conference, 2005
BioMimetic Artifical Retina
Source: M. Koyanagi
3 stacked and interconnected layers that mimics eye
Photoreceptor array (Photodiodes)Bipolar cell layer (Cell layer)Ganglion cell layer (Pulse Modulator layer)
Footprint and short distances critical
Sandip Tiwari; Cornell University 72Short Course, International SOI Conference, 2005
Network-on-Chip for SoC
Network on chip connected to system on chip (Dally DAC01)Data hopping between moduleskn number of nodes where k is radix and n dimension of the network
2-D to 3-D leads to decrease in periphery nodes from kn/2 to kn/3
Large performance gain from increase in interconnectivity
2 3 4 5 6 7 8 9 10 11 12100
200
300
400
500
600
Lat
enc
y (N
um
ber
of
unit
2-D
wir
e de
lays
)
Dimension (n)
2-D 3-D symmetric 3-D asymmetric
2 3 4 5 6 7 8 9 10 11 12
100
200
300
Lat
enc
y (N
um
ber
of
uni
t 2-D
wir
e d
elay
s)
Dimension (n)
2-D 3-D symmetric 3-D asymmetric
Source: C. C. Liu (unpublished)
2-D
3-D
2-D
3-D
Message length=2048 bitsN=4096 nodes
Message length=64 bitsN=4096 nodes
Sandip Tiwari; Cornell University 73Short Course, International SOI Conference, 2005
Challenges in 3D
Heat removalBlockageYieldVia parasitics (RLC)Via densityDesign toolsTechnology compatible with needs of design
But, lot of potentialIrvine Sensors: http://www.irvine-sensors.comMatrix: http://www.matrixsemi.comR3logic: http://www.r3logic.comTezzaron: http://www.tezzaron.comVertical Circuits: http://www.verticalcircuits.com/Xan3D: http://www.xanoptix.com/Ziptronix: http://www.ziptronix.comZyCube: http://www.zy-cube.com/Large semiconductor manufacturers (IBM, Intel, Samsung, Sony, Hitachi, Sanyo, NEC, … )Universities galore
Sandip Tiwari; Cornell University 74Short Course, International SOI Conference, 2005
Conclusions
3D can be an effective way for achieving higher functionality and performance for a number of applications as device scaling becomes increasingly prohibitive
3D can be an effective solution for a select set of applicationstoday where footprint is at premium and performance benefits outweigh increased costs
However, considerable development of 3D is necessary before it can acquire a broader scope
Power/density
Technology with high yield and low cost
Design tools
Acknowledgements:Colleagues and Students: L. Xue, C. C. Liu, S. K. Kim, H. Silva, A. Kumar, U. Avci, A. Gokirmak, J. Zhang, J.-H. Chen, I. Ganusov, A. K. Datta, R. Manohar, M. Burtscher, K. Guarini, W. Haensch, A. Young, K. Bernstein, …Funding: DARPA (D. Radack), NSF, SRC
Sandip Tiwari; Cornell University 75Short Course, International SOI Conference, 2005
References
General (Devices and Interconnects)Y-C Tseng, W-L Huang, P.J. Welch, J.M. Ford, J.C.S. Woo, “Empirical correlation between AC kink and low-frequency noise overshoot in SOI MOSFETs,” Electron Device Letters, 157(1998)V. Agarwal, M. S. Hrishikash, S. W. Keckler, and D. Burger, “Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures,”Computuer Architecture News, 248(2000).J. W. Joyner, R. Venkatesan, P. Zarkesh-Ha, J. A. Davis, J. D. Meindl, “Impact of three-dimensional architectures on interconnects in gigascaleintegration,” IEEE Trans. VLSI Systems, 922(2001)A. Rahman, S. Das, A. Chandrakasan, and R. Reif, “Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays,” IEEE Trans. on VLSI Systems, vol. 11, 44(2003)V. V. Deodhar, J.A. Davis, J.A., “Optimization of Throughput Performance for Low Power VLSI Interconnects,” Trans. VLSI, 308(2005)K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration,” Proc. IEEE, vol. 89, 602(2001)E. Beyne, “Wafer Level Packaging Interconnect Technology,” IEDM Short Course (2003)P. Gopalakrishnan, A. Odabasioglu, L. Pileggi, and S. Raje, “An Analysis of the Wire-Load Model Uncertainty Problem,” IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, 23(2002)K. Saraswat,”3-Dimensional ICs: Motivation, Performance Analysis and Technology,” IEDM Short Course (2003)O. Faynot and T. Poiroux, “SOI MOSFET Modeling for CAD,” SOI Conference Short Course (2002)J-P Colinge, “Silicon on Insulator MOSFETs,” IEDM Short Course (2003)R. Ho, K. W. Mai and M. A. Horowitz, “The Future of Wires,” Proceedings of the IEEE, vol. 89, 490(2001)W. J. Dally and B. Towles, “Route packets, not wires: on-chip interconnection networks,” in Proceedings of Design Automation Conference, 684(2001)D. A. Patterson, “Hardware Technology Trends and Database Opportunities”, SIGMOD Conference 1998 Keynote speech.
TechnologyS. Kawamura, N. Sasaki, T. Iwai, M. Nakano, and M. Takagi, “Three-Dimensional CMOS ICs Fabricated by Using Beam Recrystallization,” IEEE Electron Device Lett., 366(1983)Y. Akasaka and T. Nishimura, “Concept and Basic Technologies for 3-D IC Structure,” IEDM Tech. Dig., 488(1986)T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto, “Three-Dimensional ICs Having Four Stacked Active Device Layers,” IEDM Tech. Dig., 837(1989)K. Yamazaki, Y. Itoh, A. Wada, K. Morimoto, and Y. Tomita, “4-layer 3-D IC Technologies for Parallel Signal Processing,” IEDM Tech. Dig., 599(1990)Y. Hayashi, K. Oyama, K, S. Takahashi, S. Wada, K. Kajiyana, R. Koh, T. Kunio, “A New Three Dimensional IC Fabrication Technology Stacking Thin Film Dual-CMOS layers ,” IEDM Tech. Dig. 657(1991)V. W. C. Chan, P. C. H. Chan, and M. Chan, “Three Dimensional CMOS Integrated Circuits on Large Grain Polysilicon Films,” IEDM Tech. Dig., 161(2000)G.W. Neudeck, T.-C. Su, and J. P. Denton, “Novel Silicon Epitaxy for Advanced MOSFET Devices,” IEDM Tech. Dig., 169(2000)V. W. C. Chan, P. C. H. Chan, and M. Chan, “Three-Dimensional CMOS SOI Integrated Circuit Using High-Temperature Metal-Induced Lateral Crystallization,” IEEE Trans. on Elec Dev, 1394(2001)V. W. C. Chan, P. C. H. Chan, and M. Chan, “Multiple layers of CMOS Integrated Circuits using Recrystallized Silicon Film,” IEEE Elec Dev Lett , 77 (2001)
Sandip Tiwari; Cornell University 76Short Course, International SOI Conference, 2005
References
Technology (continued)L. Xue, C. C. Liu, and S. Tiwari, “Multi- Layers with Buried Structures (MLBS): An Approach to Three Dimensional Integration,” SOI Conf. Tech. Digest, 117(2001) R. J. Gutmann, J.-Q. Lu, Y. Kwon, J. F. McDonald, and T. S. Cale, “Three Dimensional (3D) ICs: A Technology Platform for Integrated Systems and Opportunities for New Polymeric Adhesives,” Proc IEEE Int’l Conf on Polymers and Adhesives in Microelectronics and Photonics, Germany, 173(2001) K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. T. Park, H. Kurino, M. Koyanagi, “Three-Dimensional Shared Memory Fabricated using Wafer Stacking Technology,” IEDM Tech Dig, 165(2000)R. Reif , A. Fan, K.-N. Chen, and S. Das, “Fabrication Technologies for Three Dimensional Integrated Circuits,” Proc IEEE Int’l Symposium on Quality Electronic Design, 33(2002)H. S. Kim, L. Xue, A. Kumar, and S. Tiwari, “Fabrication and Electrical properties of Buried Tungsten Structure for Direct Three Dimensional Integration,” in Int. Conf. on Solid State Devices and Materials, Sept. (2002)K. W. Guarini, A. W. Topol, M. Ieong, R. Yu, L. Shi, M. R. Newport, D. J. Frank, D. V. Singh, G. M. Cohen, S. V. Nitta, D. C. Boyd, P. A. O’Neil, S. L. Tempest, H. B. Pogge, S. Purushothaman, and W. E. Haensch, “Electrical Integrity of State-of-the-Art 0.13 µm SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication,” IEDM Tech Dig., 943(2002)S. K. Kim, L. Xue, and S. Tiwari, “Low Temperature Silicon Circuit Layering for 3-Dimensional Integration,” SOI Conf. Tech Digest, 136(2004)
Circuits/CADC. C. Liu, J. H. Chen, R. Manohar and S. Tiwari, “Mapping System-on-Chip Designs from 2-D to 3-D ICs,” Tech. Digest of ISCAS, (2005)C. C. Tong, C.-L. Wu, “Routing in a Three-Dimensional Chip,” IEEE Trans. Computers, 106(1995)C.C. Liu and S. Tiwari, “Performance Advantages of 3-D Digital Integrated Circuits in a Mixed SOI and Bulk CMOS Design Space,” IEEE Trans. On Circuits and Systems (2005)
MemoryY. Uemoto, E. Fujii, A. Nakamura, and K. Senda “A High Performance Stacked CMOS SRAM Cell by Solid Phase Growth Technique,” VLSI Tech. Symp. Tech. Digest, 21(1990) H. Kuriyama, Y. Ishigaki, Y. Fujii, S. Maegawa, S. Maeda, S. Miyamoto, K. Tsutsumi, H. Miyoshi and A. Yasuoka, “A C-Switch Cell for Low-Voltage and High-Density SRAMs,” IEEE Trans. El. Dev., 2483(1998)S-M Jung et al., “Highly Cost-effective and High Performance 65 nm S3 SRAM Technology with 25F2, 0.16 mm2 and Doubly Stacked SSTFT Cell Trnasostors for Ultra High Density and High Speed Applications,” VLSI Tech. Symp. Digest, 220(2005)C. C. Liu and S. Tiwari, “Application of 3D CMOS Technology to SRAMs,” SOI Conf. Tech. Digest, 68(2002)
ProcessorsS. Alam, D. Troxel, and C. Thompson, “A Comprehensive Layout Methodology and Layout-Specific Circuit Analysis for Three-Dimensional Integrated Circuits,” Proc IEEE Int’l Symposium on Quality Electronic Design, 246(2002)M. B. Kleiner, S. A. Kuhn, P. Ramm, and W. Weber, “Performance Improvement of the Memory Hierarchy of RISC-Systems by Application of 3-D Technology,” IEEE Trans. Comp. Packaging, Manuf. Technol., 709(1996)J. C. Koch, D. A. Leder, R. J. Sung, T. L. Brandon, D. G. Elliott, B. F. Cockburn and L. McIlrath, “Design of a 3D Fully Depleted SOI Computational RAM,” IEEE Tran. on VLSI, 358(2005)
Sandip Tiwari; Cornell University 77Short Course, International SOI Conference, 2005
References
Processors (continued)D. W. Nelson, C. Webb, D. McCauley, K. Raol, J. Rupley, J. DeVale and B. Black, “A 3D Interconnect Methodology Applied ot iA32-class Architectures for Performance Improvement through RC Mitigation,” Proc. VLSI Multilevel Interconnection Conference (2004).B. Black, D. W. Nelson, C. Webb, N. Samra, “3D Processing Technology and Its Impact on iA32 Processors,” IEEE International Conference on Computer Design: VLSI in Computers and Processors, 316(2004)K. Puttaswamy and G. H. Loh, “Implementing Caches in a 3D Technology for High Performance Processors,” To appear in ICCD 2005.C. C. Liu, I. Ganusov, M. Burtscher, and S. Tiwari, “Bridging the Processor-Memory Performance Gap with 3-D IC Technology,” IEEE Design and Test of Computers Magazine, (2005)
Programmable ArraysS. Peng, D. Fang, J. Teifel, R. Manohar, “Automated Synthesis for Asynchronous FPGAs,” Proc. FPGA (2005)D. Fang, J. Teifel, R. Manohar, “A High Performance Asynchronous FPGA: Test Results,” Proc. FCCM (2005)
Mixed SignalK. Nishikawa, K. Kamogawa, T. Nakagawa, M. Tanaka, "Low-voltage C-band Si BJT Single-Chip Receiver MMIC Based on Si 3D MMIC Technology", IEEE Microwave and Guided-wave Letters, 248(2004)S. K. Kim, C. C. Liu, L. Xue and S. Tiwari, “Crosstalk Attenuation with Ground Plane Structures in Three-Dimensionally Integrated Mixed Signal Systems,” Tech. Dig. of IEEE International Microwave Symposium (2005)J-O Plouchart Plouchart, J.-O.; Zamdmer, N.; J. Kim, R. Trzcinski, S. Narasimha, M. Khare, L.F. Wagner, S.L. Sweeney, S. Chaloux, “A 243-GHz FT and 208 GHz Fmax, 90-nm SOI CMOS SoC Technology With Low-Power mmWave Digital and RF Circuit Capability,” IEEE Trans. Electron Devices, 1370(2005)
ThermalC. C. Liu, J. Zhang, A. K. Datta, and S. Tiwari, “Heating Effects of Clock Drivers on Bulk, SOI, and 3-D CMOS,” IEEE Electron Device Letters, 716(2002)B. Goplen and S. Sapatnekar, “Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach,” Int. Conf. on Computer Aided Design Digest, 86(2003)
Potential
M. Crowley, A. Al-Shamma, D. Bosch, M. Farmwald, L. Fasoli, A. Ilkbahar, M. Johnson, B. Kleveland, T. Lee, T.-Y. Liu, Q. Nguyen, R. Scheuerlein, K. So, and T. Thorp, “512Mb PROM with 8 layers of Antifuse/Diode cells,” ISSCC Tech Dig, 284(2003)
J. Burns, L. McIlrath, C. Keast, C. Lewis, A. Loomis, K. Warner, P. Wyatt, “3-D ICs: A Novel Chip Design for Improving Deep-SubmicrometerInterconnect Performance and Systems-on-Chip Integration,” ISSCC Tech. Dig., 268(2001)
J. Deguchi, T. Watanabe, T. Nakamura, Y. Nakagawa, T. Fukushima, S. Jeoung-Chill, H. Kurino, T, Abe, M Tamai and M. Koyanagi, “Three-Dimensionally Stacked Analog Retinal Prosthesis Chip,” Japan J. of Appl. Phys., 1685(2004)
Top Related