Performances of recent outstanding 28FDSOI circuits and systems taped out through the CMP services
Andreia Cathelin, fellow
STMicroelectronics, Crolles
CMP, Annual Users Meeting
Paris, January 25th, 2018
Fully depleted Silicon-on-Insulator (FD-SOI)FBB
Total dielectric isolation
No channel doping
No pocket implant
FD-SOI is unmatched for cost-sensitive markets requiring digital and Mixed Signal SoC integration and performance
Power and energy efficiency
Analog performancefor mixed signal and RF design
Robustnessfor mission critical applications
High k / metal gate
Elevated SD
Thin silicon film
Thin buried oxide
<100> substrate
0 1.1V
2
Addressing Power Sensitive Markets
FinFetHigh-end Servers
Tablet PC
NetworkingInfrastructure
ConsumerMultimedia
Automotive
Smartphone
Internet of Things,Wearables
Ultimate Digital / Analog & Mixed-Signal / RF
Integration
Ultimate Digital Density
Laptops
3
ST 28nm FD-SOI Transistor Flavors
-3 -2 -1 0 1 2 3-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
FBB
RBB
RBB
FBBVth
(V)
VB (V)
NLVT NRVT PLVT PRVT
Bulk type CMOS
Regular VT (RVT) CMOS in FD-SOI
Low VT (LVT) CMOS in FD-SOI; flipped-well
BOX BOX
VBBPVBBN
GSD
GSD
P‐WellN‐Well
P‐Sub
PMOSNMOS
BOX BOX
VBBNVBBP
GSD
GSD
P‐WellN‐Well
P‐Sub
NMOSPMOS
‐3 3‐0.3
‐3 3VBBN+0.3
‐3 3‐0.3
‐3 3VBBP+0.3
Nominal VBB
GND
GND
VDD
GND
LVT NMOS
LVT PMOS
RVT PMOS
RVT NMOS
Biasing mode
FBB
FBB
RBB
RBB
4
for Simpler Analog IntegrationST 28nm FD- SOI makes analog/RF/HS designer’s life easier
Efficient Short Devices
Improved Analog Performance
Improved Noise
Speed increase in all analog blocksHigher gain for a given current density
Higher bandwidth
Lower power
Smaller designs
Improved design margins wrt PVT variations
Novel flexible design architectures
Lower gate and parasitic capacitanceLower noise variability
Better matching for short devices and efficient design with L>Lmin
Very large VT tuning range Analog parameters wide range tuning via a new independent “tuning knob” (back-gate)
High performance frequency behavior
fT/ fmax >300GHz for LVTNMOS and high performance passives enabling RF/mmW/HS integration with technology margin
5
Advantages in Analog Design
• Efficient use of short devices : • High analogue gain @ Low L• Low Vt mismatch (Avt ~ 2mV.µm)
• Performance example:• A 1µm/100nm device has a
DC gain of 80 & a Vt of only 6mV
• Higher Gm for a given current density
• Lower gate capacitance
Higher achievable bandwidth or lower power for a given
bandwidth
• For NLVT MOS 1µm/120nm @ 1µA drain current, get 1.5dB lower 1/f noise in FDSOI
Efficient Short Devices Improved Analog Perf. Improved NoiseDC gain-lin (Gm/Gds)
Gate lenght (m)
28FDSOI
28LP bulk
Gate lenght (m)
Avt (mV.µm)Curves for W=1µm
28FDSOI
28LP bulk
28FDSOI
28LP bulk
Gate lenght (m)
Gm/Id (1/V)
Gate lenght (m)
Cgg (fF/µm) 28LP bulk28FDSOI
Input ref. voltage noise @1HzFor NLVT W=1µm/L=1µm
Input ref. voltage noise @1HzFor NLVT W=1µm/L=120nm
28FDSOI
28LP bulk
28FDSOI28LP bulk
Idrain/W (µA/µm)
Idrain/W (µA/µm)
6
Advantages in Analog Design-II
• Flip-well devices:• Large Forward Body Bias (FBB) range• Negligible control current
• Use back-gate as « VT tuning knob »: • Unprecendented ~250mV of tuning
range for FD-SOI vs.• ~ 10’s mV in any bulk
Very large VT tuning range by FBB
FD-SOI(flip-well flavor/LVT devices)
P-Sub
FBB
VBBP
VBBN
0V
+3V
-3VP-sub
BulkFD-SOI
Forward body bias [V]
V T[m
V]
ST 28nm LVT NMOS (typical)
7
Advantages in RF/mmW Design
• For RF operationfrequency :
• Work with L = 100nm• MAG = 12dB @10GHz• NFmin ~ 0.5dB @ 10GHz• Work @ current density: 125
µA/µm
• Few passive devices examples:
• Inductor L=0.5nH Q=18 @10GHz, 8ML
• Varactor C=50fF Q=20 @20GHz
• Tline: 0.8dB/mm @60GHz Zc=50 Ohm, 8ML
Active devices high frequency performance Performant passive devices
• For mmW operationfrequency (intrinsic models):
• Work @ Lmin• MAG = 12dB @60GHz• NFmin ~ 1.3dB @ 60GHz• Work @ current density: 200
µA/µm 33% less power thanin 28LP bulk
• For ST 28nm FD-SOI LVTNFET: fT/ fmax >300GHz
8
Advantages in Mixed Signal Design
• Tighter process corners and less random mismatch than competing processes
• Benefits:• Simpler design process, shorter
design cycle• Improved yield or improved
performance at given yield
Variability Switch performance Lower capacitance
• Improved gate control allows smaller VTH
• Backgate bias allows for VTH reduction by tuning
• Results is an unprecedented quality of analog switches
• Compounding benefits: smaller R -> smaller switch -> compact layout -> lower parastics -> even smaller switch
• Key for high performance data converters and other Switched-Cap. Circuits
• Lower junction capacitance makes a substantial difference in high-speed circuits
• Drastic reduction of self-loading in gain stages
• Drastic reduction of switch self-loading
• Two-fold benefit:• Leads to incremental
improvements• Allows the designer to use circuit
architectures that would be infeasible/inefficient in bulk technologies
Vth (mV)
Gate lenght (m)
28FDSOI
28lp bulk
SlowTypFast
SlowTypFast
9
– The FBB Advantage for Digital Design
Forward Body Biasing: An extremely powerful and flexible concept in FD-SOI
0 1.1V
Performance boost
Reduce power consumption at a given performance requirement
Seamless inclusion in the EDA flow
Process compensation reducing the margins to be taken at design
Comparatively easy to implementIf you’ve ever done DVFS you’ll
have no difficulty with Body Biasing
A very reasonable effort for extremely worthwhile benefits
10
Body Bias AdvantagesBoost performances
Improve power efficiency
Enable leakage reduction
Enable area reduction
Reduce process dispersion
Allow compensation techniques
11
Process Compensation Through FBB
• Process compensation through FBB allows• Masking SS-FF process spread• Recovering +17% speed in 28nm FD-SOI, at no dynamic power expense
0,1
1
10
100
0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7
Leak
age
Pow
er @
1.0
V/12
5C (m
W)
Frequency @ 0.8V/WC_temp (GHz)
SS
TT
FF
Lmin
+4nm
+10nm
+16nm
FFTT
SS
Speed/Leak Vt distribution across process corners
1
10
100
0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7
Leak
age
Pow
er @
1.0
V/12
5C (m
W)
Frequency @ 0.8V/WC_temp (GHz)
SS FBB 500mV
TT FBB 250mV
FF 0FBB
WC
Lmin
+4nm
+10nm
+16nm
WC
+17%
Compensated Worst Case Speed/Leak Vt distribution
Com
pens
ated
de
sign
12
Design examples in 28nm FD-SOI- from building blocs to SoC’s
A Digital Delay Line with Coarse/Fine tuningthrough gate/body biaising in 28FDSOI
• Novel low power design architectures for 60GHz receivers enabled by FDSOI: DFE with un-clocked delay feedback, searchminimum delay spread at 2GS/s data rate
• Total delay >10ns• Granular delay < 500ps
• FDSOI specific unity delay cell (thyristor revisited):
• Body bias control for rising/falling edge delayfine tuning
• Gate control for coarse delay tuning• Complementary input scheme for reduced
power consumption
• State of the art results: ultra wide range linear control, fs/mV sensitivity and energy efficiency
[I. Sourikopoulos et al., ESSCIRC2016]
Gate controlBody control
14
28FD-SOI Distributed Oscillator at 134 GHz and 202GHz15[R. Guillaume at al, RFIC2017]
• The oscillation frequency depends on:• The electrical Tline parameters• The transistor inverting properties around Fosc (Fmax)
• The highest Fosc topology proposed so far in a 28nm node• Phase noise optimization through body bias tuning• Oscillation frequency measurements, histogram over 8
locations on a wafer: • <0.1% variation simulation vs measurements Very
small on wafer dispersion
Oscillation frequency(Fosc)
Simulation : = 134.14GHz
Theory : = 134.2GHz
Measurement average
H21
U-20dB/dec
Dra
in
Sour
ce
Dra
in
Sour
ceGate
Gate
Top View Cross Section
mmW transistor integrationexample and freq. parameters
A 128 kb Single-Bitline 8.4 fJ/bit 90MHz at 0.3V 7T Sense-Amplifier-less SRAM in 28nm FD-SOI
• 7T SRAM architecture with new: single clock cycle and low area booster, decoding scheme and read architecture (no sense-amplifier)
• Energy efficiency achieved by keeping the storage-elements at ULV, whereas critical nodes are boosted
• Intensive body biasing design• State of the art performance:
• 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access• the minimum operating voltage is 240mV • the retention voltage is 200mV
16
[B. Mohammadi et al., ESSCIRC2016]
Pixel Pitch-Matched Ultrasound Receiver in 28FDSOI
First proof-of-concept pitch-matched fully-digital subarray beamformer IC for 3D ultrasound
• Highest per-channel SNR with ~7x area reduction
FDSOI Technology Enabler:• High integration density • Immune to latch-up allow the use of
slewing-based amplifier using minimum length cascaded inverters
• Low Vth devices provide area-efficient low Ron switches
Inverter-based amplifier in SC M
[M-C. Chen et al., ISSCC2017 and JSSC Dec2017]
SleepTalker - 28nm FDSOI ULV WSN Transmitter: RF-mixed signal-digital SoC
• IR-UWB BPSK and BPM RF transmitter operated at 0.55V• IEEE 802.15.4a compliant• 3.5 – 4.0 – 4.5GHz channels reconfiguration• Configurable Data Rate: 0.11, 0.85, 1.7, 6.81, 27.24Mb/s• RF SoC: digital and RF transmit path, frequency synthetizer, DC-DC (1.2V to 0.55V) and
Body Bias Generator (up to +/-1.8V, for variable output voltage)• SoC architecture innovation enabled by FDSOI:
• Extremelly low power PLL-free architecture with aggressive duty cycling, compensated by on chip adaptive FBB for Local Oscillator tuning and trimming upon the requested transmit frequency
• Digital Power Amplifier with programmable pulse shaping enabled by body biasing control, meeting FCC spectral regulation for all channels
• High speed – ultra low voltage digital implementation enabled by FBB• Record energy efficiency improving by 16 the State of the Art (Tx: 14pJ/bit, SoC: 24pJ/bit)
[G. de Streel , D. Bol et al., VLSI2016 and JSSC2017]
18
A 128x8 Massive MIMO Precoder-Detector in 28FDSOI• Flexible solution wrt to
classical 4x4 MIMO implementations, improves by 12dB arrayand 2X spatial multiplexing gains
• Hardware reuse, clock-gating, body biasing
• Uses FBB and RBB for performance-power trade-off and fine tuning of PVT
• The donwlink pre-coder QRD unit has the highestreported energy efficiency@lowest reported area cost
• Uplink detector shows the highest reported energyefficiency and area efficiency detection
19
[H. Prabhu et al., ISSCC2017]
ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI
Energy efficient FDSOI-enabled processor for deep neural network inference• Local processing in connected objects• Complete processor with state-of-the-art energy efficiency
• Up to 10TOPs/Watt
• Approximate computing techniques exploiting body biasing• Scaling 2-16bit accuracy, for >10x efficiency improvement with different
bias settings for each accuracy level
• 18% energy efficiency gains due to body bias
Throughput [GOPS]
BBopt
30025 75 150
8.2TOPS/W1
10.6
1
.8
0.1Throughput [GOPS]
75 150 30025
8.2TOPS/W
0.61V
10TOPS/W
0.63V
BBnom
Eff.
[TO
PS/W
]Vol
tage
[V]
+
*
o
30-60% Sparse 4x3-4b
4x4b
2x8b
1x16b
[B. Moons et al., ISSCC2017]
Fine-Grained AVS in 28nm FDSOI Processor SoC• Energy-efficient FDSOI-enabled processor SoC
featuring:• Intensive deployment of body biasing techniques
• Integrated voltage regulation• 82-89% system efficiency with adaptive clocking
• Fully-featured processor (RISC-V Rocket Processor)• 41.8 DP GFLOPS/W with integrated regulators
• Integrated power management• Low-overhead power estimation• Programmable PMU
• Sub-µs adaptive voltage scaling (AVS)• Up to 40% energy savings
• Compact implementation:• Core area: 1.07mm²• 568k Std Cells
• Boots Linux
Async. FIFO/Level shiftersbetween domains
CORE (1.07 mm2)
UNCORE
16KB ScalarInst. Cache
(Custom 8T SRAM Macros)
32KB Shared Data Cache
(Custom 8T SRAM Macros)
8KB VectorInst. Cache
(Custom 8T SRAM Macros)
To/from off-chip FPGA FSB and DRAMDigital IO pads to wire-bonded chip-on-board
Rocket Core
Vector AcceleratorVector Issue Unit
Vector Memory Unit
...
...int int int int int
(16KB Vector RF uses eight custom 8T SRAM macros)
Crossbar
ScalarRF FPU
int
Arbiter
INTEGRATED MEASUREMENT
Clock Counter Set body bias
Set DC-DC Vout
Programmable current mirror load
Vout waveform reconstruction
SRAMBIST
Back-BiasGenerator
NWELL PWELL
Functional units (64-bit Int. Mul., SP/DP FMA)
Branch Prediction1.0V1.8V
48 switched-capacitorDC-DC unit cells
DC-DC controller
Adaptive clockgenerator
Vout
...
DC
DC
togg
le
+
FSM Vref
core clk
Toscope
1.0V
Toscope
VOLTAGE AND CLOCK GENERATION (0.4 mm2)
POWER MANAGEMENT(0.1 mm2)
Toggle Counter Z-scale PMU
8KB Scratchpad Iref
Iload
Rocket Processor and Vector Accelerator
SC-D
CD
C U
nit C
ells
Adaptive Clock Generator
PMU
SC-DCDC ControlPower Measurement Counters
SC-D
CD
C U
nit C
ells
[B. Keller et al., ESSCIRC2016 and JSSC2017]
21
Conclusion
Takeaways for Analog/RF/mixed-signal body biasing• Unprecedented very wide VT tuning range of ~250mV for FDSOI
vs ~10mV for bulk
• New “tuning knob” with no parasitic effects on the signal path (control under the BOX)
• Enhanced switches performances for all type of mixed-signal circuits
• Efficient revisited tuning/trimming strategies:• Process/Temperature compensation• Circuit reconfiguration
• Flexible and energy saving SoC solutions
• Simpler circuits revisit State of the Art Efficient Flexible Simple
23
FD-SOI will Enable the Ultimate Integrationfor Tomorrow’s Connected World
Performant Ft / Fmax,Performant passive devices
Improved noise,Lower parasitic capacitances
Adapt power consumption to load
Ultra low voltage operations with high performance.
Easy and efficientanalog integration
(ADC/DACs, RF, LDOs, …)
FBB for dynamic power/ leakage/ frequency tuning
Excellent reliability and soft-error performances
Network infrastructureThe Internet of Things
Enterprise& Cloud Datacenter
CoreNetwork
Access Network
BackhaulMobile
Network
Radio Access Network
Smart City
Healthcare
Smart Home
Smart Car
Smart Industrial
Performance and power efficiency
5G
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…. and in BiCMOS55
B55 Design of Low-Power Active Tags for Operation with 77-81 GHz FMCW Radar[M.S. Dadash et al., IMS2017 and MTT2017]
• 1st low‐power W‐band active‐tag in 55nm SiGe BiCMOS
• 19dB gain, 9GHz BW, and NF50< 9 dB
• Wake‐up function with ‐62dB sensitivity
• 25/10.8mW in active/stand‐by mode from 2.5/1.8 V supplies.
0.57 mm x 0.88 mm
20mm x 23 mm
Modulator
Activate
GC1
GC2
VGA
VGA
Vmod
3-StageLNA
SOISiGe
Detector
Vdet
450fF
2.5 V
150pH : 450pH
IN
Vbias
450fF
2.5 V
450fF
GC
70fF
300pH:100pH
320pH 2.5 V
500Ω
450fF
450fF
OUTTL
20fF
1.5mA
450fF 450fF 450fF
30pH : 30pH
450fF 450fF
100fF
220pH
130pH
220pH
130pH
450fF
100fF
Vbias Vbias Vbias
RFout
1.5mA
2kΩ 2kΩ 2kΩ
450fF 450fF
1.5mA
1.5mA110fF
RFin
2.5 V
100fF
VDET
IN
640fF
320pH
50µA
270fF270fF
2.5 V
450fF
25fF70pH : 250pH
IN
Vbias
2.5V
450fF
0.45mA
0.45mA
450fF
2.5 VOUTP OUTNVmod
VGAModulatorDetectorLNA
A Compact 130 GHz Fully-Packaged Point-to-Point Wireless System with 3D-Printed 26dBi Lens Antenna Achieving 12.5Gbps at 1.55 pJ/bit/meter
PCB
AiP
Chip
TX RX
PCB
AiP
Chip
TXD
ata I
n
Buffer CurrentSwitching
PA
2:1
2.7V
TXR
F Out
VCO
OOK TXR
XR
F In 1:1
Vb,LNA
LNA
1.5V
1:1
Vb,
ED
ED Buffer
RX
Dat
a Out
OOK RX
Biasing TXD
ata I
n
Buffer CurrentSwitching
PA
2:1
2.7V
TXR
F Out
VCO
OOK TX
RX
RF I
n 1:1
Vb,LNA
LNA
1.5V
1:1
Vb,
ED
ED Buffer
RX
Dat
a Out
OOK RXBiasing
VCOtune VCOtune
01 1 1
0 0
OOK Signal
Fully-Packaged System
PCB
IC
Antenna-in-
Package
3D-Printed Lens
feed
BGA Package Stack-Up
Prepreg (75μm)
RO4003 (200μm)
Aperture-coupled patch antennas
Prepreg (75μm)
7x7mm2TopBottom
Ring CavityFeed PatchesIC Footprint
RF Pads
1mm
Antenna-in-Package
(1.62x1.98mm2)
TX
RX
TRX Power Consumption <100mW
OOK Transceiver Performance: A low-cost, energy efficient, high-capacity,
scalable, easy-to-deploy, and fully-packaged point-to-point wireless link using OOK modulation.
Measurement results verify 12.5Gbps OOKdata transmission over 5m.
Energy/bit/range FoM is improved >40xcompared to the state-of-the-art.
Enabled by high gain antenna, efficientand low-cost packaging, and efficient TRXdesign.
B55 Technology Enablers:- High integration density.- Combined RF/baseband solutions using
BiCMOS technology.- High fT/fmax enabling high-frequency
operation.- High output power enabled by high
performance and efficient BJTs.
40mm
[Nemat Dolatsha, et al. ISSCC 2017]
ST and the CMP• A continued collaboration since almost 30 years
• Win-win operation• Recognized by ST as best service unit for SME and research institutes• Supports ST’s customers for small volume business• Creating ecosystem in advanced More Moore and More Than Moore Silicon
technologies
• The CMP: a professionnal team dedicated to their Users’ best experience in designing and prototyping IC’s
28
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