IBM Systems and Technology Group
Package Model Proposal | Dec 2007
Title: Package Model Proposal
Source: Nanju Na ([email protected]) Jean Audet ([email protected]),David R Stauffer ([email protected])
IBM Systems and Technology Group
Date: Dec 2007
Abstract: New package models are proposed to represent package responses of real world industry packages available for high speed applications today and to reflect realistic package behavior
IBM Systems and Technology Group
Package model proposal | Dec 2007
Agenda
High speed packaging and modeling challenges
Package behaviors in measured S-parameters
Package behavior in existing IEEE package models
3D EM modeling of package structures
New models proposed
IBM Systems and Technology Group
Package model proposal | Dec 2007
High speed packaging and modeling challengesGreater impact of high frequency package behavior on signal integrity of Multi-Gbps and up Various discontinuity components exist in package signal path and impact
package behavior at high frequencies Using real world package model with high frequency well
characterized is critical to reasonable channel analysis and realization 3D package modeling vital to capturing accurate high frequency
behavior
Manufacturing process and environmental factors to high frequency performance Process variation; impedance tolerance Surface roughness – higher loss at high frequencies Material loss – higher loss factor at high frequencies Temperature/humidity effect on high frequency loss
Design factors for performance as cost-performance tradeoff Design development for high frequency performance improvement Signal behavior is affected by wiring scheme associated with wiring density Impedance control along discontinuity paths
IBM Systems and Technology Group
Package model proposal | Dec 2007
Packaging for ASIC high speed applications Cost-performance as primary factor for package selection in average ASIC networking market space
Increasing bandwidth demand: link density to noise isolation
Package size-layer count versus loss-coupling
Organic laminates are prevailingly popular with its cost-performance effectiveness – matured technology
Various with layer build-up construction technologies; thin core/thick core/coreless
limited layer count but high wiring density per layer enabled by low dielectric constant with manufacturing technology advancement
Relatively lossy material
Ceramic – matured technology Excellent reliability and low loss material
Poor cost-performance competitiveness
Shrinking application space
Other packaging developments for general ASIC networking applications Process/material NOT developed or matured to make performance leap in any visible
future
IBM Systems and Technology Group
Package model proposal | Dec 2007
Package high frequency behavior characterized in measured S-parameters and TDR waveforms
-Measurements on actual product packages of a high speed link application-Compared with existing IEEE package models for real package responses
IBM Systems and Technology Group
Package model proposal | Dec 2007
Insertion loss measured on 35mm packages
Organic laminate Ceramic
[dB]
[dB]
[dB]
[GHz] [GHz]
[GHz]2 4 6 8 10 12 14 16 180 20
-6
-4
-2
-8
0
Glass Ceramic
Design factor to performance
Differential insertion loss displayed
Various design nets measured in each package
Transmission varies with trace length, routing via configuration and reflection of the structure (next slide)
IBM Systems and Technology Group
Package model proposal | Dec 2007
Return loss measured on 35mm packages
Organic laminate Ceramic
[dB]
[dB]
[dB]
[GHz]
[GHz]
[GHz]
2 4 6 8 10 12 14 16 180 20
-40
-30
-20
-10
-50
0
Glass Ceramic
Differential return loss displayed
Reflection pattern differs with routing paths/configurations in each package
IBM Systems and Technology Group
Package model proposal | Dec 2007
[Ω]
C4 pads open
Package-board interface (BGA)
[Ω]
[Ω][Ω]
BGA
C4 pads open
Probing on C4 pads Probing on C4 pads
Probing on board pads Probing on board pads
Board pads openBoard pads open
Package discontinuities in measured TDR waveforms
IBM Systems and Technology Group
Package model proposal | Dec 2007
Existing IEEE package modelsLossless transmission line??
*product packages are lossy.
IBM Systems and Technology Group
Package model proposal | Dec 2007
Non-representative package behavior of IEEE models
2 4 6 8 10 12 14 16 180 20
-10
-8
-6
-4
-2
-12
0
2 4 6 8 10 12 14 16 180 20
-40
-30
-20
-10
-50
0
100 200 300 400 500 600 7000 800
60
80
100
40
120
Differential insertion loss
Differential return loss
Differential TDR waveform of Cap-like model, probed from PWB pins
[ps]
[dB]
[GHz]
Cap-like pkg
Ind-like pkg
[dB]
[GHz]
Cap-like pkgInd-like pkg
Modeled using lossless transmission lines (??) while physical packages are lossy.
Extremely exotic behavior of inductor-like package model which is not plausible in real packages.
Too high return loss in both models
Silicon side pins terminated with 50Ωs
Non-real package behavior
Too high reflection in both
Too small loss orUnrealistically large reflection bounces
IBM Systems and Technology Group
Package model proposal | Dec 2007
3D electromagnetic modeling can capture high frequency behavior of package physical structures with multiple discontinuities
IBM Systems and Technology Group
Package model proposal | Dec 2007
Typical signal path in organic flip-chip BGA packages consists of multiple discontinuities
C4Buildup via Trace (controlled impedance)
Buildup via
Jogging trace PTH via Buildup
via
Jogging trace Solder ball
Trace differential pair
PTH vias
Solder ball pair
Buildup vias, jogs
C4
BGA
Each transition introduces large or small discontinuity and adds reflection and loss
capaci
tive
capacit
ive
Manufac
turing
variat
ion
IBM Systems and Technology Group
Package model proposal | Dec 2007
3D EM modeling captures high frequency behavior of physical structures
OTX_B64T_OUT1
IBM Systems and Technology Group
Package model proposal | Dec 2007
Package loss increases with size: 23/35/42/55mm
2 4 6 8 10 12 14 16 180 20
-5
-4
-3
-2
-1
-6
0
freq, GHz
2 4 6 8 10 12 14 16 180 20
-40
-30
-20
-10
-50
0
freq, GHz
Return loss from BGA Insertion loss
Trace impedance 100Ω
23mm35mm42mm
55mm
Up to 55mm by JEDEC standard for BGA packageLonger interconnect assumed for larger package size
2 4 6 8 10 12 14 16 180 20
-40
-30
-20
-10
-50
0
freq, GHz
2 4 6 8 10 12 14 16 180 20
-5
-4
-3
-2
-1
-6
0
freq, GHz
Trace impedance 115Ω
IBM Systems and Technology Group
Package model proposal | Dec 2007
Performance varies with design and physical layer construction
2 4 6 8 10 12 14 16 180 20
-40
-30
-20
-10
-50
0
freq, GHz
2 4 6 8 10 12 14 16 180 20
-40
-30
-20
-10
-50
0
freq, GHz
2 4 6 8 10 12 14 16 180 20
-5
-4
-3
-2
-1
-6
0
freq, GHz
2 4 6 8 10 12 14 16 180 20
-5
-4
-3
-2
-1
-6
0
freq, GHz
Differential return loss Differential insertion loss
Trace impedance 100Ω
Trace impedance 115Ω
Thin core
PTH via routing under die
Thick core*55mm package
IBM Systems and Technology Group
Package model proposal | Dec 2007
Performance varies with routing scheme/design strategy
(1) Small PTH via pitch under die (2) Small PTH via pitch above BGA
(3) PTH vias aligned with BGA[dB]
(2)
(3)(1)
Differential insertion loss
Ref: Nanju Na et. al., “Discontinuity impacts and design considerations of high speed differential signals in FC-PBGA packages with high wiring density”, IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 107-110, Austin, Texas, Oct. 24-26, 2005.
There is design trade-off in wiring density-performanceHigh performance design option is preferable for high speed data transmission.
Chip pads
Solder balls
Chip pads
Solder balls
Chip pads
Solder balls
IBM Systems and Technology Group
Package model proposal | Dec 2007
Impedance tolerance 15% is achievable
1
23
4
5
6
Line ShapeLine width +/- X μmLine thickness +/- Y μmDielectric thickness +/- Z μm
Impedance distribution in measured TDR waveforms
Design target impedance of differential pairs is 100Ω.
!15% impedance variation after manufacturing is manageable with current packaging technology 85Ω to 115Ω at 3σ distribution
3σ statistics
Ref: Jean Audet et. al, “Manufacturing Impedance Tolerance Control for High Speed Data Link Applications”, IEEE 56th Electronic Components and Technology Conference, pp. 1023-1028, 2006.
IBM Systems and Technology Group
Package model proposal | Dec 2007
Package coupling cannot be ignored in moderate to high density packages and needs to be considered in channel analysis
IBM Systems and Technology Group
Package model proposal | Dec 2007
Package coupling as part of package behavior
Trace coupling involved in moderate to high package wiring density, moderately manageable
Wiring density-isolation is an ASIC cost-performance factor
PTH via/ BGA coupling factor to BGA assignments - package size
Ref: Nanju Na, et. al., “Design Optimization for Isolation in High Wiring Density Packages with High Speed SerDes Links”, IEEE 56th Electronic Components and Technology Conference, pp. 187-193, San Diego, Cal. May 30-June 2, 2006.
IBM Systems and Technology Group
Package model proposal | Dec 2007
Measured near-end crosstalk in high density packages
2 4 6 8 10 12 14 16 180 20
-80
-60
-40
-20
-100
0
freq, GHz
dB(S
(1,2
))dB
(S(1
,1))
2 4 6 8 10 12 14 16 180 20
-80
-60
-40
-20
-100
0
freq, GHz
dB(S
(1,2
))dB
(S(1
,1))
2 4 6 8 10 12 14 16 180 20
-80
-60
-40
-20
-100
0
freq, GHz
dB(S
(1,2
))dB
(S(1
,1))
2 4 6 8 10 12 14 16 180 20
-80
-60
-40
-20
-100
0
freq, GHz
dB(S
(1,2
))dB
(S(1
,1))
Coupling controlled in design
High coupling seen in a
high density Ceramic
Probed on chip pads of two neighboring pairs with solder balls open
Near-end pair to pair differential coupling
IBM Systems and Technology Group
Package model proposal | Dec 2007
Package model proposal
-Organic flip-chip package modeled as a representative packagecost-performance effective and readily available with matured technologymost popular in SerDes application spaceperformance comparable among different organic package typesdesign routing option for better transmission
-Size: 23mm/55mm (as max. specified by JEDEC)-Impedance tolerance !15% for packaging industry reality-Coupling consideration for reasonable ASIC wiring density
IBM Systems and Technology Group
Package model proposal | Dec 2007
Package model #1: Pkg55mm_T33mm115ohm_highBGAcoupling.s8p
++
HFSS model:extracted C4 escape
HFSS model:33mm, Zd=115Ω,Pair coupling -35dB
HFSS model:PTH vias/BGA balls
13
57
24
68
55mm package: JEDEC standard maximum33mm trace (considered longest) with 15% impedance tolerance considerationHigh BGA coupling
IBM Systems and Technology Group
Package model proposal | Dec 2007
2 4 6 8 10 12 14 16 180 20
-40
-30
-20
-10
-50
0
freq, GHz
2 4 6 8 10 12 14 16 180 20
-60
-40
-20
-80
0
freq, GHz
2 4 6 8 10 12 14 16 180 20
-4
-3
-2
-1
-5
0
freq, GHz
2 4 6 8 10 12 14 16 180 20
-60
-40
-20
-80
0
freq, GHz
Differential pair behavior of the proposed model #1[dB] [dB]
[dB] [dB]
Insertion loss Return loss
Far-end crosstalk Near-end crosstalk
IBM Systems and Technology Group
Package model proposal | Dec 2007
Package model #2: Pkg55mm_T33mm115ohm_lowBGAcoupling.s8p
++
HFSS model:extracted C4 escape
HFSS model:33mm, Zd=115Ω,Pair coupling -35dB
HFSS model:PTH vias/BGA balls
13
57
24
68
55mm package: JEDEC standard maximum33mm trace (considered longest) with 15% impedance tolerance considerationLow BGA coupling
IBM Systems and Technology Group
Package model proposal | Dec 2007
Package model #3: Pkg35mm_T21mm115ohm_highBGAcoupling.s8p
++
HFSS model:extracted C4 escape
HFSS model:21mm, Zd=115Ω,Pair coupling -35dB
HFSS model:PTH vias/BGA balls
13
57
24
68
35mm package21mm trace (considered longest) with 15% impedance tolerance considerationHigh BGA coupling
IBM Systems and Technology Group
Package model proposal | Dec 2007
Package model #4: Pkg35mm_T21mm115ohm_lowBGAcoupling.s8p
++
HFSS model:extracted C4 escape
HFSS model:21mm, Zd=115Ω,Pair coupling -35dB
HFSS model:PTH vias/BGA balls
13
57
24
68
35mm package: JEDEC standard maximum21mm trace (considered longest) with 15% impedance tolerance considerationLow BGA coupling
IBM Systems and Technology Group
Package model proposal | Dec 2007
Back-up
IBM Systems and Technology Group
Package model proposal | Dec 2007
Probing for package net measurements
OIF Forum: Technical and MA&E Committees Meeting, Nov 6-8, 2007
Package model proposal | Dec 2007
Major design-performance components in organic laminatesTrace
• Electrically long – significant impact if not controlled well
• Impedance control with manufacturing tolerance
• Design for impedance vs coupling in die escaping region
PTH vias• Relatively large discontinuity path along vertical signal transition
through high dielectric core
• Impedance effect of via hole/land/pitch
• Coupling effect with various pair patterns
BGA• Very low impedance and high coupling path due to large
geometric volume of the structure interacting with surrounding power/ground
• I/O assignment pattern for isolation
C4 bumps
Core
Solder balls
IBM Systems and Technology Group
Package model proposal | Dec 2007
Simulation to measurement correlation
[GHz] [GHz]
[GHz]
Red: simulationBlue: measurement, includes 3mm board microstrip
Top left: return loss from C4 padsTop right: return loss from BGAsBottom: insertion loss
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