Orit Skorka and Dileepan Joseph University of Alberta, Canada
Reducing Crosstalk in Vertically- Integrated CMOS Image
Sensors
Slide 2
2 Introduction
Slide 3
Vertically-integrated image sensors 3 Vertical-integration is a
new trend in IC design. Each die can be fabricated in a process
optimized for the devices it contains. Image sensors contain
photodetectors, analog circuits, and digital circuits. More degrees
of freedom in the design of the photodetector; no longer limited to
a certain CMOS process.
Slide 4
Vertically-integrated image sensors 4 Vertical stacking allows
more circuits to be placed within the same pixel area. Enables
reasonable pixel dimensions while having: More pixel-level
electronics to improve signal-to-noise ratio (SNR) and dynamic
range (DR); High fill-factor.
Slide 5
5 Background
Slide 6
6 Device structure VI-CMOS image sensor made by flip-chip
bonding
Slide 7
Reduction of crosstalk 7 Crosstalk A situation where signals
reach destinations other than their original ones. Flow of lateral
currents in the light-sensitive semiconductor can cause crosstalk
in the VI- CMOS image sensor shown. Lateral currents are caused by
drift and diffusion of charge carriers.
Slide 8
Reduction of crosstalk 8 One way to prevent flow of lateral
currents is by device patterning. However: Edges of patterned
devices introduce imperfections and defect states; The additional
lithography steps increase the overall manufacturing costs. In
standard CMOS image sensors, the photodetector must have
well-defined borders. Therefore, the problem is unique to VI-CMOS
image sensors.
Slide 9
Reduction of crosstalk 9 The method used here is based on
maintenance of a uniform vertical electric field across the
unpatterned photodetector array.
Slide 10
Primary circuit requirements 10 Although this idea has been
used by Schneider et al., they do not address important design
considerations such as stability and compensation. In standard CMOS
APS image sensors, the read-out is based on the voltage across the
photodetector. Since the photodetector voltage must be kept
constant, its current should be used as the input signal. For an
efficient design, one needs to know the expected range of the
photodetector current, I pd.
Proposed solution 12 With a proper design of the read-out
circuit, a high DR image sensor can be made with a-Si:H
photodetectors. Logarithmic response is preferred because it
supports a higher DR than a linear one. To conclude circuit
requirements: Maintain a constant voltage on the photodetector; Use
I pd as the input signal; Have a logarithmic response to
illuminance.
Slide 13
13 Method
Slide 14
Feedback circuit overview 14 A feedback element varies I pd to
keep node a at a constant potential, V ref. The feedback element
should generate I pd that is related to V out logarithmically. The
resistance, R ph, decreases with illuminance.
Slide 15
Optional circuit topologies 15 There are three main feedback
topologies that achieve a logarithmic response:
Slide 16
Bias point analysis 16 The common-drain is the only topology in
which the feedback loop does not draw current from the op-amp. If I
pd is drawn from the op-amp, I b max(I pd ), which significantly
increases the power consumption.
Slide 17
Optional circuit topologies 17 The NMOS transistor can be
replaced with a PMOS one if an opposite polarity is required.
Slide 18
Small-signal analysis 18 In spite of having a negative
feedback, the pixel circuit might oscillate because phase changes
may result in positive feedback. The frequency response of the
simplified small-signal model shows that the loop gain has two
poles and a finite zero.
Slide 19
19 Results
Slide 20
DC response 20 Two op-amps have been designed: In the
common-drain topology, I b equals 1A; In the others, I b equals
38A.
Slide 21
Compensation capacitor 21 The operating point of the circuit
changes with illuminance, and so does the frequency response. The
phase margin (PM) decreases with illuminance. To ensure PM 60 0 at
all bias points, the value of a compensation capacitor, C C, was
calculated for the highest expected I pd. Two equations (with two
unknowns) need to be solved: |A OL ( f 0dB, C C )| = 1; A OL ( f
0dB, C C ) = 60. The solution gives f 0dB = 29MHz and C C =
60fF.
Slide 22
Loop gain Simplified modelCadence simulation 22
Slide 23
Transient response 23 The transient response is checked to
ensure that the circuit does not oscillate. Transition times are
asymmetric, typical of logarithmic circuits.
Slide 24
24 Conclusion
Slide 25
25 This work introduced circuits to reduce crosstalk in VI-CMOS
image sensors with an unpatterned photodetector array. Flow of
lateral currents can be reduced by applying a constant electric
potential at all pixels of the unpatterned photodetector array. The
read-out circuit is required to: Maintain a constant potential at
the photodetector; Use the photodetector current as the input
signal; Generate a logarithmic response.
Slide 26
Conclusion 26 The circuit is implemented using a logarithmic
amplifier with feedback control. The common-drain configuration is
found to be the most power efficient. A simplified small-signal
model of the circuit has been developed to test the system for
stability and determine the value of the compensation capacitor.
Transient simulations confirm that the circuit does not oscillate
in bright light when C C is added.
Slide 27
Acknowledgments 27 The authors gratefully acknowledge the
support of: Alberta Ingenuity; The Natural Sciences and Engineering
Research Council (NSERC) of Canada; Micralyne Inc; CMC
Microsystems.