NEW READ RETRY
Powerful and automatic solution to improve reading of NAND flash chips
Patryk Płudowski - RUSOLUT
What is Read Retry?
2
1. Command
2. Response
Write Page
Command
Read Retry
Standard
VendorSpecific
Read Page
Read ID
READ RETRY IS A SPECIFIC COMMAND SET TO TWEAK READING MODE
CONTROLLER NAND FLASH
3
Problem with chip reading – bit errors
DATA FROM RAW NAND DATA FROM CONTROLLER
• Read disturb (noise, connection problems)
• Program disturb
• Endurance of cells
• Data retention
Bit error sources
Error Correction Codes (ECC)
No errors Correctable Uncorrectable
Green RedLight green
Am
ou
nt
of
erro
rs Error Correction Capability
ECC CORRECTABILTY IS STRICTLY LIMITED BY ECC CAPABILITYUncorrectable errors can be repaired with Read Retry
4
ECC map
NAND flash internals
5
Pe
riph
erals
PAGE DECODER PAGE DECODER
Me
mo
ry array
Blo
ck
Blo
ck
PAGEPAGEPAGEPAGE
PAGE
PageCELL CELL CELL CELLCELL
PAGE IS THE SMALLEST R/W UNIT
Page decoder
6
Digital data
01101011
Analog data
Page decoderMemory
array
2.3v 2.9v 3.1v 1,7v NAND controller
2.3v >> 012.9v >> 103.1v >> 101,7v >> 11
ANALOG STATES FROM CELLS ARE CONVERTED INTO DIGITAL DATA
*Simplified view
Architecture of cells
7
1 Bit Per Cell2 Levels100,000 P/E Cycles
2 Bits Per Cell4 Levels10,000 P/E Cycles
3 Bits Per Cell8 Levels1,000 P/E Cycles
LOWER ENDURANCE
11
10
01
00
SLC MLC TLC
1
0
111
010
100
001
110
101
000
011V
olt
age
[V]
= St
ore
d d
ata
LARGER CAPACITY
LARGER ECC AREA
8
Thresholds in memory cells
THE DATA IN CELL IS STORED AS A VOLTAGE LEVEL
3.0V
2.2V
2.5V
2.8V
0V
Vo
ltag
e[V
] =
Sto
red
dat
a
11(2)
10(2)
00(2)
01(2)
Zones of detection
1.9V
2.7V
2.4V
2 Bits Per Cell 4 Levels 10,000 P/E Cycles
MLC memory cell
9
Bits inside memory cell
*Simplified view
2.0V
Cell 3
2.0V
Cell 2
Vo
ltag
e[V
] =
Sto
red
dat
a
THE DATA IN CELL IS STORED AS A VOLTAGE LEVELController is reading data according to specific zones
2.2V
2.5V
2.8V
0V
11(2)
10(2)
00(2)
01(2)
Cell 1 Cell 4
2.9V 3.0V
Zones of detection
MLC memory cellCycle 1 2 3 4 HEX
Initial 10 11 11 10 BE
10
Retention Error
Cell 1 Cell 4V
olt
age[
V]
= St
ore
d d
ata
2.7V2.75V
WHEN CHARGE LEAKS OUT FROM CELL WE GET BIT ERROR
*Simplified view
2.2V
2.5V
2.8V
0V
11(2)
10(2)
00(2)
01(2) Zones of detection
Cycle 1 2 3 4 HEX
Initial 10 11 11 10 BE
Default read 00 11 11 00 3C
2.0V
Cell 3
2.0V
Cell 2
MLC memory cell
11
Read-Retry Mechanism
2.5V
2.8V
2.7V
2.75V
Cell 4Cell 1
Default read
10(2)
00(2)
Vo
ltag
e[V
] =
Sto
red
dat
a
WHEN CHARGE LEAKS OUT FROM CELL WE GET BIT ERRORDegraded cell gives wrong data
*Simplified view
Cycle 1 2 3 4 HEX
Initial 10 11 11 10 BE
Default read 00 11 11 00 3C
MLC memory cell (focused view)
READ RETRY MECHANISM HELPS TO SHIFT READ VOLTAGE THRESHOLDS
12
Read-Retry Mechanism #1
Vo
ltag
e[V
] =
Sto
red
dat
a
Shift threshold – atempt 1
Default read
*Simplified view
2.5V
10(2)
2.72V00(2)
2.75V
Cell 4Cell 1
2.7V
Cycle 1 2 3 4 HEX
Initial 10 11 11 10 BE
Default read 00 11 11 00 3C
Atempt #1 00 11 11 10 3E
MLC memory cell (focused view)
13
Read-Retry Mechanism #2
Vo
ltag
e[V
] =
Sto
red
dat
a
Default read
READ RETRY MECHANISM HELPS TO SHIFT READ VOLTAGE THRESHOLDS
Shift threshold – atempt 2
*Simplified view
2.5V
10(2)
00(2)
2.75V
Cell 4Cell 1
2.7V2.68V
Cycle 1 2 3 4 HEX
Initial 10 11 11 10 BE
Default read 00 11 11 00 3C
Atempt #1 00 11 11 10 3E
Atempt #2 10 11 11 10 BE
MLC memory cell (focused view)
Sets of parameters
14
ALL ZONES NEED TO BE ADJUSTED SEPARETLY
Default threshold
Default threshold
Default threshold
2.2V
2.5V
2.8V
0V
Vo
ltag
e[V
] =
Sto
red
dat
a
11(2)
10(2)
00(2)
01(2)
2.1V
2.4V
2.7V
0V
11(2)
10(2)
01(2)
00(2)
2.08V
2.55V
2.81V
0V
11(2)
10(2)
00(2)
01(2)
SHIFTED READ THRESHOLDS
DEFAULT THRESHOLD THRESHOLD SET #1 THRESHOLD SET #2
DIFFERENT PARAMETERS PRODUCE DIFFERENT ERROR RATE
Read Retry effect
15
15
13
11
10
8
6
5
2
0
2
3
7
Amount of errors SET -5SET -4SET -3SET -2SET -1DefaultSET +1SET +2SET +3SET +4SET +5SET +6
?resS any?koy to r?`ooTQresS any kgy to rebootPresS any kgy to rebootPress any key to rebootPress any key to rg2ootPress any key tk Rg??otPress an? +ey tk Rg?ootPress an? +ey ?k Rg??otPress`a~? +ey ?? Rg??otPre{s`a~? +ey ?? Zg??otPve{s`a|? +%y ?? Zw??otPveos`?|? +?y ??jZw??ot
CORRECT
New firmware which allows us to read chips faster and change NAND protocol instantly
16
What we did to implement Read Retry?
We made new universal software platform just to start Read Retry analysis
17
More than 500 devices analyzedTO UNDERSTAND what controller does to improve reading
18
And finally after ~2000 human hours we made an automatic and smart Read Retry algorithm in VNR
19
Read Retry results compared to normal ECC ReRead
20
1-st pass 2-nd Pass 3-th pass 4-th pass 5th-pass 6-th pass 7-th pass
ReadRetry 73% 87% 100%
ReRead 42% 55% 64% 69% 73% 75% 77%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Co
rre
cte
d e
rro
rsEffectiveness of correction
READ RETRY HELPS TO CORRECT ERRORS FROM ANY SOURCEWhen ReRead corrects errors caused only by read disturb
Already supported chips
21
Almost all chips of:
Micron, Intel2C64444BA989A4E53CA52C84643CA52C846454A92C68044AA9B5646454A4
….
Sandisk, Toshiba453C86937A983A95937A983AA89276983C95937A453C96937645DE94937645DEA49276454CA8A276453E9B927E
….
Most popular of:
SamsungECDEA47A68ECD7947E64ECD798CE74ECDE98CE74
ECD798CAECDED9CA
….
HynixADD7149E34ADDE14A742ADD794DA74ADDE14AB42ADDE94EB74ADD7949160
….
MUCH MORE SOON
SUMMARY• READING NAND FLASH WITH READ RETRY HELPS TO ADJUST READING PROTOCOL AND SIGNIFICANTLY IMPROVE
QUALITY OF DATA
• ALL NEW CHIPS HAVE A BUILT-IN READ RETRY MECHANISM AND ITS USAGE IS THE ONLY PROPER WAY TO EXTRACT PHYSICAL IMAGE
• WORKING BETA VERSION IS RELEASED IN VNR 3.5.
• IN CURRENT VERSION OF SOFTWARE IT IS SPECIFICALLY DESIGNED FOR PARTICULAR MEMORY CHIP
IT IS A AVAILABLE BY REQUEST AT: [email protected]
22
LET’S MOVE TO PRACTICAL PART
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