© 2010 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Berkeley, 3-4 November, 2011
Nanowire Tunnel FETs
M. Björk, H. Schmid, K. Moselund, C. Bessire, H. Ghoneim, S. Karg, E. Lörtscher and
Heike Riel
IBM Research – Zurich
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
2
Roadmap of Energy Efficient Devices
Adapted from A. Ionescu
?
CNT
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
3
Roadmap of Energy Efficient Devices
Supply voltage is biggest lever to address power performance trade-off
Tunnel FETs can achieve S < 60 mV/dec.
Tunnel FETs – the most promising steep slope device.
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
4
Outline
All-Si Nanowire Tunnel FETs &
Esaki Diodes
Towards InAs/Si Heterostructure
Tunnel FETs
– InAs/Si Heterostructure Diodes
– First Demonstration of InAs/Si NW Tunnel FETs
Summary
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
5
Tunnel FET – The Principle
Source Drain
TFET: Gated p-i-n structure (p-type tunnel FET)
Reverse bias: band-to-band-tunneling (BTBT)
OFF state VDS = negative
VGS = 0V
No current flows
EC
EV
n+
i
p
ON state VDS = negative
VGS = negative
Holes are injected into the channel via BTBT
EC
EV
n+
i p
T. Baba JJAP 1992
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
6
Tunnel FET Functionality
Inter-band Tunnel FET requirements:
Steep slope Strong modulation of channel bands by gate (l)
Abrupt doping profile
Optimized source doping level
Ion high Small bandgap at source-channel tunneling point
Ioff low Wide(r) bandgap at drain-channel “contact” point
J. Knoch et al. SSE vol. 51, 2007
J. Appenzeller TED, 2005
BTBT acts as bandpass filter cutting off the tails of
the Fermi distribution
Effectively cooling down the system
S < 60 mV/dec possible Filtering of the
Fermi function
source channel
EC
( )
+ DF - =
G
G WKB
tunneling on E qh
E m T I
3
2 4 exp ~
2 / 3 * l
Needed for
high TFET
performance {
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
7
All-Si Nanowire Tunnel FET – Implementation
Vapor-Liquid-Solid (VLS) grown and in situ doped
No high temperature anneal required to activate dopants
n++ (source) phosphorous 1.5x1020 cm-3 (solubility limit)
i (channel) not intentionally doped
p (drain) boron ~5x1018 cm-3
p-segment is tapered due to SiH4/B2H6 reactivity
Wire diameters: 10 - 80 nm
Gate oxide used: SiO2, HfO2, Al2O3
500 nm
Growth direction
p+ shell taper BTBT junction
Si Nanowire Tunnel FET
H. Schmid et al. J. Appl. Phys., 103 (2008)
H. Schmid, et al, Nano Letters, 9, 173 (2009)
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
8
All-Si Nanowire Tunnel FET – Results
Ion: HfO2 = 0.1 mA/mm
SiO2 = 0.025 mA/mm
(VDS=-1V, VGS=-2V)
Improves with high-k due to
improved λ
Ioff : ~ 10-7 mA/mm
Avg. slope Point slope
HfO2 = 120 90 mV/dec
SiO2 = 200 60mV/dec
(10-7 to 10-3mA/mm)
5nm HfO2, dNW= 50nm, l=14nm
20nm SiO2, dNW= 40nm, l= 23nm
K. Moselund et al.,
ESSDERC, 2009
Improve:
Doping concentration
High-k gate oxide quality
Thinner wire diameter
Junction abruptness
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
9
Proof of Tunnel FETs
Property Observation
(1) Id vs Vds Superlinear
(2) SS vs. T Constant
(3) Ion vs. T Slightly increasing
(4) SS vs. Id Continually increasing
(5) Ion vs Lg Constant
(1)
(2) (3) (4)
Demonstration and proof of working TFETs but Ion and S need improvement
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
10
Tunneling – Importance of Doping Level & Interface Abruptness
Grown p-n Junction:
VLS-grown and in-situ doped SiNW p-n junction
Doping levels: NA ~ 5·1018 cm-3 , ND = 1.5·1020 cm-3
Wire diameter: 60 nm
Ideality factor of = 2.3
Very low TUNNELING in reverse direction & no NDR !!
Too low doping and / or not sharp enough doping profile
p-n Junction
100 nm
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
11
Tunneling – Importance of Doping Level and Interface Abruptness
p-n Junction:
VLS-grown in-situ n-doped Si nanowire
on p-Si <111> substrate
Wire diameter: 60 nm
Doping levels: NA ~ 1·1020 cm-3
ND ~ 1·1019 cm-3
Improved tunnel junction
n+ SiNW
p+
Au tip
Peak-to-valley-ratio
(PVCR) 1.9 – 4.1
forward reverse
Si Nanowire Diode Fabrication
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
12
Influence of p-type doping:
Strong dip (negative differential resistance, NDR)
Esaki diodes!
All SiNW diodes grown under identical conditions
Forward and reverse current density increase with
doping level in the substrate
NDR indicates high doping level and abrupt profile
Record high PVCR indicates near ideal
tunnel junctions
~ 9x1019cm-3
~ 6x1019cm-3
Fabricated ‘beautiful’ SiNW Esaki tunnel diodes
p-doping ~1.2x1020cm-3
Tunneling – Importance of Doping Level and Interface Abruptness
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
13
Si Nanowire Diode Properties
Author Year Method PCD PVCR
Franks ‘65 Alloying 1000 3.9
Jorke ‘93 MBE - 2.0
Rommel ‘98 MBE 3200 1.5
Duschel ‘95 MBE 80 2.7
Thompson ‘09 MBE 1500 2.5
Oehme ‘09 MBE 7 3.9
Oehme ‘10 MBE 4 5.1
This work ‘11 VLS 2500 3.8
SiNW based Esaki diodes have excellent device properties
Large reverse current important figure for TFETs
High PVCR = low trap density, required to get steep slope characteristics
ID rev ~ 100 kA/cm2 at 0.4V
NA= 6, 9 and 12x1019cm3 Simulations show that ND at the junction is higher than in the wire:
ND ~ (5-10)×1019 cm-3 at the nanowire side of the junction
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
14
Summary of Published Si TFET Performance
Reference Technology tox tchannel Local SS
[mV/dec]
SS over
min. 2
decs
Ion
[mA/mm] Ion/Ioff Year
W. M. Reddick and G. A. J. Amaratunga, Applied Physics Letters, 1995, Vol. 67, pp. 494-496
P-well, planar 24nm SiO2 ∞ >600 >600 ~0.001 105 1995
P.-F. Wang et al., Solid-State Electronics, 2004, Vol. 48, pp. 2281–2286. C-TFET, planar non-defined
non-
defined ~300 ~300 ~3 10
5 2004
K. K. Bhuwalka et al, Japanese Journal of Applied Physics, 2006, Vol. 45, No. 4B, pp. 3106-3109.
MBE SiGe,
vertical 4.5nm SiO2
non-
defined >400 >400 ~1 10
6 2006
W. Y.Choi, J. D. Lee, and B. Park, Japanese Journal of Applied Physics, 2007, Vol. 46, pp. 2622-2625.
SOI, Mesa, planar
3nm SiO2 non-
defined ~130 ~130 ~0.1 ~10
3 2007
W. Y. Choi, B. Park, J. D. Lee, and T. K. Liu, Electron Device Letters, 2007, Vol. 28, No. 8, pp. 743-745.
SOI, Mesa,
planar 3nm SiO2 70nm 52.8 <60 12.1 10
4 2007
M. T. Björk et al.. Applied Physics Letters, 2008, Vol. 92, No. 193504. VLS, Si NW 20nm SiO2 60nm ~800 ~800 ~0.01 >10
3 2008
F. Mayer et al.., IEDM, 2008, pp. 163-166. SixGe1-xOI 3nm HfO2 20nm x=1: 42
x=0: ~500
x=1: 60
x=0: ~500
x=1: 0.01
x=0: 1
x=1: 104
x=0: 102
2008
T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, IEDM, 2008, pp. 947-949. Strained Ge, DG
Unknown ≥ 5nm
~10nm (DG
~5nm)
~50 ~60 300 105 2008
M. Fulde et al. INEC, 2009 Complementary, fin TFET, SOI
1.6nm HfSiON 1.9nm SiOMN
Wfin=30nm
210 ~250 0.04 ~103 2008
Kim et al. Symp. VLSI Tech. 2009, pp. 178-179. Ge-source, Si
channel SOI 3nm SiO2 70nm ~40 ~60 0.4 >10
6 2009
K. E. Moselund et al., DRC 2009. VLS, Si NW 20nm SiO2 40nm <60 ~100 ~0.3 107 2009
K. E. Moselund et al., ESSDERC 2009. pp. 448-451 VLS, Si NW 5nm HfO2 50nm ~90 ~100 ~0.3 107 2009
D. Kazazis et al., Applied Physics Letters 94, no.
263508, 2009. Ge-OI 6nm HfO2 ~60nm 469 >400 ~2 <10
2 2009
C. Sandow et al. Solid-State Electronics, Vol. 53, 10, 2009
Thin SOI 3.5, 4.5nm
SiO2 20nm 300 ~300 ~0.05 ~10
4 2009
Z. X. Chen et al. Electron dev. Lett. Vol. 30, pp.754--
756, 2009
Eched vertical
SiNW 4.5nm SiO2 200nm ~70 ~70 53 ~10
7 2009
Nah et al. (Tutuc) GeSixGe1-x core-
shell NW 5.5nm HfAlO2 36nm ~370 ~370 5 ~10
3 2010
D. Leonelli et al. ESSDERC 2010, p.170-173 Thin SOI 2nm HfO2 on
1nm SiO2 65nm ~100 ~100 46 (pTFET) >10
6 2010
K. Jeon et al. VLSI, pp. 121-122 SOI, with NiSi +
pocket (gFET)
0.9nm EOT
(HfO2) 40nm 46 ~46 1.2 ~7x10
7 2010
Gandhi, R et al. IEEE Electron Device Letters, 2011, 32, 437-439
Si vertical etched NW
4.5nm thermal SiO2
20-200 30 50 0.02 ~105 2011
Not all in one device yet
Point slope does not help
Si alone may not make it
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
15
Further Optimization of Tunnel FETs
Parameter Means of Improvement
l Electrostatics: GAA geometry,
Materials (high-k) & abrupt junction,
Small body thickness.
EG Source: SiGe or InAs, III-V
heterostructures, (strain), CNT
m* Small effective tunnel mass, SiGe,
III-V, CNT
Si In(Ga)As
D S G
Si Ge
D S G
P-TFET
N-TFET
Target:
• S < 60 mV/dec over many decades
• High Ion (~100 m A/mm) and low Ioff
• Low V (<0.5 V) ( )
+ DF - =
G
G WKB
tunneling on E qh
E m T I
3
2 4 exp ~
2 / 3 * l
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
16
InAs Source on Silicon Tunnel FET
Advantages:
III-V source: small bandgap high currents
A. Verhulst et al. IEEE EDL, 29,
1398, 2008
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
17
InAs Source on Silicon Tunnel FET
Advantages:
III-V source: small bandgap high currents
Intrinsic Si channel: best dielectric interface
(less Dit than III-V)
Si drain: established Si platform
Grown wires:
– on doped substrates enable formation
of tunnel junctions
– allow for strain accommodation and
material combinations
– provide gate-all-around architecture
Targeted TFET structure
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
18
InAs Source on Silicon Tunnel FET
Advantages:
III-V source: small bandgap high currents
Intrinsic Si channel: best dielectric interface
(less Dit than III-V)
Si drain: established Si platform
Grown wires:
– on doped substrates enable formation
of tunnel junctions
– allow for strain accommodation and
material combinations
– provide gate-all-around architecture
Challenges:
Integration of InAs on Si with defect-free interface
(Lattice mismatch InAs/Si 11%)
Appropriate doping levels in source, channel, and drain
High-k metal gate stack with low Dit
Processing of vertical devices with scaled dimensions
Targeted TFET structure
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
19
InAs Nanowire Growth (MOCVD) on Si <111>
InAs nanowires epitaxially grown on Si <111>
NW structure essential for material composition,
because of 11% lattice mismatch
Patterned SiO2 mask used for selective NW growth
Precursors: Trimethylindium [TMIn]
Tertiarybutylarsine [TBA]
Temperature: 520°C
n-type behavior (as grown ~5·1017cm-3)
200 nm diameter InAs wires with
hexagonal cross-section.
n-type InAs NW on p-type Si wafer
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
20
Diode Processing
(1) Deposition of spacer polymer
(2) Back-etch of spacer polymer(3) Deposition of photo- resist
(4) Exposure and development of photo-resist
(5) Evaporation of Ti/Al (6) Lift-off of photo-resist
InAs-Si pn-junction forms between NW and bulk wafer
Contact pad
Nanowire
InAs/Si pn-junction forms between NW and bulk wafer
Diode characteristics to elucidate band line-up & tunneling mechanism
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
21
InAs-Si Heterojunction Tunnel Diodes
Effect of Silicon substrate doping:1×1016 cm-3, 1×1019 cm-3, 4×1019 cm-3, 1×1020 cm-3
InAs wire diameter d ~ 145 nm
Small Eg,eff = 220meV
Esaki Diode:
Forward direction
- NDR for high substrate doping
- PVCR up to 2.44
High quality pn-heterojunction
- Ipk up to ~ 10 kA/cm2
Reverse direction
- JD up to 250 kA/cm2 @ 0.5V
Björk et al. APL 2010
Forward Reverse
p-Si concentration
NDR signature of high quality heterojunction
High tunnel current densities achieved, similar to all III-V junctions
Low defect junctions and high currents are crucial for Tunnel FETs
Eg,eff = 220 meV
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
22
InAs/Si Interface Characterization – HRTEM
FIB preparation &
HR TEM analysis
InAs is ZB with stacking
faults
Lattice mismatch is 11.6 %
Abrupt interface
Tilted view shows in-plane
dislocation network at
InAs/Si interface with 36Å
periodicity
InAs
Si
Tilted along <111>
Geometric phase analysis
Courtesy of:
K. Reuter and F. Ross, IBM YKT
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
23
Tunneling at the InAs/Si Interface
InAs/Si interface quality is critical for tunneling
Certain variability in PVCR observed from device to device
Low temperature transport measurements of Si / InAs tunnel diodes performed to
– get insight into tunnel process
– investigate the interface quality
Temperature dependence:
– Excess current decreases with lower Temp.
– Higher PVCR at 4K due
to lower excess current
– Rs changes
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
24
InAs/Si Interface Characterization
Low-T Electrical Characterization
Peaks in d2I/dV2 at low voltage indicate
trap-assisted tunneling via dislocations and
point defects at the interface
Peaks disappear for biases > ~100 mV
reverse bias
– One-sided junction
– With increasing reverse bias the
generation rate shifts into InAs,
away from the interface.
Traps exist at interface but may be less
critical as tunneling occurs in InAs
reverse forward
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
25
InAs-Si Nanowire Fabrication for Tunnel FETs
Key fabrication steps:
Channel:
Si epiwafer
MBE epilayer of i -Si on p+ Si
thickness 150 nm
Source:
InAs nanowire growth in mask
openings by MOCVD at 520 °C.
Diameter = 100 to 150 nm,
Height = 600 to 700 nm
Drain:
InAs NW acts as self-aligned
mask for Si channel and drain
during DRIE etching
p
i
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
26
InAs-Si Nanowire TFET Fabrication
Final Planarization step
Source contact fabrication
Structural analysis by cross sectioning (FIB/SEM/TEM)
400 nm
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
27
Transfer and Output Curves of InAs-Si Nanowire TFET
Transfer characteristics of single devices
with varying VDS and of several devices
with normalized current density.
Ion < 0.4 mA/mm at 1VDS
SS > 220 mV/dec
Significant shift in the transfer curves
observed
Output curves of an InAs-Si TFET showing
superlinear behaviour in ID vs. VDS
Indication of an additional series resistance
(barrier)
Electrical results: Transfer Characteristics Several Devices
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
28
Temperature-Dependent Measurements
Temperature-dependent transfer
characteristics shows strong variation of
drain current
SS increases with T
Arrhenius plot of ID. The slope corresponds
to an activation energy of 80 meV
Results suggests the presence of non-ideal
(source) contacts
-1.5 -1.0 -0.5 0.0 0.5 1.0
10-13
10-12
10-11
10-10
10-9
10-8
10-7
VDS
= 1V
T= 300K
T= 150 K
I D [
A]
VGS
[V]
First InAs-Si TFET fabricated and measured
Non ohmic contacts are likely limiting device performance
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
10-10
10-9
10-8
I D a
t V
GS=
-1V
[A
]1/Temperature [1/K]
EA
~0.080eV
VDS= 0.5 V
VDS= 1 V
EA= 80 meV
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
29
Improved Top Contact
Improved contact increases current: Ion ~ 2 μA/μm (VGS=VDS=1V)
Ion less T-dependent indication of reduced potential barrier
Minimum SS (2 dec. of current) ~100mV/dec. compared to 220mV/dec. before.
InAs-Si Tunnel FET demonstrated
Optimization on-going (doping, oxide quality, wire diameter, …)
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
30
Summary
All-Si Nanowire Tunnel FETs with decent average S of 120 mV/dec demonstrated.
High quality Si Esaki diodes based on nanowires demonstrated.
InAs/Si Esaki tunnel diodes demonstrated.
– NDR with PVCR of 2.44 indicates abrupt, high quality heterojunction
– Tunnel current of 250 mA/cm2 at 0.5 V reverse direction achieved
– Dislocations at heterointerface present but seem not to influence current at high
reverse bias one-sided tunnel junction
1st vertical InAs/Si Nanowire Tunnel FET demonstrated
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
31
Acknowledgements
Nanoscale Electronics Team:
B. Gotsmann, P. Das Kanungo, F. Menges, P. Mensch, P. Nirmalraj, A. Rey,
F. Schwarz, G. Signorello, M. Tschudy
ZRL S&T Department:
M. Richter, W. Riess, D. Webb, D. Widmer, U. Drechsler, …
TEM: K. Reuter, F. Ross, L. Gignac, C. Breslin
Teams at IBM Watson Research Center: W. Haensch et al.
Andreas Schenk, ETHZ
EU Funding: FP6 NODE, FP7 Steeper
Thank you for your attention
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
32
Vertical SiNW TFET
Vertical, etched Si NW TFET
Minimum SS 30 mV/dec
Ca 50 mV/dec over 3 order of magnitude
Wire diameter critical for small SS
Ion/Ioff 105
Low-T dopant-segregated silicidation to achieve high
and abrupt doping
Gandhi et al. IEEE EDL online, 2011
Diameter-dependence of SS
Smaller diameter:
better electrostatics
More efficient dopant segregation
higher doping and more abrupt
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
33
Undoped InAs on p-type Si (1×1016 cm-3)
NW diameter ~150 nm
Ideality factor: 2-2.4
Temperature Dependence:
Reverse direction
• Shockley-Read-Hall generation at low voltages
• Impact ionization at higher voltages
Goal: Identify the band-lineup in the
InAs/Si heterodiode
InAs-Si Heterojunction Diodes – InAs on Low Doped Si
Reverse Direction
© 2011 IBM Corporation
2nd Berkeley Symposium on Energy Efficient Electronic Systems | Heike Riel – [email protected]
34
Temperature Dependence:
Forward direction
• Barrier height ΦB derived from Arrhenius plot
• Bias-dependent barrier height ΦB (V) observed
Zero bias barrier ΦB ~ 275 meV
• Valence band offset of ΔEV ~130 meV
(assuming InAs doping is 5×1017 cm-3)
Effective bandgap: Eg,eff = 220 meV
InAs-Si Heterojunction Diodes – InAs on Low Doped Si
Forward Bias
M
. B
joe
rk e
t a
l. A
PL
20
10
Small effective bandgap High tunnelling probability
Top Related