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Microwave
Ofce
For Modules
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Layout
CircuitDesign
SystemDesign
Simulation
& Analysis
LVS/DRC
Extraction
Speed and innovation. Work harder aster. These are the goals that AWR
adheres to or our agship Microwave Ofce design environment. We are RF/
microwave engineers ourselves, and we know all too well the demanding RF
module design requirements you must meet, and the intense pressure you
are under to deliver solutions that work at requency and deliver the innovative
eatures your customers demand. And not only do you have to produce complex
designs that meet specs, you also have to deliver them ast beore design
windows shrink or competitors beat you to it. Outside-the-box thinking is required
i you want your modules to perorm better than the competition. Miss the
design window in time or eatures--and youre let out o the game.
For you and or AWR, successul module design is about orchestrating a variety
o independently-designed circuits to work together harmoniously where the whole
is greater than the sum o the parts. Each individual circuit may be a masterpiece
in its own right, but i improperly used or designed in isolation, is likely to result
in a suboptimal module. Successul module design requires co-design -- co-design
o at least one monolithic microwave integrated circuit (MMIC) die, sometimes
several, and in multiple process technologies, in a package o yet another process
technology, and, fnally, perhaps even onto the printed circuit board (PCB).
THE AWR MODULE DESIGN FLOW EDGE
The Microwave Ofce design environment delivers the industrys most innovative
tools or RF module design, with the most intuitive user interace, and the most
complete integration with third party point tools and technologiesenabling
engineers to solve tough, modern design problems and maintain their competitive
advantage against ferce competition. The AWR user experience is not just a
collection o tools and technology but rather an integrated, cohesive design ow
engineered rom Day One to maximize productivity and minimize the need or time
investment, manual intervention, and training.
Schematic and layout - not schematic or layout Many tool vendors believe
that i you can just electrically simulate the whole design then you are on your
way to a successul module design. Not necessarily so. The issue with this train
o thought is that as increasingly challenging RF module perormance criteriapush the boundaries o electrical design, layout dependencies increase, and,
consequently, competitive module design now requires more than simply an all-out
electrical simulation. Under these circumstances, co-design, or, more accurately,
multi-domain concurrency, means that simulation, layout, and electromagnetic
(EM) must work in unison, as well as integrating with system simulation, design
rule check (DRC), and layout-vs.-schematic (LVS).
Co-design o the Module Modules are frst and oremost defned by the space
they are allotted, and todays handset power amplifer/ront-end modules (PA/
FEMs) are arguably the area where the boundaries are being
Advancing the State
o High-Frequency
Design Automation
Much more than a design tool, Microwave
Ofce software is a complete design ow
offering all of the essential technologies:
linear and nonlinear circuit simulators, EM
analysis tools, layout-vs.-schematic checks,
statistical design capabilities, and parametric
cell libraries with built-in DRC.
The combination of the integrated Microwave Ofce
environment and accurate Cree device models enabled
me to achieve a design in a matter of days that
simulated to within a few percent of my measured
output power and achieved greater than 85% PAE.
Michael Boers, Macquarie University
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pushed more than anyplace else when it comes to minimal space. Mm-wave modules
are challenging in their own right because o the need to appropriately size and
separate eatures. While the MMICs in the module may be designed in a very top-
down, schematic-driven methodology, the module interconnects are so constrained
or space and the electrical perormance criteria so demanding that layout-driven
simulation seems a natural approach. Designers need to do much more than just
update schematic parameter values rom the layout or microstrips--they need to
use powerul, layout-based model generation and ast EM simulation, ollowed by
accurate EM analysis or post-layout verifcation. And trade-os among MMIC or RFIC
unctionality, matching, and perormance require a similar layout-based approach to
ft within orm-actor and manuacturing constraints. With so many circuits comingtogether, and the necessity or it all to be done in the schematic, layout, EM, and
verifcation stages, only AWRs Microwave Ofce sotware with its trend-setting
ease-o-use and real-time tuning and optimization, schematic-driven EM, and access
to all the industry-leading technology you need can take you through IC design and
module integration, and into manuacturing quickly and efciently.
USER-FLEXIBLE DESIGN ENVIRONMENT
While other sotware tools hold customers captive to their way o doing things,
AWR has built Microwave Ofce rom the ground up based on the idea o a exible
architecture that encourages additional and alternative solutions that empower
successul module design. Your ow demands the exibility to continue using, or to addthird-party point tools, and to integrate to adjacent ows like test or enterprise PCB.
All o these requirements are possible with the Microwave Ofce module design ow.
Multi-technology PDKs - At the core o the Microwave Ofce sotware is a Unifed
Data Model (UDM) that is neither an IC nor PCB database, but instead takes
on the orm needed based on the process design kits
(PDKs) loaded into it. I just a gallium arsenide (GaAs)
heterojunction biopolar transistor (HBT) PDK is loaded,
than the UDM is a complete design environment across
all the design ow domainsschematic, simulation,
layout, EM and extraction, DRC and LVSor MMICdesign. I a our-layer laminate PDK is added to the HBT
PDK, then the two can be co-designed through simulation
and layout, with complete representations available at
all times. Multiple IC PDKs, including silicon germanium
(SiGe) or silicon complimentary metal oxide semiconductor
(Si CMOS), can be added along with other MMIC
technologies and surace mount device (SMD) passives
and packaging to achieve total circuit and system,
schematic and layout co-design.
Microwave Ofce, with APLAC simulation
technology, is renowned for its speed and
convergence, allowing module designers to
power through the most complex simulations.
Microwave Ofce software simultaneously loads all necessary PDKs to
represent various technologies used in designing this power amplier.
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USA
Corporate Headquarters
AWR Corporation
1960 E. Grand Avenue, Suite 430
El Segundo, CA 90245
+1 310 726 3000
+1 310 726 3005 (ax)
Japan
AWR Japan KK
Level 5, 711 Building
7-11-18 Nishi-Shinjuku, Shinjuku-ku
Tokyo 160-0023 Japan
+81 3 5937 4803
Korea
AWR Korea Co. Ltd.
B-1412, Intellige-II, 24 Jeongja-dong,
Bundang-gu, Seongnam-si,
Gyeonggi-do, South Korea, 463-811
+82.31.603.7772~3
UK
AWR UK
2 Hunting Gate
Hitchin, Herts
SG4 0TJ, UK
+44 (0) 1462 428 428
Finland
AWR APLAC
Lars Sonckin kaari 16
FI-02600 Espoo, Finland
+358 10 834 5900
France
AWR France
140 Avenue Champs Elysees
75008 Paris, France
+33 1 70 36 19 63
www.awrcorp.comwww.awr.tv
Copyright 2010 AWR Corporation. All rights reserved. AWR and the AWR logo, Microwave Ofce andAPLAC are registered trademarks and Visual System Simulator, AXIEM, ACE, AWR Design Environment,EXTRACT, Unifed Data Model, and Intelligent Net are trademarks o AWR Corporation.All others are the property o their respective holders.
A HOST OF INNOVATIVE TECHNOLOGIES
APLAC harmonic balance and transient The incomparable APLAC circuit
simulator combines linear and nonlinear requency-domain simulation with
time-domain transient. Renowned or its speed and convergence on the
toughest problems, APLAC simulates in minutes where others take hours, i,
in act, they converge at all. Large problems, like ull-up module verifcation,
are no problem or APLAC.
The EXTRACT fow The EXTRACT ow within AWRs Microwave Ofce design
environment makes lie so much easier by allowing EM and circuit extraction
to be controlled by the schematic; there is no need to go to the layout and
launch EM as a separate step rom the schematic and the resulting highport-count S-parameter fle does not need to magically and manually
be knit back into the schematic. Consequently, there are no errors
in integrating EM back into the circuit and system simulation.
With the EXTRACT ow, EM is a seamless and integral part o
tuning, optimization, and statistical analysis, ultimately saving
you hours or days o time.
ACE circuit extraction ACE, AWRs unique automated
circuit extraction technology, is another breakthrough AWR
technology that essentially creates netlists o distributed
models, many containing optimized EM solvers, rom
arbitrary interconnects. Using AWRs interconnect (Intelligent
Net) routing technology combined with microstrip lines,
discontinuities, and even printed inductors. Diagnosing critical
couplings is a breeze with ACE. By creating parameterized netlists
using distributed models, ACE powers through your layout to create the
same models you would have created in the schematic, but 10,000x aster
than any alternative approach.
AXIEM 3D planar EM technology The revolutionary AXIEM product is the
industrys frst solver to enable to enable user-discretion speed and accuracy
trade-os o the design rom DC up through millimeter wave. AXIEMs exibility
as both an in-situ EM solver or modeling as well as post-layout electrical
verifcation means that theres no need to change any setup inormation other
than speciying accuracy and speed as the design progresses rom concept
to fnal layout. AXIEM reduces cycle time with and saves inrastructure costs
because it is the only planar 3D EM solver needed.
BR-MWO-MODULE-2010.5.10
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