ECE2030 Introduction to Computer Engineering Lecture 1
1Fundamental of MOS Theory and CMOS Transistors
Hello every one lets learn VLSI basic building block
Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurBasic SwitchA path exists when the Switch Control is closedIf (Open) OUTPUT = unknown ; Switch is open (OFF)Else OUTPUT = INPUT ; Switch is closed (ON)
INPUTOUTPUTSwitch Control
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurSemiconductors
N+N+N-
AlSiO2Si X Y
Conductivity of Si is proportional to No. of free carriers(electrons or holes)
No. of free carriers is programmable:
a. At fabrication time (N- means small excess of electrons N+ means large excess of electrons)b. At run time (heat/light/static charge/injection).edge view
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurMOS Transistor
N+N+P-
AlSiO2Si X gate Y
1. The gate (metal) / SiO2 (oxide) / Si (semiconductor)sandwich makes a capacitor.3. Result: a switch! 0V on gate -> OFF; +5V on gate -> ON+ + + + + + + + + + + + +
- - - - - - - - - - - - -2. Charging the capacitor brings carriers to the surface of theoxide -- the carriers on the Si side make a high-conductivitychannel.
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurThe Analogy of A Transistor
Cross SectionAn N-Channel Metal-Oxide Semiconductor Field Effect Transistor (MOSFET)
INPUTOUTPUTSwitch Control (Gate)
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurNMOS Transistors4 electrical terminalsSourceDrainGateSubstrateConnected to Gnd
Source and drain are only different in their interpretationTerminal with lower voltage is the source (by convention)
Simplified symbol omits the substrateDrain Source
GateSubstrate (Body)V D V S
V G
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurPMOS TransistorsSame 4 electrical terminalsSourceDrainGateSubstrateConnected to VDD
Again, source and drain are only different in their interpretationTerminal with higher voltage is the source (by convention)
Simplified symbol omits the substrateGate
V
DDDrain SourceSubstrate (Body)V G V D V S
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurPhysical Structure of MOS FETS
NMOSPMOS
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurTransistor CharacteristicsCut-off RegionVgs Vt 0No current (Ids) between drain and sourceLinear (or Ohmic) Region0 < Vds < Vgs VtIds is a function of Vgs and VdsIds = *[(Vgs-Vt)*Vds Vds*Vds/2]Saturation Region0 < Vgs Vt < VdsIds is independent of VdsIds = (/2)*(Vgs-Vt)2 = process factor * (W/L)Vt : Threshold voltage, a function of materials, doping, insulator thickness, etc.
Gate
DrainSource
IdsVds
VgsN-type MOS Transistor
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurTransistor Characteristics
#Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur
MOS CapacitorGate and body form MOS capacitorOperating modesAccumulationDepletionInversion
#Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur11
3: CMOS Transistor Theory12Terminal VoltagesMode of operation depends on Vg, Vd, VsVgs = Vg VsVgd = Vg VdVds = Vd Vs = Vgs - VgdSource and drain are symmetric diffusion terminalsBy convention, source is terminal at lower voltageHence Vds 0nMOS body is grounded. First assume source is 0 too.Three regions of operationCutoffLinearSaturation
#Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur12
nMOS CutoffNo channelIds 0
#Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur13
nMOS LinearChannel formsCurrent flows from d to s e- from s to dIds increases with VdsSimilar to linear resistor
#Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur14
Switches in Series
INPUTOUTPUTS1S2Truth TableS1S2PATH?OFFOFFOFFONONOFFONON
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurSwitches in Series
INPUTOUTPUTS1S2Truth Table (OFF/ON=0/1)S1S2PATH?OFFOFFNOOFFONNOONOFFNOONONYES
What Function ??
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurSwitches in Series
INPUTOUTPUTS1S2Truth Table (OFF/ON=0/1)S1S2PATH?000
Function = ??
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurSwitches in Series
INPUTOUTPUTS1S2Truth Table (OFF/ON=0/1)S1S2PATH?000010
Function = ??
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurSwitches in Series
INPUTOUTPUTS1S2Truth Table (OFF/ON=0/1)S1S2PATH?000010100
Function = ??
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurSwitches in Series
INPUTOUTPUTS1S2Truth Table (OFF/ON=0/1)S1S2PATH?000010100111
Function = Logic AND
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurSwitches in Parallel
INPUTOUTPUTS1Truth Table S1S2PATH?OFFOFFNOOFF ONYESONOFFYESONONYES
S2
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurSwitches in Parallel
INPUTOUTPUTS1Truth Table S1S2PATH?000
Function =??
S2
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurSwitches in Parallel
INPUTOUTPUTS1Truth Table S1S2PATH?000011
Function =??
S2
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurSwitches in Parallel
INPUTOUTPUTS1Truth Table S1S2PATH?000011101
Function =??
S2
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurSwitches in Parallel
INPUTOUTPUTS1Truth Table S1S2PATH?000011101111
Function = Logic OR
S2
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurCMOS TransistorComplementary MOSP-channel MOS (pMOS)N-channel MOS (nMOS)pMOSP-type source and drain diffusionsN substrateMobility by holesnMOSN-type source and drain diffusionsP substrateMobility by electrons
Gate
DrainSource
Gate
SourceDrain
pMOSnMOS
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurPass Transistor using NMOSAssume capacitor (CL) is initially dischargedGate=1, Vin=1CL begins to conduct and charges toward 1 (Vdd) and stops at (Vdd-Vt)Signal is degradedGate=Vdd
Vin=VddVoutGround
Load Capacitor
Vgs
IGate=Vdd
Vin=0Vout=VddGround
Load Capacitor
Vgs
I
Gate=1, Vin=0CL begins to discharge toward 0
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurVoltage Levels
The binary values 0 and 1 can be represented as levels of current or of voltage voltage is most common
Positive logic system associates1 with high and 0 with low
Max voltage is VDD (or VCC)5V for TTLMuch smaller (1.0 V) for ASICs
Min voltage is VSS (or Gnd)Typically 0V
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurLogic RangesTypically V0,max = 0.4VDD and V1,min = 0.6VDD
5 V
3 V
2 V
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurTransmission Degradation using Pass Transistor
Vdd - VtVddVdd (1)Vdd - 2VtVddVdd
VddVout = Vdd- N*VtStill 1??
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurCMOS Signal Transfer PropertyGatePath0Closed1Open
Gate
DrainSource
Gate
SourceDrain
GatePath0Open1Closed
pMOSnMOS Transmits 1 well Transmits 0 poorly Transmits 0 well Transmits 1 poorly
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurCMOS Transmission GateTransmit signal from INPUT to OUTPUT when Gate is closedGate (complementary of Gate)SourceDrain
GateINPUTOUTPUT
GatepMOSnMOSOUTPUT0OFFOFFZ1ONONINPUT
Z : High-Impedance State, consider the terminal is floating
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurHigh ImpedanceWhen a path existsImpedance is low to allow ample flow of current
When no pathImpedance is high allowing almost no current flow between two terminalsGate=1
DrainSource
> 100M ClosedGate=0
DrainSource
Open
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurTransmission Gates
Gate = 100
Gate = 0
Transmit Logic 0
Gate = 111
Gate = 0
Transmit Logic 1
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurTransmission Gate Symbol
Gate
GateINPUTOUTPUT
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurCMOS InverterConnect the following terminals of a PMOS and an NMOSGatesDrains
VinVout
VddGnd
VoutVinVin
Vin = HIGHVout = LOW (Gnd)ONOFF
VddGnd
VoutVinVin
Vin = LOWVout = HIGH (Vdd)ONOFFVdd
PMOS
Ground
NMOS
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurCMOS Voltage Transfer Characteristics
VddGnd
VinVoutPMOSNMOSOFF: V_GateToSource < V_ThresholdLINEAR (or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSourceNote that in the CMOS Inverter V_GateToSource = V_in
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurPull-Up and Pull-Down NetworkCMOS network consists of a Pull-UP Network (PUN) and a Pull-Down Network (PDN)PUN consists of a set of PMOS transistorsPDN consists of a set of NMOS transistorsPUN and PDN implementations are complimentary to each otherPMOS NOMSSeries topology Parallel topology
.
I0I1In-1OUPTUTVdd
PUN
Gnd
PDN
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurPUN/PDN of a CMOS InverterAB011Z
AB0Z10
AB0110
Pull-UpNetworkPull-DownNetworkCombinedCMOSNetworkVdd
A
Gnd
B
CMOS Inverter
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurGate Symbol of a CMOS InverterVdd
A
Gnd
B
CMOS Inverter
ABB =
#Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur
PUN/PDN of a NAND GateABC00101110111Z
ABC00Z01Z10Z110
Pull-UpNetworkPull-DownNetworkVdd
ABABC
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurPUN/PDN of a NAND GateABC00101110111Z
ABC00Z01Z10Z110
ABC001011101110
Pull-UpNetworkPull-DownNetworkCombinedCMOSNetworkVdd
ABABC
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurNAND Gate SymbolABC001011101110
Vdd
ABABC
ABCTruth Table
#Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpur
PUN/PDN of a NOR GateABC00101Z10Z11Z
ABC00Z010100110
Pull-UpNetworkPull-DownNetworkVdd
AC
B
AB
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurPUN/PDN of a NOR GateABC00101Z10Z11Z
ABC00Z010100110
ABC001010100110
Pull-UpNetworkPull-DownNetworkCombinedCMOSNetwork
AC
B
AB
Vdd
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurNOR Gate SymbolABC001010100110
ABCTruth Table
AC
B
AB
Vdd
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurHow about an AND gateVdd
ABA
VddGnd
C
NANDInverterBC = A B
ABC
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurAn OR Gate
A
B
AB
Vdd
VddGnd
C
InverterNOR
ABC
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurWhats the Function of the following CMOS Network?
Vdd
CABC00Z01110111Z
ABC00001Z10Z110
ABC000011101110
Pull-UpNetworkPull-DownNetworkCombinedCMOSNetworkFunction = XOR
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurYet Another XOR CMOS Network
Vdd
CABC00Z01110111Z
ABC00001Z10Z110
ABC000011101110
Pull-UpNetworkPull-DownNetworkCombinedCMOSNetworkFunction = XOR
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExclusive-OR (XOR) Gate
Vdd
CABC000011101110
ABCTruth Table
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurHow about XNOR GateABC001010100111
ABCTruth Table
How do we draw thecorresponding CMOS networkgiven a Boolean equation?
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurHow about XNOR GateABC001010100111
ABCTruth Table
Vdd
C
Vdd
XORInverter
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurA Systematic ApproachEach variable in the given Boolean eqn corresponds to a PMOS transistor in PUN and an NMOS transistor in PDNDraw PUN using PMOS based on the Boolean eqnAND operation drawn in seriesOR operation drawn in parallelInvert each variable of the Boolean eqn as the gate input for each PMOS in the PUNDraw PDN using NMOS in complementary formParallel (PUN) to series (PDN)Series (PUN) to parallel (PDN)Label with the same inputs of PUNLabel the output
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExample 1
In series
In parallel
Vdd
(1) Draw the Pull-Up Network
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExample 1
In series
In parallel
Vdd
(2) Assign the complemented inputACB
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExample 1
In series
In parallel
Vdd
(3) Draw the Pull-Down Network in the complementary formACB
A
C
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExample 1
In series
In parallel
Vdd
(3) Draw the Pull-Down Network in the complementary formACB
A
C
B
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExample 1
In series
In parallel
Vdd
Label the output FACB
A
C
B
F
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExample 1
In series
In parallel
Vdd
ACB
A
C
B
FABCF00000010010101111001101011011111
Truth Table
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurAn Alternative for XNOR GateABC001010100111
ABCTruth Table
Vdd
C
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExample 3
Start from the innermost term
A
B
D
A
C
AD
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExample 3
Start from the innermost term
A
B
D
A
C
AD
A
C
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExample 3
Start from the innermost term
A
B
D
A
C
AD
A
C
B
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExample 3
Start from the innermost term
A
B
D
A
C
AD
A
C
B
Vdd
F
Pull-Up NetworkPull-DownNetwork
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurExample 4
Start from the innermost term
A
B
D
A
C
AD
A
C
B
Vdd
F
E
D
E
D
Pull-DownNetwork
Pull-UpNetwork
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurAnother Example
How ??
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurPerformance 1: Gate Delay
X (Input)Y (Output)
Delay proportional to R * C
R (on resistance of the driver)C (gate capacitance of the receiver)XY
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurMinimum unit of delay:tau = R * C
N+N+P
AlSiO2Si X gate Y
TopviewEdgeview
LW
R proportionalto L/W.(typical: 10Kohms)
C proportionalto W * L(typical: 10fF)L & W quantized to multiples of the minimum line width, currently 0.13um
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurGate DelayMinimum delay (tau) assumes minimum-size transistors
Additional delay arises fromfanoutreal-world outputs (pins ~1pF +)long wires...
Can increase driving transistor width (W) to reduce delay.note exponential chain.
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurPerformance 2: Wire Delay
X (Input)Y (Output)
Delay proportional to R * C
R (on resistance PLUS wire resistance)C (gate capacitance PLUS wire capacitance)XY
#Prof.Kunal N Dekate, G H Raisoni college of Engineering NagpurThank You
#Prof.Kunal N Dekate, G H Raisoni college of Engineering Nagpursilicon dioxide insulator
p-type body
+
-
polysilicon gate
Vg < 0
(a)
depletion region
(b)
+
-
0 < Vg < Vt
depletion region
(c)
+
-
inversion region
Vg > Vt
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