Module-3 ( MOS designs,Stick Diagrams,Designrules ) Sandeep
Radhakrishnan VJEC,Chemperi
Slide 2
Before we start. In this module we are going to study NMOS and
CMOS Design Styles Both combinational and sequential (We had done
many examples in our class.So Please go on that.Here I am giving
the design of basic gates only) Stick Diagrams Layouts Lamda and
micron design rules
Slide 3
Transistors as Switches We can view MOS transistors as
electrically controlled switches Voltage at gate controls path from
source to drain
Slide 4
CMOS Inverter AY 0 1
Slide 5
AY 0 10
Slide 6
AY 01 10
Slide 7
CMOS NAND Gate ABY 00 01 10 11
Slide 8
ABY 001 01 10 11
Slide 9
ABY 001 011 10 11
Slide 10
ABY 001 011 101 11
Slide 11
ABY 001 011 101 110
Slide 12
CMOS NOR Gate ABY 001 010 100 110
Slide 13
VLSI design aims to translate circuit concepts onto silicon.
stick diagrams are a means of capturing topography and layer
information using simple diagrams. Stick diagrams convey layer
information through colour codes (or monochrome encoding). Acts as
an interface between symbolic circuit and the actual layout.
Slide 14
Stick diagrams A stick diagram is a cartoon of a layout. Does
show all components/vias (except possibly tub ties), relative
placement. Does not show exact placement, transistor sizes, wire
lengths, wire widths, tub boundaries.
Slide 15
Stick Diagrams Key idea: "Stick figure cartoon" of a layout
Useful for planning layout relative placement of transistors
assignment of signals to layers connections between cells cell
hierarchy
Slide 16
Stick Diagrams (3/3)
Slide 17
Stick Diagrams Notations 17 Metal 1 poly ndiff pdiff Can also
draw in shades of gray/line style. Stick Diagrams Similarly for
contacts, via, tub etc..
Slide 18
Stick Diagrams Some rules Rule 1. When two or more sticks of
the same type cross or touch each other that represents electrical
contact. 18 Stick Diagrams
Slide 19
Stick Diagrams Some rules Rule 2. When two or more sticks of
different type cross or touch each other there is no electrical
contact. ( If electrical contact is needed we have to show the
connection explicitly). 19 Stick Diagrams
Slide 20
Stick Diagrams Some rules Rule 3. When a poly crosses diffusion
it represents a transistor. 20 Note: If a contact is shown then it
is not a transistor. Stick Diagrams
Slide 21
Stick Diagrams Some rules Rule 4. In CMOS a demarcation line is
drawn to avoid touching of p-diff with n-diff. All pMOS must lie on
one side of the line and all nMOS will have to be on the other
side. 21 Stick Diagrams
Slide 22
V out V dd = 5V V in V out V dd = 5V V in pMOS nMOS Stick
diagram -> CMOS transistor circuit In practice, first draw stick
diagram for nMOS section and analyse (pMOS is dual of nMOS
section)
Slide 23
Stick Diagrams 23 Gnd V DD X X X X Gnd Stick Diagrams
Slide 24
Static CMOS NAND gate
Slide 25
Static CMOS NOR gate
Slide 26
Static CMOS Design Example Layout
Slide 27
Draw the stick diagram
Slide 28
Identify the Circuit
Slide 29
Slide 30
CMOS INVERTER
Slide 31
Layout of CMOS NAND
Slide 32
Please practice more examples
Slide 33
Design Rules
Slide 34
Design rules Circuit engineers needs to reduce the size but
process engineers needs a controllable and reproducible fabrication
So we needs design rules to get more yield. Design rules can never
be met exactly at the wafer level because physical nature of
semiconductor causes some variations. Parameter limits that cover
six standard deviation ensure that 99.7 percentage meets the
specification.
Slide 35
Design Rules Interface between the circuit designer and process
engineer Guidelines for constructing process masks Unit dimension:
minimum line width scalable design rules: lambda parameter absolute
dimensions: micron rules Rules constructed to ensure that design
works even when small fab errors (within some tolerance) occur A
complete set includes set of layers intra-layer: relations between
objects in the same layer inter-layer: relations between objects on
different layers
Slide 36
Why Have Design Rules? To be able to tolerate some level of
fabrication errors such as 1.Mask misalignment 2.Dust 3.Process
parameters (e.g., lateral diffusion) 4.Rough surfaces
Slide 37
Based Design Rules Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power) Feature size f = distance between source
and drain Set by minimum width of polysilicon Feature size improves
30% every 3 years or so Normalize for feature size when describing
design rules Express rules in terms of = f/2 E.g. = 0.3 m in 0.6 m
process 0: Introduction Slid e 37
Slide 38
NMOS Design Rules( based) Minimum width of PolySi and diffusion
line 2 Minimum width of Metal line 3 as metal lines run over a more
uneven surface than other conducting layers to ensure their
continuity Metal Diffusion Polysilicon
Slide 39
Design Rules PolySi PolySi space 2 Metal - Metal space 2
Diffusion Diffusion 3 To avoid the possibility of their associated
regions overlapping and conducting current Metal Diffusion
Polysilicon
Slide 40
Design Rules Diffusion PolySi Metal lines can pass over both
diffusion and polySi without electrical effect. Where no separation
is specified, metal lines can overlap or cross Metal Diffusion
Polysilicon
Slide 41
Metal Vs PolySi/Diffusion Metal lines can pass over both
diffusion and polySi without electrical effect It is recommended
practice to leave between a metal edge and a polySi or diffusion
line to which it is not electrically connected Metal
Polysilicon
Slide 42
Depletion Transistor We need depletion implant An implant
surrounding the Transistor by 2 Ensures that no part of the
transistor remains in the enhancement mode A separation of 2 from
the gate of an enhancement transistor avoids affecting the device.
2
Slide 43
Depletion Transistor Implants are separated by 2 to prevent
them from merging 2
Slide 44
Contact Area must be a min. of 2 *2 to ensure adequate contact
area. 2 2 Contact Area
Slide 45
Contact Cut Metal connects to polySi/diffusion by contact cut.
Contact area: 2 2 Metal and polySi or diffusion must overlap this
contact area by so that the two desired conductors encompass the
contact area despite any mis-alignment between conducting layers
and the contact hole 4
Slide 46
Contact Cut Contact cut any gate: 2 apart Why? No contact to
any part of the gate. 4 2
Slide 47
Contact Cut Contact cut contact cut: 2 apart Why? To prevent
holes from merging. 2
Slide 48
Nmos Design rules N+Diffusion Mask Diffusion width 2 Diffusion
spacing 3 Implant Mask Implant gate overlap 1.5 Implant to
enhancement gate spacing 1.5 Buried contact mask Buried contact to
active device 2 (to avoid short circuit) Overlap in diffusion
direction 2 Overlap in poly or field direction 1 Buried contact to
unrelated poly or diffusion spacing 2
Slide 49
Poly Mask Poly width 2 Poly spacing 2 Poly diffusion spacing 1
Poly gate extension beyond diffusion 2 Diffuin to poly edge 2
Contact Mask Contact size 2 x 2 Contact diffusion overlap 1 Contact
poly overlap 1 Contact to contact space 2 Contact to FET channel 2
Contact to metal overlap 1 Metal mask Metal width 3 Metal spacing
3
Slide 50
Rules for CMOS layout To ensure the separation of the PMOS and
NMOS devices, n-well supporting PMOS is 6 away from the active area
of NMOS transistor. Why? Avoids overlap of the associated regions
n-well n+ 6
Slide 51
Rules for CMOS layout 2 2 N-well must completely surround the
PMOS devices active area by 2
Slide 52
Rules for CMOS layout 2 2 The threshold implant mask covers all
n-well and surrounds the n-well by
Slide 53
Rules for CMOS layout 2 2 The p + diffusion mask defines the
areas to receive a p + diffusion. It is coincident with the
threshold mask surrounding the PMOS transistor but excludes the
n-well region to be connected to the supply.
Slide 54
Rules for CMOS layout A p + diffusion is required to effect the
ground connection to the substrate. Thus mask also defines this
substrate region. It surrounds the conducting material of this
contact by 4
Slide 55
Simplified Design Rules Conservative rules to get you started
0: Introduction Slid e 55
Slide 56
Micron rules
Slide 57
Slide 58
Intra-Layer Design Rule Origins Minimum dimensions (e.g.,
widths) of objects on each layer to maintain that object after fab
minimum line width is set by the resolution of the patterning
process (photolithography) Minimum spaces between objects (that are
not related) on the same layer to ensure they will not short after
fab 0.15 0.3 micron
Slide 59
Intra-Layer Design Rules Metal2 4 3
Slide 60
Transistor Layout
Slide 61
Select Layer
Slide 62
Please refer the text for more details about the design rules.
Text:VLSI Technology Author: Sujatha Pandey and Manoj Pandey Page
No.: 5.36 to 5.44