Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Topics
Combinational logic functions. Static complementary logic gate structures.
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Combinational logic expressions
Combinational logic: function value is a combination of function arguments.
A logic gate implements a particular logic function.
Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Gate design
Why designing gates for logic functions is non-trivial:– may not have logic gates in the library for all
logic expressions;– a logic expression may map into gates that
consume a lot of area, delay, or power.
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Boolean algebra terminology
Function:f = a’b + ab’
a is a variable; a and a’ are literals. ab’ is a term. A function is irredundant if no literal can be
removed without changing its truth value.
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Completeness
A set of functions f1, f2, ... is complete iff every Boolean function can be generated by a combination of the functions.
NAND is a complete set; NOR is a complete set; {AND, OR} is not complete.
NOT = NAND with shorted inputs. AND = NAND followed by a NOT. OR = Two inverters followed by a NAND. Transmission gates are not complete. If your set of logic gates is not complete, you can’t design arbitrary
logic.
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Static complementary gates
Complementary: have complementary pullup (p-type) and pulldown (n-type) networks.
Static: do not rely on stored charge. Simple, effective, reliable; hence
ubiquitous.
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Static complementary gate structure
Pullup and pulldown networks:
pullupnetwork
pulldownnetwork
VDD
VSS
outinputs
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Inverter
a out
+
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Inverter layout
(tubs notshown)a out
+
transistors
GND
VDD
a out
tub ties
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
NAND gate
+
ba
out
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
NAND layout
+
ba
out
b
a
out
VDD
GND
tubties
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
NOR gate
+
b
a
out
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
NOR layout
b
a
out
a
b
out
VDD
GND
tub ties
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
AOI/OAI gates
AOI = and/or/invert; OAI = or/and/invert. Implement larger functions. Pullup and pulldown networks are compact:
smaller area, higher speed than NAND/NOR network equivalents.
AOI312: and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert.
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
AOI example
out = [ab+c]’:
symbol pull-up circuit
and
or
invert
pull-down circuit
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Pullup/pulldown network design
Pullup and pulldown networks are duals. To design a CMOS logic circuit for a
combinational expression, first design a pull-down network for it, then compute the dual to get the pull-up network.
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Dual network construction
dum
my
a
b c
dummy
a
b c
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Dual network construction
The pull-up part of a CMOS implementation of f can be obtained by writing a sum-of-product expression for f and likewise the pull-down part can be obtained by writing a sum-of-product expression for f’.
Note: As we discussed in class, it is not always possible to use p-type transistors in the pull-up circuit and/or n-type transistors in the pull-down circuit unless we use inverter gates for negated inputs in certain cases. For example, (A’B + CD) cannot be realized all with p-type transistors unless we use an inverter to generate A’.
Modern VLSI Design 3e: Chapter 3 Copyright 1998, 2002 Prentice Hall PTR
Dual network construction
(A’B + CD)’
GND
vDD
GND
A
C
B
D
A
B
C
D
(A’B + CD)
(A’B + CD)’ = (A +B’)(C’+D’)
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