MC602 2011 1
IC-UNICAMP MC 602
IC/Unicamp2011s2
Prof Mario Crtes
VHDLMquina de Estados (FSM)
MC602 2011 2
IC-UNICAMPTpicos
Mquinas de estados Moore Mealy
Dois templates para implementao em VHDL
MC602 2011 3
IC-UNICAMP
Combinational circuit
Flip-flops
Clock
Q W
Z Combinational
circuit
Forma geral de um circuito sncrono
MC602 2011 4
IC-UNICAMPMquina de Moore
C z 1 =
Reset
B z 0 = A z 0 = w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0
z=1 se w=1 nos dois ltimos ciclos de clockz=0 caso contrrio
MC602 2011 5
IC-UNICAMP
Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
C z 1 =
Reset
B z 0 = A z 0 = w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
Diagrama de Estados
MC602 2011 6
IC-UNICAMP Implementao
Combinationalcircuit
Combinationalcircuit
Clock
y2
z
wy1Y1
Y2
MC602 2011 7
IC-UNICAMPFSM de Moore
USE ieee.std_logic_1164.all;
ENTITY simple ISPORT (Clock, Resetn, w : IN STD_LOGIC;
z : OUT STD_LOGIC );END simple;
ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C); -- Tipo Enumerado para
-- definir os EstadosSIGNAL y : State_type;
BEGINPROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THEN -- A o estado inicialy
MC602 2011 8
IC-UNICAMP
FSM de MooreCASE y IS
WHEN A =>IF w = '0
THEN y
MC602 2011 9
IC-UNICAMP FSM de Moore - Simulao
C z 1 =
Reset
B z 0 = A z 0 = w 0 =
w 1 =
w 1 =
w 0 = w 0 = w 1 =
MC602 2011 10
IC-UNICAMP
FSM de MooreCodificao Alternativa (2 processos)
USE ieee.std_logic_1164.all;
ENTITY simple ISPORT (Clock, Resetn, w : IN STD_LOGIC;
z : OUT STD_LOGIC );END simple;
ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C);
SIGNAL y_present, y_next : State_type;
C z 1 =
Reset
B z 0 = A z 0 = w 0 =
w 1 =
w 1 =
w 0 = w 0 = w 1 =
MC602 2011 11
IC-UNICAMP
FSM de MooreCodificao Alternativa (2 processos)
BEGINPROCESS ( w, y_present )BEGIN
CASE y_present ISWHEN A =>
IF w = '0' THENy_next
MC602 2011 12
IC-UNICAMPFSM de Moore - Codificao Alternativa
WHEN C =>IF w = '0' THEN
y_next
MC602 2011 13
IC-UNICAMPResumo alternativas prx estado: Moore
PROCESS ( Resetn, Clock )BEGIN
IF Resetny
MC602 2011 14
IC-UNICAMP
FSM - Especificando a Atribuio de Estados
ARCHITECTURE Behavior OF simple ISTYPE State_TYPE IS (A, B, C);ATTRIBUTE ENUM_ENCODING : STRING;ATTRIBUTE ENUM_ENCODING OF State_type: TYPE IS "00 01 11";
SIGNAL y_present, y_next : State_type;BEGIN
cont ...
Obs: Atributo Enum_Encoding especfico da ferramenta Quartus. Estasoluo pode no funcionar em outras ferramentas CAD
MC602 2011 15
IC-UNICAMP
LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY simple IS
PORT ( Clock, Resetn, w : IN STD_LOGIC;z : OUT STD_LOGIC );
END simple;ARCHITECTURE Behavior OF simple IS
SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0);CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
BEGINPROCESS ( w, y_present )BEGIN
CASE y_present ISWHEN A =>
IF w = '0' THEN y_next
MC602 2011 16
IC-UNICAMP
WHEN B =>IF w = '0' THEN y_next
MC602 2011 17
IC-UNICAMP
A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
Reset
w 1 = z 0 =
Mquina de Mealy
MC602 2011 18
IC-UNICAMPFSM de Mealy
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY mealy ISPORT (Clock, Resetn, w : IN STD_LOGIC;
z : OUT STD_LOGIC );
END mealy;
cont
MC602 2011 19
IC-UNICAMPFSM de Mealy
ARCHITECTURE Behavior OF mealy ISTYPE State_type IS (A, B);SIGNAL y : State_type;
BEGINPROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THEN y
MC602 2011 20
IC-UNICAMPFSM de Mealy
PROCESS ( y, w )BEGIN
CASE y ISWHEN A =>
z
z