Leveraging Distribution
The Actel Sales Process
3 - PLAN3 - PLAN
2 - QUALIFY2 - QUALIFY
1 - PROSPECT1 - PROSPECT
4 - WIN4 - WIN
5 - LEVERAGE5 - LEVERAGE
sales leads
Compile a listof possible users.
Qualify prospectsto find best potentials.
Plan a sales strategy to convince decision makers.
Execute sales strategy to win the business. Leverage the win to
exploit other opportunities.S
S
1. Prospect
Objective: Find all potential Actel users. Look for prospects
Existing users within your customer base
Xilinx and Altera users
Programmable logic users
Standard logic users
Gate array users
Objective: Find all potential Actel users. Develop opening lines Create list of prospects Contact prospects & setup visits
1. Prospect
General Positioning High performance FPGAs at
high capacity Antifuse is a production
technology Best delay predictability and
design flexibility
1. Prospect
General Positioning (cont.) Actel has products for customers’
needs today and planning for future needs
Design with Actel is easy!
1. Prospect
Market Segments of Best Prospects Telecom: PBX switches,
networking (LAN, FDDI, token ring) Computer peripherals: graphics,
tape backup, multimedia, accel cards
Instrumentation: scopes, analyzers
1. Prospect
Market Segments of Best Prospects Medical: imaging systems,
diagnostics, analyzers Industrial Equipment: control and
measurement systems Military: Actel is the only high
density military FPGA in town!
1. Prospect
Breakout #1
Break into regional groups of 5-6 people
Brainstorm a list of potential prospects in your region (at least 4 per person)
Come up with an effective opening line you can use when calling your prospects (pick best one)
Objective: Determine whichprospects are most
likelyto become design wins.
Determine if there is fit between customer needs & Actel products
2. Qualify
Ask key qualifying questions during visit Active & new projects – design windows
Who are decision makers
Major customer needs (speed, cost, I/Os, gates)
Submit design win registrations to Actel
2. Qualify
End Product Profiles: Time to market is critical Short product life cycles End product is very feature
intensive Footprint/size of product
is shrinking
2. Qualify
End Product Profiles: Time to market is critical Low to medium volume (<25k)
Device security/non-volatility required
Military environment
2. Qualify
TTL Logic User / Discrete Logic Users Reduce # boards, size & cost
(10"sq: save $1/ layer)
Increase functionality: more features per inch2
Reduce power & cost (~$1.00 per Watt)
2. Qualify
TTL Logic User / Discrete Logic Users Need >1500 Gates to replace effectively
with FPGA
Not a good fit if designer doesn’t have defined spec
Good fit if user has schematic/simulation experience
2. Qualify
TTL User – Why Actel? Actel macro library combined with
ACTgen enables easy map from MSI/LSI
Actel offers the most cost effective device/in2
Integrating TTL shrinks PCB & # layers
Easy to change FPGA routing without I/O restrictions
2. Qualify
TTL User - Why Actel? Predictable delays
Determine fit before design start
Maintain performance during design iterations
Quickly find problems with Action Probe not: guess, blow & go!
2. Qualify
PLD User PLDs are best fit for:
<6 22V10
<3 7032
<15ns Tpd APPLICATIONS Actel is best at deep, multi-level
applications >1500 gates
2. Qualify
PLD user may think they need reprogrammability No simulation experience
Blow & go design style
Actel is better fit for flip flop intensive designs
1 FPGA needs much lower power than many PLDs
2. Qualify
Xilinx User Don’t waste your time on low
speed apps. Look for: <12 ns Clk – Q >40 MHz INTERNAL PERFORMANCE RANDOM LOGIC INTENSIVE
2. Qualify
Look for Xilinx user struggling with moving up to schematic capture!
Actel offers high speed, high capacity in same part
Pitch Actel as a complement: evaluate needs for each design
2. Qualify
Gate Array User Easy scenario to show Actel is
good solution Simulation is a way of life for gate
arrays
Actel architecture closest to gate array
2. Qualify
FPGAs allow faster time to market (proto & pre-prod)
FPGAs allow faster time to market (proto & pre-prod)
Design changes are faster and cheaper
Likely HDL users – Actel has a good story
2. Qualify
They most likely use CAE tools supported by Actel
MPGAs may be attractive for medium volume – no extra work!
And remember no gate array is reprogrammable
Actel is a single chip solution
2. Qualify
Breakout #2
Review your prospect list and eliminate any that are not good fits
Pick your best prospect Compile at least 5 qualifying
questions that you will use to determine if your prospects will likely become design wins
Objective: Formulate a plan to convince the decision makers to buy Actel FPGAs.
Gather critical sales info Who are decision makers?
What are their 3 main needs/issues?
When is the design start?
What role does FPGA play in the system?
3. Plan
Assemble appropriate strategy Assign specific actions
(eg. send demo to project eng, schedule corp presentation)
3. Plan
Some Available Resources
Selector Guides Data Book Actel Homepage Take it to a higher level video ACTgen Testdrive
3. Plan
Some Available Resources Designer Series Multimedia Demo Limited Software Eval Handling reprogrammability
(app note, presentation) Corporate & technical presentations
3. Plan
Some Available Resources Actel pricelist Actel RM, FAE & rep What else for ‘96
3. Plan
Breakout #3
Develop a sales strategy for your selected top prospect. Be sure to target: Project lead
Engineering Mgr
Management
Breakout #3
Create a plan to implement the specific actions for each of the targeted individuals
Assign responsibility for each action. Use your FAE, the Actel rep, FAE & RM!
S
Objective: Execute the salesstrategy to secure thedesign win.
Coordinate plan with Actel RM, FAE and rep
Design registration becomes a win when a $2,500 POS is placed
4. Win
Objective: Execute the salesstrategy to secure thedesign win.
Do quarterly review of POS to get pre-prod, volume production & next project start
Get $$’s!
S 4. Win
Breakout #4
List 3 problems or objections you may encounter in winning your selected account.
How would you overcome these problem? Consider the following to help you: Individuals who could help you Existing collateral Experience with other Actel wins
Objective: Take advantage of yoursuccess to exploit
otheropportunities.
Perform a design review Contact other users at account
that may be influenced by this win
5. LeverageS
Host seminar at account highlighting win
Do selective mailer to similar accounts focusing on specific benefits gained
... and you’re back to step 1 with more opportunities.
5. LeverageS
Breakout #5
Assuming you have just won the account, what specific actions can you take to get at least 2 new prospects/opportunities with your design win?
How soon should you follow up on these?
Summary
All together now . . .
Prospect Qualify
Plan
Win
Leverage
That’s the Actel Sales Process!!!
3 - PLAN3 - PLAN
2 - QUALIFY2 - QUALIFY
1 - PROSPECT1 - PROSPECT
4 - WIN4 - WIN
5 - LEVERAGE5 - LEVERAGE
Sals Leads
Compile a listof possible users.
Qualify prospectsto find best potentials.
Plan a sales strategy to convince decision makers.
Execute sales strategy to win the business. Leverage the win to
exploit other opportunities.S
S
1 - PROSPECT1 - PROSPECT
Stepsa) Examine your existing customer base for the following profile:
* Standard logic user (eg. Motorola, TI)* Programmable logic user (eg. Altera, AMD, Cypress, Lattice)* FPGA user (eg. Atmel, AT&T, Crosspoint, Quicklogic, Xilinx)* Gate array user (eg. AMI, Gould, LSI, VLSI) * CAE user (eg. Cadence, Mentor, OrCAD, Synopsys, Viewlogic)
b) Create a list of potential leads using the Prospect Worksheet.
c) Develop an opening line to get your prospect’s attention.
d) Call names on prospect list and setup visit or eliminate from list.
DeliverableList of names and phone numbers of potential Actel users.
Resources• Prospect Worksheet• Your previous Actel wins• Actel sales leads• Actel Market-Product Matrix
Actel Sales ProcessStepsa) Collect all project information using the Qualify
Worksheet.b) Use the FPGA Design Cycle chart (flip side) to
determine design phase:* Past critical window or no active design -> when is next design?* Within critical window -> you have a hot lead!
c) Determine the compelling customer needs for vendor selection (eg. capacity, performance, design time, tool support). DO NOT DISMISS any opportunity if customer believes he needs a reprogrammable solution. Use the Reprogramability Decision Information Brief.
d) Based on customer needs and price range, use the Actel Market-Product Matrix to determine the best family/device. Use the Cross Reference Guide if you have a competitive part number.
e) Complete and submit an Actel Design Win Registration form to secure a high margin! (Typically 3 registrations yield a design win).
DeliverableSubmission of design registrations for all qualified
prospects.
Resources• Qualify Worksheet• Sales Guides• Cross Reference Guide• Design Win Registration Form • Product Information Briefs• Decision Information Briefs
2 - QUALIFY2 - QUALIFY
Actel Sales Process
Stepsa) Review customer needs and objections/issues to
determine a specific sales strategy to win the business.
b) Develop specific actions using the available resources and the Planning Worksheet. There should be specific actions to convince all the decision makers.
c) Plan with your FAE, sales Rep, Actel FAE and Regional Manager.
DeliverableA strategy and plan of action to win the business.
Resources•Planning Worksheet•Sales Guides•Product Bulletins•“Sales Page” on Homepage•Sales Rep, Actel FAE & RM
TYPICAL FPGA TYPICAL FPGA DESIGN CYCLEDESIGN CYCLE
MilestoneMilestone
TimelineTimeline
designconcept
designspec
vendorselection
designstart
designdone
volumeproduction
obsoletenextspec
0 8 wks 12 wks 24 wks 28 wks 2 yrs
Critical Window
3 - PLAN3 - PLAN
4 - WIN4 - WIN SStepsa) It is your job to orchestrate all the
players necessary to execute the sales strategy and win the business.
b) You have invested considerable time to get to this stage. Don’t hesitate to use the Rep, Actel FAE, RM or other factory resource to help close the deal!
c) If you don’t win the design, even after the Rep or Actel is directly involved, understand why so you can use this with your next lead.
d) Your customer places $2500 POS order, and you have a design win!
e) Ask about other design opportunities!
DeliverableCustomer places a silicon POS order > $2500.
Resources•Tech & Corp Presentations•Selector Guides•Data Book•Actel Homepage•ACTgen Testdrive•Designer Multimedia Demo•Software Evals•Rep, Actel FAE & RM
Stepsa) Perform a design review with the
Leverage Worksheet to understand why you won. This information will be invaluable to secure other wins at the same or similar accounts.
b) Contact others at the account that may be influenced by the win.
c) Host an FPGA seminar at the account highlighting the current win.
d) Ask the design team for a letter of referral -- a powerful tool.
e) Go back to step 1 with these new opportunities!
DeliverableYou have 2 new prospects or design opportunities from the win.
Resources•Leverage Worksheet•Customer letter of referral•Host Actel Seminar
5 - LEVERAGE5 - LEVERAGE S
Actel Market-Product MatrixActel Market-Product MatrixComputer & Peripherals
Application Design Issues Actel Advantages FamilyUniversal Serial Bus Host Interface * Fast design iteration & debug cycle * Effective state machines3200DX
* High performance with synthesis * Fast dual-port SRAM* Multiple dynamic clocks * 6 global clock networks
32 Bit Image Compression * 40 MHz system clock speed * Fast devices ACT 3 PCI* One chip solution * Easy to use software* Short development time * Fast design iterations
ATM Network Interface Controller * Fast time to market * Flexible & routable architecture3200DX
* System logic integration * Fast SRAM blocks* 66 MHz system clock * Fast wide decode modules
Numerical Accelerator * Fast time to market * Assign I/Os before layout ACT 3* 40 MHz system clock using Verilog * Fast clock-to-outCommunications & Networking
Application Design Issues Actel Advantages FamilyHigh Speed Router * Vendor-idependent HLD * Synthesis frendly architecture ACT 3
* Easy conversion to gate array * Architecture very similar to gate arrays
Ethernet Media Access Controller * 100 Mbit/sec transfer rate * Fast devices and SRAM blocks 1200XL* Logic integration & small package * Asynchronous debug - Action Probe
High Speed Communications Link * Design flexibility * 100% automatic place & route 1200XL* Logic integration & low power * Board layout before FPGA done
ATM Switch Fabric * Fast time to market * Predictable delays & ACTgen ACT 3* High performance * Multiplexer-based logic module
Industrial & Medical
Application Design Issues Actel Advantages FamilyMedical Imaging * < 6 month design time * Fast design iteration 1200XL
* Use of existing CAE tools * Actel supports all major CAE tools* Decrease board space * Large and flexible devices
Time to Digital Converter * Design flexibility * FPGA changes with fixed I/Os 1200XL* Fast design iterations * Automatic place & route tools ACT 1
DSP Finite Impulse Response Filter * 40 MHz system clock speed * Fast register-to-register ACT 3* Variable coefficients * Device flexibility
100 MBit Image Setter * 100 MHz counters * Load-latency technique & fast parts 1200XL* Design flexibility * 100% automatic place & route tools
Military & Aerospace
Application Design Issues Actel Advantages FamilyCommercial Satellites * High reliability * Impeccable antifuse track record RH
* Space qualified devices * High radiation tolerance* Decrease board space * Large & flexible devices
Tracking Data and Relay * Non-volative technology * Antifuse is only high capacity solution ACT 2* Military grade FPGA * Actel is the only FPGA military vendor
Guidance Systems * Device security * Antifuse is reverse-engineering proof ACT 1* Very high device reliability * No antifuse failures ever reported
Field Communications * Board space reduction * Actel is the only FPGA military vendor ACT 2* Design flexibility * 100% automatic place & route
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