Adib AbrishamifarEE Department
IUST
Lecture 8 – Design Rules
Digital Integrated Circuit Design
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 20082/50
} Design Rules} CMOS Process Layers} Intra-Layer Design Rules} Via’s and Contacts} Select Layer} Example
} Cell Design} Standard Cells} Datapath Cells
} Sticks Diagrams} Logic Graph} Euler Path} Area Estimation
} Summary
Contents
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 20083/50
} Interface between designer and process engineer} Guidelines for constructing process masks} Unit dimension: Minimum line width} scalable design rules: lambda parameter} absolute dimensions (micron rules)
Design Rules
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 20084/50
Layer
PolysiliconMetal1Metal2Contact To PolyContact To DiffusionVia
Well (p,n)Active Area (n+,p+)
Color Representation
YellowGreen
RedBlueMagentaBlackBlackBlack
Select (p+,n+) Green
Design Rules
} CMOS Process Layers
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 20085/50
Metal2 4
3
10
90
Well
Active3
3
Polysilicon2
2
Different PotentialSame Potential
Metal1 3
32
Contactor Via
Select2
or6
2Hole
} Intra-Layer Design Rules
Design Rules
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 20086/50
} Transistor Layout
Design Rules
1
2
5
3
Tran
sisto
r
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 20087/50
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
Design Rules
} Via’s and Contacts
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 20088/50
1
3 3
2
2
2
WellSubstrate
Select3
5
Design Rules
} Select Layer
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 20089/50
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
Design Rules
} CMOS Inverter Layout
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200810/50
} Design Rules} CMOS Process Layers} Intra-Layer Design Rules} Via’s and Contacts} Select Layer} Example
} Cell Design} Standard Cells} Datapath Cells
} Sticks Diagrams} Logic Graph} Euler Path} Area Estimation
} Summary
Contents
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200811/50
} Standard Cells} General purpose logic} Can be synthesized} Same height, varying width
} Datapath Cells} For regular, structured designs (arithmetic)} Includes some wiring in the cell} Fixed height and width
Cell Design
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200812/50
} Layout can be very time consuming} Design gates to fit together nicely} Build a library of standard cells
} Standard cell design methodology} Vdd and GND should abut (standard height)} Adjacent gates should satisfy design rules} NMOS at bottom and PMOS at top} All gates include well and substrate contacts
Cell Design
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200813/50
signals
Routingchannel
VDD
GND
Cell Design
} Standard Cell Layout Methodology-1980s
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200814/50
M1
No Routingchannels VDD
GNDM2
VDD
GND
Mirrored Cell
Mirrored Cell
Cell Design
} Standard Cell Layout Methodology-1990s
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200815/50
Cell boundary
N WellCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch = repetitive distance between objects
Cell height is “12 pitch”
2λ
Rails ~10λ
In Out
VDD
GND
Cell Design
} Standard Cells
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200816/50
In Out
VDD
GND
In Out
VDD
GND
With silicideddiffusion
With minimaldiffusionrouting
OutIn
VDD
M 2
M 1
Cell Design
} Standard Cells
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200817/50
A
Out
VDD
GND
B
2-input NAND gate
B
VDD
A
Cell Design
} Standard Cells
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200818/50
OutIn
VDD
PMOS
NMOS
Polysilicon
In Out
VDD
GND
PMOS 2λ
Metal 1
NMOS
Contacts
N Well
Cell Design
} Standard Cells} CMOS Inverter
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200819/50
Connect in Metal
Share power and ground
Cell Design
} Standard Cells} Two Inverters
VDD
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200820/50
One finger Two fingers (folded)
Less diffusion capacitance
} Multi-Fingered Transistors
Cell Design
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200821/50
Cell Design
} Inverter
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200822/50
} NAND3} Horizontal N-diffusion and P-diffusion strips} Vertical polysilicon gates} Metal1 Vdd rail at top} Metal1 GND rail at bottom
Cell Design
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200823/50
} Design Rules} CMOS Process Layers} Intra-Layer Design Rules} Via’s and Contacts} Select Layer} Example
} Cell Design} Standard Cells} Datapath Cells
} Sticks Diagrams} Logic Graph} Euler Path} Area Estimation
} Summary
Contents
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200824/50
} To help plan layout quickly• Need not be to scale• Draw with color pencils or dry-erase markers
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200825/50
In
Out
VDD
GND
Inverter
A
Out
VDD
GNDB
NAND2
Sticks Diagrams
} Contains No Dimensions} Represents Relative Positions of Transistors
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200826/50
} Stick Diagram for a 4-input NOR Gate
AVDD
GND
B C
Y
D
Sticks Diagrams
A
B
C
D
A B C D
Vdd+
Y
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200827/50
j
VDDX
X
i
GND
AB
C
(PUN)
(PDN)
Logic Graph
} Logic Graph
Sticks Diagrams
Pull Up Network
Pull Down Network
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200828/50
C
A B
X = (A+B)•(C+D)
B
A
D
VDDX
X
GND
AB
C
PUN
PDN
C
D
D
ABCD
} OAI22 Logic Graph
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200829/50
C
A B
X = C • (A + B)
B
AC
i
j
j
VDDX
X
i
GND
AB
C
PUN
PDNABC
Logic Graph
} Logic Graph
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200830/50
X
CA B A B C
X
VDD
GND
VDD
GND
} Two Versions of C(A + B)
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200831/50
j
VDDX
X
i
GND
AB
C
A B C
} Consistent Euler Path
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200832/50
} Euler Path and Circuit } As legend has it, a resident of Konigsberg wrote to
Leonard Euler saying that a popular pastime for couples was to try to cross each of the seven bridges in the city exactly once, without crossing any bridge more than once
} It was well-known that the feat could not be accomplished, yet no one knew why. Could Euler, great mathematician as he was, answer that question
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200833/50
} Euler Path and Circuit } In Konigsberg, Germany, a river ran through the city
such that in its center was an island, and after passing the island, the river broke into two parts. Seven bridges were built so that the people of the city could get from one part to another as below
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200834/50
} Euler Path and Circuit } Euler realized that all problems of this form could be
represented by replacing areas of land by points (he called them vertices), and the bridges to and from them by arcs
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200835/50
} Euler Path and Circuit } Once the problem is simplified the graph of the
bridges and land look like this
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200836/50
} Euler Path and Circuit } The problem now becomes one of drawing this
picture without retracing any line and without picking your pencil up off the paper
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200837/50
} Euler Path and Circuit } Euler looked at the vertices that had an odd number
of lines connected to it} He stated they would either be the beginning or end
of his pencil-path
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200838/50
} Euler Path and Circuit } Euler path: a continuous path that passes through
every edge once and only once} Euler circuit: when a Euler path begins and ends at
the same vertex
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200839/50
} Euler Path and Circuit } Euler’s 1st Theorem
• If a graph has any vertices of odd degree, then it can't have any Euler circuit
• If a graph is connected and every vertex has an even degree, then it has at least one Euler circuit (usually more)
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200840/50
} Euler Path and Circuit } Euler’s 2nd Theorem
• If a graph has more than two vertices of odd degree, then it cannot have an Euler path
• If a graph is connected and has exactly two vertices of odd degree, then is has at least one Euler path. Any such path must start at one of the odd degree vertices and must end at the other odd degree vertex
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200841/50
} Euler Path and Circuit } Path, circuit, or neither…?
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200842/50
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {a b c d}b
} Example: x = ab + cd
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200843/50
} Area Estimation} Wiring Tracks
• A wiring track is the space required for a wire– 4 λ width, 4 λ spacing from neighbor = 8 λ pitch
• Transistors also consume one wiring track
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200844/50
} Area Estimation} Well Spacing
• Wells must surround transistors by 6 λ– Implies 12 λ between opposite transistor flavors– Leaves room for one wire track
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200845/50
} Area Estimation} Estimate area by counting wiring tracks
• Multiply by 8 to express in λ
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200846/50
} Area Estimation} Stick diagram for O3AI and
estimate area
• Y = ( A + B + C) D
Sticks Diagrams
A
B
C
D
B C
D
Vdd+
Y
A
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200847/50
} Area Estimation} Stick diagram for O3AI and estimate area
• Y = ( A + B + C) D
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200848/50
} Area Estimation} Sketch a stick diagram for O3AI and estimate area
• Y = ( A + B + C) D
Sticks Diagrams
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200849/50
} Design Rules} CMOS Process Layers} Intra-Layer Design Rules} Via’s and Contacts} Select Layer} Example
} Cell Design} Standard Cells} Datapath Cells
} Sticks Diagrams} Logic Graph} Euler Path} Area Estimation
} Summary
Contents
IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 200850/50
Summary
} This lecture describes the basic design rules for the layout of both MOS and CMOS transistors, cells design methodologies and also sticks diagrams. Specifically described in detail are:} Design Rules} Cells Design Methodologies} Sticks Diagrams} Logic Graph} Euler Path} Area Estimation
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