11/5/2004 EE 42 fall 2004 lecture 28 1
Lecture #28 PMOS
• LAST TIME: NMOS Electrical Model– NMOS physical structure: W and L and dox,
• TODAY: PMOS– Physical structure– CMOS– Dynamic circuits (Ring oscillators)
11/5/2004 EE 42 fall 2004 lecture 28 2
n
P
oxide insulatorn
drain
- +
source
gate
NMOS =device which carrier current using electrons but on the surface of a p-type substrate (p-type substrate
means that no electrons are available)
n
P
oxide insulatorn
drainsource N-MOS In this device the gate controls electron flow from source to drain.
(in the absence of gate voltage, current is blocked)
gate
VGS > Vt
If we increase gate voltage to a value greater than Vt
then a conducting channel forms between source and drain. (“Closed switch”)
11/5/2004 EE 42 fall 2004 lecture 28 3
CMOS = Complementary MOS(PMOS is a second Flavor)
n
P
oxide insulatorn
drainsource N-MOS
In this device the gate controls electron flow from source to drain.
The NEW FLAVOR! P-MOS
It is made in p-type silicon.
It is made in n-type silicon. (In n-type silicon no positive charges (“holes”) are normally around.)
In this device the gate controls hole flow from source to drain.
gate
source drain
n-type Si
P-MOSgate
p p
11/5/2004 EE 42 fall 2004 lecture 28 4
PMOS
It is made in n-type silicon.
In this device the gate controls hole flow from source to drain.
source
drain
n-type Si p
gate
+ -
p
What if we apply a big negative voltage on the gate?
If |VGS |>|Vt | (both negative)
then we induce a + charge on the surface (holes)
source drain
n-type Si
P-MOSgate
p p
|VGS |>|Vt |
11/5/2004 EE 42 fall 2004 lecture 28 5
NMOS and PMOS Compared
NMOS“Body” – p-typeSource – n-typeDrain – n-type VGS – positive
VT – positive
VDS – positive
ID – positive (into drain)
PMOS“Body” – n-typeSource – p-typeDrain – p-type VGS – negative
VT – negative
VDS – negative
ID – negative (into drain)G
n nID
DS
p
B
G
pID
DS
nB
ID
4321VDS
VGS=3V1 mA
VGS=0
(for IDS = 1mA)
4321VDS
VGS= 3V1 mA
VGS=0
ID
(for IDS = -1mA)
11/5/2004 EE 42 fall 2004 lecture 28 6
NMOS circuit symbol
CIRCUIT SYMBOLS
G
S
D
A small circle is drawn at the gate to remind us that the polarities are reversed for PMOS.
PMOS circuit symbol
G
S
D
11/5/2004 EE 42 fall 2004 lecture 28 7
PMOS Transistor Switch Model
Operation compared to NMOS: It is complementary.
For PMOS for the normal circuit connection is to connect S to VDD (The function of the device is a “pull up”)
VG = VDD
Switch is open : Drain (D) is disconnected from Source (S) when VG = VDD
VG =0
Switch is closed: Drain (D) is connected to Source (S) when VG =0
G
S
D
VDD
VDD
Switch OPEN
VDD
G
S
D
V=0
Switch CLOSED
S
D
G
11/5/2004 EE 42 fall 2004 lecture 28 8
PMOS Model RefinementPMOS transistor has an equivalent resistance RDP when closed
The circuit symbol
G
D
S
P Ch
S
D
G
RDP
The Switch model
CGS
There is also a gate capacitance CGS, just as in NMOS
11/5/2004 EE 42 fall 2004 lecture 28 9
CMOS
Challenge: build both NMOS and PMOS on a single silicon chip
NMOS needs a p-type substrate
PMOS needs an n-type substrate
Requires extra process steps
oxide
P-Si n-well
p p n n
GDG DSS
11/5/2004 EE 42 fall 2004 lecture 28 10
THE BASIC STATIC CMOS INVERTER
voutvin
VDD
PMOS
NMOSFor Vin < 1V NMOS off , PMOS on
For Vin > 1.5V NMOS on , PMOS off
source
drain
source
drain
Example for Discussion:
NMOS: VTn = 1 V
PMOS: VTp = -1 V
Let VDD = 2.5V
Vout = 0
Vout = VDD
Vin Vout
VDD
Vin
VDD
Vout
11/5/2004 EE 42 fall 2004 lecture 28 11
THE BASIC STATIC CMOS INVERTERQuasi-static operation (ignoring transients)
voutvin
VDD
PMOS
NMOSFor Vin < 0.5V NMOS off , PMOS on
For Vin > 2V NMOS on , PMOS off
source
drain
source
drain
Example for Discussion:
NMOS: VTn = 0.5 V
PMOS: VTp = - 0.5 V
Let VDD = 2.5V
Vout = 0
Vout = VDD
Vin Vout
VDD
Vin
VDD
Vout
11/5/2004 EE 42 fall 2004 lecture 28 12
CMOS INVERTER TRANSFER CURVE
voutvin
VDD
PMOS
NMOS
Transfer Curve
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
Vin
Vo
ut
11/5/2004 EE 42 fall 2004 lecture 28 13
CHAIN OF CMOS INVERTERS
Vout
If the input is toggled, the state of every inverter will change and there will be a gate delay for every gate caused by the combination of the output resistance of the switching devices combined with the input capacitance of the following stage. Let’s estimate the stage delay.
STAGE M
VDD VDD VDD VDD
vin
VDD
Vout
Vin
VDD
11/5/2004 EE 42 fall 2004 lecture 28 14
CHAIN OF CMOS INVERTERS STAGE-M
When the input VM is high, the lower (NMOS) switch is closed and according to
our model the resistor RN discharges the input capacitance of the next gate, the capacitors CGN and CGP in parallel.
The time constant is RN(CGN+CGP) so the gate delay is 0.69 RN(CGN+CGP) .
We do not consider here the capacitance of the gates in Stage M, because they load Stage M-1, and contribute to its delay.
VDD
VM+1VM
DDV the model
VM
VDD
VM+1RN
CGP
CGN
gate delay if input HIGH
“Open”
“Closed”M M+1
VDD
11/5/2004 EE 42 fall 2004 lecture 28 15
Core Circuit for “Pull-Down” Transition
Circuit only contains one resistor and two capacitors
Capacitors CGp and CGn … how can they be
combined into one?
Capacitors share one node; the other nodes are held at constant voltages. vC(t)
V = 01
V = VDD2
C2
C1
i( )2( )
i1 t)
ti t
(KCL: currents sum at common node, ie node capacitance is SUM (parallel capacitor formula).
“Virtually Parallel” Capacitors
11/5/2004 EE 42 fall 2004 lecture 28 16
Pull-Down Equivalent Circuit
Two capacitors add for finding the charging current applies to gate capacitances
Rn
vout1
DCGn + CGp
t = 0+
Precharge: VDD
vout1 =v in2
vin1+ -
VDD
vout2
Lets once more associate circuit above to the actual inverter circuit.
11/5/2004 EE 42 fall 2004 lecture 28 17
Equivalent circuit vs actual circuit
Rn
vout1
DCGn + CGp
t = 0+
Precharge: VDD
1) Remove inactive device
vout1
v in2
vin1+ -
VDD
vout2
3) Replace NMOS pull-down by by its output equivalent.
2) Replace load devices by their input equivalents
11/5/2004 EE 42 fall 2004 lecture 28 18
Gate Delay from Pull-Down Equivalent Circuit
Capacitor is precharged to VDD and discharged to ground through
resistance Rn.
Rn
vout1
DCGn + CGp
t = 0+
Precharge: VDD
If we define the switching delay as the time for the output voltage to swing halfway to its new steady-state value, we will find the switching delay is 0.69RC. [remember 0.5 = exp(-0.69)]
t/RC
VDD
VDD
0.69
2
VDD exp(-t/RC)
Vout1We can compute the delay easily. It is just an RC delay.
11/5/2004 EE 42 fall 2004 lecture 28 19
CHAIN OF CMOS INVERTERS STAGE-M
When the input VM is low, the upper (PMOS) switch is closed and
according to our model the resistor RP charges the input capacitance of the next gate, the capacitors CGN and CGP in parallel.
The time constant is RP(CGN+CGP) so the gate delay is 0.69 RP(CGN+CGP).
Normally we try to have equal rising and falling gate delay, so for the simple inverter we design the transistors so RP = RN.
VDD
VM+1VM
DDV
gate delay if input LOW
“CLOSED”
“Open” M M+1
the model
VDD
VM+1
RP CGP
CGN
VM
VDD
11/5/2004 EE 42 fall 2004 lecture 28 20
CMOS PARAMETERS3 generations of CMOS
Return
Parameter NMOS PMOS NMOS PMOS NMOS PMOS (0.25m) (0.25m) (0.18m) (0.18m) (0.13m) (0.13m) L (m) 0.25 0.25 0.18 0.18 0.13 0.13 IDS’ (A/[V-m]) 350 -175 500 - 250 650 - 325 V-1 0.05 0.05 0.07 0.07 0.1 0.1 VT
V) 0.5 - 0.5 0.4 - 0.4 0.4 - 0.4 VDSAT
V) 1 -1 0.75 - 0.75 0.6 - 0.6 dOX
nm) 5 5 3.5 3.5 2.5 2.5 CGS ‘fF/m2) 7 7 10 10 14 14 VDD
V) 2.5 2.5 1.8 1.8 1.5 1.5
11/5/2004 EE 42 fall 2004 lecture 28 21
Interconnect layers
• On top of the transistor layers, many metal layers interconnect the logic
Illustration Actual TEM photo
11/5/2004 EE 42 fall 2004 lecture 28 22
CHAIN OF CMOS INVERTERS TO MEASURE delay
If the input is toggled, the state of every inverter will change and there will be a gate delay for every gate. Suppose there are 1001 gates and we move the input switch from VDD to ground. 1001 gate delays later the output will go from ground to VDD.
Vout
STAGE 1VDD STAGE 101
But suppose in the meantime we moved the switch to connect to Vout (which is initially zero).
At at time equal to exactly 1001 gate delays, the input to stage 1 will go high, and after another equal time it will go low, etc. We have created a “RING OSCILLATOR”, which toggles at a frequency equal to 1/(1001 delay ).
Such ring oscillators are commonly used to estimate the performance of a technology. No switch is actually needed, the output is permanently wired to the input, and the oscillations start when power is applied.
11/5/2004 EE 42 fall 2004 lecture 28 23
CMOS INVERTERS DRIVING ANY LOAD
If we substitute the switch model for the transistors we have the following circuit:
VDDNo matter what the load is, the behavior is the same: the stage delay is 0.69RC where C= CLOAD and R= RN if input is switched high or R= RP if input is switched low.
VoutCLOAD
Rn
D
CLOAD
VDD
Rp Vout
The actual load consists of whatever gates are attached to the node plus any additional capacitance. In the next lecture we will compute the gate capacitance on the input to any NAND logic block for example. As another example, if an external wire is attached to a node with the wire going to a printed circuit board, we will have a load of several pF.
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