Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 020 - SUBMICRON CMOS TECHNOLOGYLECTURE ORGANIZATION
Outline• CMOS Technology• Fundamental IC Process Steps• Typical Submicron CMOS Fabrication Process• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 18-29
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-2
CMOS Analog Circuit Design © P.E. Allen - 2010
CMOS TECHNOLOGYClassification of Silicon Technology
Silicon IC Technologies
gate gate gate gate060112-02
JunctionIsolated
Dielectric Isolated
Oxideisolated
CMOSPMOS
(Aluminum Gate)
NMOS
Bipolar Bipolar/CMOS MOS
Aluminum Silicon Aluminum Silicon Silicon-Germanium
Silicon
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Categorization of CMOS Technology• Minimum feature size as a function of time:
1
0.1
0.01
Min
imum
Fea
ture
Siz
e (µ
m)
1985 1990 1995 2000 2005 2010070215-01Year
Deep Submicron Technology
Ultra Deep Submicron Technology
Submicron Technology
• Categories of CMOS technology:1.) Submicron technology – Lmin 0.35 microns2.) Deep Submicron technology (DSM) – 0.1 microns Lmin 0.35 microns3.) Ultra-Deep Submicron technology (UDSM) – Lmin 0.1 microns
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Why CMOS Technology?Comparison of BJT and MOSFET technology from an analog viewpoint:
Comparison Feature BJT MOSFETCutoff Frequency(fT) 100 GHz 50 GHz (0.25μm)
Noise (thermal about the same) Less 1/f More 1/fDC Range of Operation 9 decades of exponential
current versus vBE
2-3 decades of square lawbehavior
Transconductance (Same current) Larger by 10X Smaller by 10XSmall Signal Output Resistance Slightly larger Smaller for short channelSwitch Implementation Poor GoodCapacitor Voltage dependent More optionsPerformance/Power Ratio High LowTechnology Improvement Slower Faster
Therefore,• Almost every comparison favors the BJT, however a similar comparison made from a
digital viewpoint would come up on the side of CMOS.• Therefore, since large-volume mixed-mode technology will be driven by digital
demands, CMOS is an obvious result as the technology of availability.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-5
CMOS Analog Circuit Design © P.E. Allen - 2010
How Does IC Technology Influence Analog IC Design?
Characteristics of analog IC design:• Continuous in signal amplitude• Discrete or continuous in time• Signal processing primarily depends on ratios of values and time constants
- Ratios are generally resistance, conductance, or capacitance- Time constants are generally products of resistance and capacitance
• Dynamic range is determined by the largest and smallest signals
Influence of IC Technology:• Accuracy of signal processing depends on the accuracy of the ratios of values• The dynamic range depends upon the linearity of the circuit elements and the noise• The value of components is limited by area considerations• IC technology introduces resistive, capacitive and inductive parasitics that cause
deviation from desired behavior• The analog circuit is subject to the influence of other circuits fabricated in the same
substrate
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-6
CMOS Analog Circuit Design © P.E. Allen - 2010
FUNDAMENTAL IC PROCESS STEPSBasic Steps• Oxide growth• Thermal diffusion• Ion implantation• Deposition• Etching• Shallow trench isolation• EpitaxyPhotolithographyPhotolithography is the means by which the above steps are applied to selected areas ofthe silicon wafer.Silicon Wafer
0.5-0.8mm
n-type: 3-5 Ω-cmp-type: 14-16 Ω-cm Fig. 2.1-1r
125-200 mm(5"-8")
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-7
CMOS Analog Circuit Design © P.E. Allen - 2010
OxidationDescription:Oxidation is the process by which a layer of silicon dioxide is grown on the surface of asilicon wafer.
Original silicon surface
0.44 tox
tox
Silicon substrate
Silicon dioxide
Fig. 2.1-2
Uses:• Protect the underlying material from contamination• Provide isolation between two layers.Very thin oxides (100Å to 1000Å) are grown using dry oxidation techniques. Thickeroxides (>1000Å) are grown using wet oxidation techniques.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-8
CMOS Analog Circuit Design © P.E. Allen - 2010
DiffusionDiffusion is the movement of impurity atoms at the surface of the silicon into the bulk ofthe silicon. Always in the direction from higher concentration to lower concentration.
HighConcentration
LowConcentration
Fig. 150-04
Diffusion is typically done at high temperatures: 800 to 1400°C
Depth (x)
t1 < t2 < t3
t1t2
t3
N(x)
NB
Depth (x)
t1 < t2 < t3
Infinite source of impurities at the surface. Finite source of impurities at the surface.
N0
Fig. 150-05
ERFC Gaussian
t1 t2t3
N(x)
NB
N0
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Ion ImplantationIon implantation is the process by whichimpurity ions are accelerated to a highvelocity and physically lodged into thetarget material.
• Annealing is required to activate theimpurity atoms and repair the physicaldamage to the crystal lattice. This stepis done at 500 to 800°C.
• Ion implantation is a lower temperatureprocess compared to diffusion.
• Can implant through surface layers, thus it isuseful for field-threshold adjustment.
• Can achieve unique doping profile such asburied concentration peak.
Path of impurity
atom
Fixed Atom
Fixed Atom
Fixed AtomImpurity Atomfinal resting place
Fig. 150-06
N(x)
NB
0 Depth (x)
Concentration peak
Fig. 150-07
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-10
CMOS Analog Circuit Design © P.E. Allen - 2010
DepositionDeposition is the means by which various materials are deposited on the silicon wafer.Examples: • Silicon nitride (Si3N4)
• Silicon dioxide (SiO2)
• Aluminum • PolysiliconThere are various ways to deposit a material on a substrate: • Chemical-vapor deposition (CVD) • Low-pressure chemical-vapor deposition (LPCVD) • Plasma-assisted chemical-vapor deposition (PECVD) • Sputter depositionMaterial that is being deposited using these techniques covers the entire wafer andrequires no mask.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Etching
Etching is the process of selectivelyremoving a layer of material.When etching is performed, the etchant mayremove portions or all of: • The desired material • The underlying layer • The masking layerImportant considerations: • Anisotropy of the etch is defined as,
A = 1-(lateral etch rate/vertical etch rate) • Selectivity of the etch (film to mask and film to substrate) is defined as,
Sfilm-mask = film etch rate
mask etch rate A = 1 and Sfilm-mask = are desired.
There are basically two types of etches: • Wet etch which uses chemicals • Dry etch which uses chemically active ionized gases.
MaskFilm
bUnderlying layer
a
c
MaskFilm
Underlying layer
(a) Portion of the top layer ready for etching.
(b) Horizontal etching and etching of underlying layer.Fig. 150-08
Selectivity
AnisotropySelectivity
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-12
CMOS Analog Circuit Design © P.E. Allen - 2010
EpitaxyEpitaxial growth consists of the formation of a layer of single-crystal silicon on thesurface of the silicon material so that the crystal structure of the silicon is continuousacross the interfaces.• It is done externally to the material as opposed to diffusion which is internal• The epitaxial layer (epi) can be doped differently, even opposite to the material on
which it is grown• It is accomplished at high temperatures using a chemical reaction at the surface• The epi layer can be any thickness, typically 1-20 microns
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
+
-
-
-
- -
-
+
+
+
Gaseous cloud containing SiCL4 or SiH4
Si Si Si Si+
Fig. 150-09
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-13
CMOS Analog Circuit Design © P.E. Allen - 2010
PhotolithographyComponents
• Photoresist material• Mask• Material to be patterned (e.g., oxide)
Positive photoresistAreas exposed to UV light are soluble in the developerNegative photoresistAreas not exposed to UV light are soluble in the developerSteps1. Apply photoresist2. Soft bake (drives off solvents in the photoresist)3. Expose the photoresist to UV light through a mask4. Develop (remove unwanted photoresist using solvents)5. Hard bake ( 100°C)6. Remove photoresist (solvents)
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of Photolithography - ExposureThe process of exposingselective areas to lightthrough a photo-mask iscalled printing.Types of printing include:• Contact printing• Proximity printing• Projection printing
Photoresist
Photomask
UV Light
Photomask
Polysilicon
Fig. 150-10
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Illustration of Photolithography - Positive Photoresist
Photoresist
Photoresist
Polysilicon
Polysilicon
Polysilicon
Etch
Removephotoresist
Develop
Fig. 150-11
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-16
CMOS Analog Circuit Design © P.E. Allen - 2010
TYPICAL SUBMICRON CMOS FABRICATION PROCESSN-Well CMOS Fabrication Major Steps 1.) Implant and diffuse the n-well 2.) Deposition of silicon nitride 3.) n-type field (channel stop) implant 4.) p-type field (channel stop) implant 5.) Grow a thick field oxide (FOX) 6.) Grow a thin oxide and deposit polysilicon 7.) Remove poly and form LDD spacers 8.) Implantation of NMOS S/D and n-material contacts 9.) Remove spacers and implant NMOS LDDs10.) Repeat steps 8.) and 9.) for PMOS11.) Anneal to activate the implanted ions12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass)13.) Open contacts, deposit first level metal and etch unwanted metal14.) Deposit another interlayer dielectric (CVD SiO2), open vias, deposit 2nd level metal
15.) Etch unwanted metal, deposit a passivation layer and open over bonding pads
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps
n-well implant
Photoresist Photoresist
Si3N4
n-well
p- substrate
p- substrate
SiO2
SiO2
Step 1 - Implantation and diffusion of the n-wells
Step 2 - Growth of thin oxide and deposition of silicon nitride
070523-01
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps – Continued
Photoresist
p- field implant
Si3N4
n-well
PhotoresistPhotoresist
n- field implant
Pad oxide (SiO2)
n-well
Si3N4
p- substrate
p- substrate
Step 3.) Implantation of the n-type field channel stop
Step 4.) Implantation of the p-type field channel stop
070523-02
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps – Continued
FOX
Polysilicon
n-well
FOX
n-well
Si3N4
p- substrate
p- substrate
FOX
FOX
Step 5.) Growth of the thick field oxide (LOCOS - localized oxidation of silicon)
Step 6.) Growth of the gate thin oxide and deposition of polysilicon. The thresholds can be shifted by an implantation before the deposition of polysilicon.
070523-03
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps – Continued
Step 7.) Removal of polysilicon and formation of the sidewall spacers
Step 8.) Implantation of NMOS source and drain and contact to n-well (not shown)
070523-04
Photoresist
SiO2 spacerPolysilicon
FOX
n-wellp- substrate
FOX
Photoresist
n+ S/D implant
Polysilicon
FOX
n-wellp- substrate
FOX
FOXFOX
FOXFOX
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps - Continued
070209-03
Photoresist
n- S/D LDD implant
Polysilicon
FOX
n-wellp- substrate
FOX
Polysilicon
FOX
n-wellp- substrate
FOX
LDD Diffusion
FOX FOX
FOX FOX
Step 9.) Remove sidewall spacers and implant the NMOS lightly doped source/drains
Step 10.) Implant the PMOS source/drains and contacts to the p- substrate (not shown), remove the sidewall spacers and implant the PMOS lightly doped source/drains
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps – Continued
Step 11.) Anneal to activate the implanted ions
Step 12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass)
070523-05
BPSG
Polysiliconn+ Diffusion p+ Diffusion
FOX FOXn-well
Polysilicon
n-well
n+ Diffusion p+ Diffusion
FOX FOX
p- substrate
p- substrate
FOX
FOX
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps - Continued
BPSG
n-wellFOXFOX
p- substrate
BPSG
n-well
Metal 1
FOXFOX
p- substrate
Metal 2
Metal 1CVD oxide, Spin-on glass (SOG)
FOX
FOX
Step 13.) Open contacts, deposit first level metal and etch unwanted metal
Step 14.) Deposit another interlayer dielectric (CVD SiO2), open contacts, deposit second level metal
070523-06
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Major CMOS Process Steps – Continued
070523-07
BPSG
n-well
Metal 1
FOXFOX
p- substrate
Metal 2Passivation protection layer
FOX
Step 15.) Etch unwanted metal and deposit a passivation layer and open over bonding pads
p-well process is similar but starts with a p-well implant rather than an n-well implant.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Approximate Side View of CMOS Fabrication
Metal 4
Metal 3
Metal 2
Metal 1
Passivation
Polysilicon
Diffusion
2 microns
070523-08
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-26
CMOS Analog Circuit Design © P.E. Allen - 2010
PlanarizationPlanarization attempts to minimize the variation in surface height of the wafer.Planarization techniques
• Repeated applications of SOG• Resist etch-back – highest areas of
oxide are exposed longest to theetchant and therefore erode away themost.
Influence of planarization on analog design:+ Number of levels of metal and the metal integrity depends on planarization+ Thin film components at the surface require good planarization+ Without planarization, resistance of conductors increases+ Planarization at the top level leads to less package induced stress (trimming?)+ Planarized passivation helps printing when the depth of field is small.- With planarization, the capacitance of the interdielectric isolation can vary (a good
reason to extract capacitance!)- Significant difference in contact aspect ratio (deep versus shallow contacts)
TungstenPlug
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Chemical Mechanical PolishingCMP produces the required degree of planarization for modern submicron technology.
• Both chemical effect (slurry) and mechanical (pad pressure) take place.• Although CMP is superior to SOG and resist etchback, large areas devoid of underlying
metal or poly produce low regions in the final surface.• Challenge: Achieve a highly planarized surface over a wide range of pattern density.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Horizontal Stripe Fill Vertical Stripe FillLayout with white space
070810-02
CMP Planarization
Pattern Fill
CMP Planarization
070810-01
Chemical Mechanical Polishing – ContinuedImpact on analog design: + Makes the surface flatter
- Vias and plugs can become longer adding resistance+ More uniform surface giving better metal coverage and foundation for thin film
components- Thickness varies with pattern density
Examples of pattern fill:
Pattern density design rules are both local and global.
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Silicide/Salicide TechnologyUsed to reduce interconnect resistivity by placing a low-resistance silicide such as TiSi2,WSi2, TaSi2, etc. on top of polysiliconSalicide technology (self-aligned silicide) provides low resistance source/drainconnections as well as low-resistance polysilicon.
Metal
FOX
Polysilicide
Polycide structure Salicide structure
FOX
070523-09
FOX
Polysilicide
FOX
Salicide
Metal
Lecture 020 – Submicron CMOS Technology (3/24/10) Page 020-30
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Fabrication is the means by which the circuit components, both active and passive, are
built as an integrated circuit.• Basic process steps include:
1.) Oxide growth 2.) Thermal diffusion 3.) Ion implantation4.) Deposition 5.) Etching 6.) Epitaxy
• The complexity of a process can be measured in the terms of the number of maskingsteps or masks required to implement the process.
• Major CMOS Processing Steps: 1.) Well definition 2.) Definition of active areas and substrate/well contacts (SiNi3) 3.) Thick field oxide (FOX) 4.) Thin field oxide and polysilicon 5.) Diffusion of the source and drains (includes the LDD) 6.) Dielectric layer/Contacts (planarization) 7.) Metallization 8.) Dielectric layer/Vias
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