LOGICAL DESIGN 2
Course titular:DUMITRAŞCU Eugen
SEQUENTIAL LOGIC CIRCUITS
CHAPTER 4
08-Mar-20 LD2_04 2019-2020 3
CONTENT
Definitions; classifications Models of deterministic synchronous
SLC Methods of specifying SLC Flip-flop circuits SLC analysis
08-Mar-20 LD2_04 2019-2020 4
DEFINITIONS; CLASSIFICATIONSDefinitions It is called sequential logic circuit (SLC) any logical circuit
whose output values depend on, at a given moment ti, by theinput values of considered moment and the input values at previous moments ti-1, ti-2,....
It is called sequential logic scheme (SLS) any graphical representation of a SLC.
It is called sequential machine (SM) the mathematical model of a sequential logic circuit.
08-Mar-20 LD2_04 2019-2020 5
DEFINITIONS; CLASSIFICATIONS It is called sequential machine (automaton) a 6-tuple:
SM=<X, Z, S, f, g, S0>where:X - input space, that is the set of values that may appear on the
input of sequential machine;Z – output space, that is the set of output values that can occur
on the output of sequential machine;S - state-space, that is the set of states of sequential machine;S0 - initial state, S0 S;f – output function;g - transition function of states.
A sequential machine with a finite number of states is called a finite state machine (FSM) or finite state automaton (FSA).
08-Mar-20 LD2_04 2019-2020 6
DEFINITIONS; CLASSIFICATIONSExample: It is considered an automaton that receives on the
input a string from the keyboard and set the output by 1 whenever it is recognized on the input string the word CAR. The default value of the output is 0.
Note:A – the set of characters that may appear at the input (input
space){0,1} – output spaceS0 – initial state, the automaton did not recognize any sequence
of word S1 – the state that is recognize the first character of the word
(C)S2 – the state that is recognize the second character of the word
(A)S3 – the state that is recognize the third character of the word
(R)
08-Mar-20 LD2_04 2019-2020 7
DEFINITIONS; CLASSIFICATIONS
The automaton is considered as a finite state machine because it has only 4 states.
08-Mar-20 LD2_04 2019-2020 8
DEFINITIONS; CLASSIFICATIONS Block diagram of a SLC
SLCexternal controlinputs
n
CLOCK
outputs
feedback
m
n1
08-Mar-20 LD2_04 2019-2020 9
DEFINITIONS; CLASSIFICATIONS SLC-specific signals:1) External control inputs, coming from the environment.2) Output signals, that SLC delivers the results of processing3) Feedback (reaction) signals, SLC receives information
from the output. They allow the circuit to control its activity.4) Clock signal is a very important signal that govern the
whole evolution of SLCs provided with this signal.
It's called clock (tact) signal a periodic signal where each pulse duration tends to 0.
t
t0 t1 t8t7t6 t9 t10t5t4t3t2
t 0
tt11 t12 t13
08-Mar-20 LD2_04 2019-2020 10
DEFINITIONS; CLASSIFICATIONSClassifications It is said that an input is synchronous if the value of the
input is taken into account only the clock pulse duration and between two consecutive clock pulses the input value remains unchanged.
In other words, the changes of values for synchronous inputs may affect the evolution of SLC only on clock pulse duration.
It is said that an input is asynchronous if the change of the input value may influence the evolution of SLC whatever time it occurs.
It is said that a SLC is synchronous if both evolution of inputs and transition states are governed by a clock signal.
It is said that a SLC is asynchronous if its all inputs act asynchronous, so the changing of the input value may affect the evolution of SLC no matter when that occurs.
08-Mar-20 LD2_04 2019-2020 11
DEFINITIONS; CLASSIFICATIONS If SLC has a special block for saving the state, it is said that
SLC is with extrinsic memory.
If SLC has a structure that holds the current state without being able to be highlighted in a special block for this purpose, it is said that the SLC is with intrinsic memory.
If the state Si of an SLC may be modified only by changing the value of several inputs, it is said that state Si is stable.
If the state Si of an SLC can go in the state Sk without any external influence, it is said that the state Si is unstable.
08-Mar-20 LD2_04 2019-2020 12
DEFINITIONS; CLASSIFICATIONS It is said that a sequential machine is completely
specified if for each present state and for each possible value of the inputs, they are known the output values and the next state.
It is said that a sequential machine is incompletely specified if there is at least one present state that is unknown or not important the output value and / or next state.
It is said that a SLC is deterministic if, whenever it starts from the same initial state, considered the present state and it is applied the same input sequence, is obtained the same final state and the same output sequence.
It is said that the SLC is a random (probabilistic) if it start from the same initial state Si and applying the same input sequence is obtained with probability pik the final state Sk or a specific output sequence.
08-Mar-20 LD2_04 2019-2020 13
CONTENT
Definitions; classifications Models of deterministic synchronous
SLC Methods of specifying SLC Flip-flop circuits SLC analysis
08-Mar-20 LD2_04 2019-2020 14
MODELS OF DETERMINISTIC SYNCHRONOUS SLC
The main simplifying hypotheses (assumptions) related models to be discussed are:
SH1: There are no delays in signal propagation. SH2: The memory elements form a separate block (extrinsic
memory).SH3: The output signals of the memory block materialize in
encrypted form the state of sequential machine. Each output of a memory element is a state variable.
SH4: Excitation functions (commands of memory elements) are generated by a combinational block. They are in encrypted form the next state.
SH5: The output functions are generated by a combinational block.
SH6: The clock signal acts only on the elements of memory. There are two fundamental models, Mealy model and Moore
model.
08-Mar-20 LD2_04 2019-2020 15
MODELS OF DETERMINISTIC SYNCHRONOUS SLC
Mealy model
CLC
z(t)x(t)
m n
MEMq
f
g
s(t)
CLOCK
s(t+1)
p
z(t) = f(x(t),s(t))
f: X x SZ
s(t+1) = g(x(t),s(t))
g: X x SS
08-Mar-20 LD2_04 2019-2020 16
MODELS OF DETERMINISTIC SYNCHRONOUS SLC
Moore model
g
MEM
f
x(t)
m
qp
z(t)
s(t+1)
s(t)CLOCK
n
z(t) = f(s(t))
f: SZ
s(t+1) = g(x(t),s(t))
g: X x SS
08-Mar-20 LD2_04 2019-2020 17
MODELS OF DETERMINISTIC SYNCHRONOUS SLC
Medvedev model
z(t) = s(t)
f: SS
s(t+1) = g(x(t),s(t))
g: X x SSg
MEM
x(t)
m
qp
s(t+1)
s(t)CLOCK
z(t)n
08-Mar-20 LD2_04 2019-2020 18
MODELS OF DETERMINISTIC SYNCHRONOUS SLC
Mealy model details
CLC
f
g
FF 1
FF p
FF 2
. . .
. . .
. . .
y1 (t)
yp(t)
y2 (t)
e1(t)
e2(t)
ep(t)
. . .
z1(t)
zn(t)
z2(t)x1(t)
xm
(t)
x2(t) . . .
s(t) s(t+1)
CLOCK
x(t) z(t)
x(t) – input vector
z(t) – output vector
y(t) – state vector
FF – flip-flop is amemory element withtwo stable states 0and 1
08-Mar-20 LD2_04 2019-2020 19
CONTENT
Definitions; classifications Models of deterministic synchronous
SLC Methods of specifying SLC Flip-flop circuits SLC analysis
08-Mar-20 LD2_04 2019-2020 20
METHODS OF SPECIFYING SLC By method of specifying a sequential logic scheme we
understand a formal representation of the evolution of states and outputs of SLS in SH1 conditions.
There are two main methods of representations:
1) Specification by state diagrams 2) Specification by state tables
08-Mar-20 LD2_04 2019-2020 21
METHODS OF SPECIFYING SLC
Sp Sq
xpi/zpi
Sp Sq
xpq
zp zqxpq
zp zq
SqSp
Mealy model
Moore model
Specification by state diagrams
or
08-Mar-20 LD2_04 2019-2020 22
METHODS OF SPECIFYING SLC
Specification by state tablesMealy model
08-Mar-20 LD2_04 2019-2020 23
METHODS OF SPECIFYING SLC
Specification by state tablesMoore model
08-Mar-20 LD2_04 2019-2020 24
METHODS OF SPECIFYING SLCExample:
08-Mar-20 LD2_04 2019-2020 25
METHODS OF SPECIFYING SLCExample:
08-Mar-20 LD2_04 2019-2020 26
CONTENT
Definitions; classifications Models of deterministic synchronous
SLC Methods of specifying SLC Flip-flop circuits SLC analysis
08-Mar-20 LD2_04 2019-2020 27
FLIP-FLOP CIRCUITSDefinitions; classifications It is named flip-flop (bistable multivibrator) a sequential
logic circuit having two stable states, denoted 0 and 1.
CS Latch
QS
QRR*
S*
CLOCK
asynchronousinputs
synchronousinputs
Q
Q
08-Mar-20 LD2_04 2019-2020 28
FLIP-FLOP CIRCUITS The memory element is the latch, which is an asynchronous SLC
with two stable states. R and S are the asynchronous command inputs of the latch. R represents the RESET input; by activating this input, the flip-
flop is brought to state 0, irrespective of the initial state. S represents the SET input; by activating this input, the flip-flop
is brought to state 1 irrespective of the initial state. In order for the latch to function correctly, only one of the
command inputs R and S may be active at any. As long as both commands are disabled, the flip-flop keeps its
state unaltered. Q – direct output; the logic value of this output defines the
state of the flip-flop. – complemented output; considering the fact that the two
outputs are not obtained by complementing the other one, it is possible for logic inconsistencies as to appear in some situations. Such a state is called a non determination state.
CS represents the command scheme generating the R and S commands for the latch. A combinational or sequential logic circuit can be such a command scheme.
Q
08-Mar-20 LD2_04 2019-2020 29
FLIP-FLOP CIRCUITS A flip-flop having a clock input and synchronous command
inputs is called synchronous flip-flop. A flip-flop having only asynchronous command inputs is
called asynchronous flip-flop.
Remark! A synchronous flip-flop usually has one or two asynchronous commands allowing setting of the initial state of the flip-flop. Because the asynchronous command inputs have priority in relation to the synchronous inputs, it is mandatory that all asynchronous inputs be disabled in order for the flip-flop to function synchronously.
08-Mar-20 LD2_04 2019-2020 30
FLIP-FLOP CIRCUITSAnalysis of an asynchronous flip-flop
08-Mar-20 LD2_04 2019-2020 31
FLIP-FLOP CIRCUITS
08-Mar-20 LD2_04 2019-2020 32
FLIP-FLOP CIRCUITSSynchronous flip-flops functional typesThe next four types of flip-flops are widely used:
RS type flip-flop; JK type flip-flop; D type flip-flop; T type flip-flop.
08-Mar-20 LD2_04 2019-2020 33
FLIP-FLOP CIRCUITSSynchronous RS type flip-flop (latch)
08-Mar-20 LD2_04 2019-2020 34
FLIP-FLOP CIRCUITS
08-Mar-20 LD2_04 2019-2020 35
FLIP-FLOP CIRCUITSJK type flip-flops
J
K Q
QClock
CLK
J - the set command
K - the reset command
JK (Jack Kilby - The Texas Instruments engineer who invented the integrated circuit in 1958. The JK flip-flop was named after him.(1997-07-03))
08-Mar-20 LD2_04 2019-2020 36
FLIP-FLOP CIRCUITSD type flip-flops
D
Q
QClock
CLK
08-Mar-20 LD2_04 2019-2020 37
FLIP-FLOP CIRCUITST type flip-flops
T
Q
QClock
CLK
Q(t+1)=Q(t)T
08-Mar-20 LD2_04 2019-2020 38
FLIP-FLOP CIRCUITS T type flip-flops are not produced as distinct integrate circuits
because they can be easily obtained from other types The common variant is obtained connecting together the J
and K inputs from JK flip-flop
08-Mar-20 LD2_04 2019-2020 39
FLIP-FLOP CIRCUITS There exist several implementation models for flip-flops that
commute into complementary state with each activation of the clock
08-Mar-20 LD2_04 2019-2020 40
FLIP-FLOP CIRCUITSConstructive variants of synchronous flip-flops
From the point of view of the way in which the clock signal controls the transfer of information from the synchronous command inputs to the outputs of the flip-flop, the flip-flops can be divided in three fundamental types:
with validation input (latch); master-slave; edge triggered.
08-Mar-20 LD2_04 2019-2020 41
FLIP-FLOP CIRCUITSFlip-flops with validation input The transfer of information from the synchronous command
inputs to the output is done immediately after activation of the clock input and is performed as long as the clock input remains active.
This is why it is essential, for a correct functioning, that the inputs do not modify their values while the clock input is active, assumption that in many applications is hard or even impossible to achieve.
For this reason, these flip-flops are not widely used
08-Mar-20 LD2_04 2019-2020 42
FLIP-FLOP CIRCUITSExample:
08-Mar-20 LD2_04 2019-2020 43
FLIP-FLOP CIRCUITSMaster-Slave flip-flops
Master-Slave flip-flops comprise two levels of memory elements.
The first level is the MASTER level, which takes information from the synchronous command inputs and generates command signals for the SLAVE level
08-Mar-20 LD2_04 2019-2020 44
FLIP-FLOP CIRCUITS
08-Mar-20 LD2_04 2019-2020 45
FLIP-FLOP CIRCUITSEdge triggered flip-flops
08-Mar-20 LD2_04 2019-2020 46
FLIP-FLOP CIRCUITSRemark! In technical catalogues, the Master-Slave flip-flops are
graphically represented using the symbol or next to the clock signal while the edge triggered ones are represented using the symbol or depending on the active edge.
08-Mar-20 LD2_04 2019-2020 47
FLIP-FLOP CIRCUITSD latch – VHDL model
08-Mar-20 LD2_04 2019-2020 48
FLIP-FLOP CIRCUITSD flip-flop – VHDL model
08-Mar-20 LD2_04 2019-2020 49
FLIP-FLOP CIRCUITSD flip-flop with asynchronous Clear – VHDL model
08-Mar-20 LD2_04 2019-2020 50
CONTENT
Definitions; classifications Models of deterministic synchronous
SLC Methods of specifying SLC Flip-flop circuits SLC analysis
08-Mar-20 LD2_04 2019-2020 51
SLC ANALYSIS
Analysis in the state space of synchronous SLCs
For performing analysis in the state space, the fundamental assumption is the lack of delays in the propagation of signals.
This type of analysis aims to emphasize the states and outputs evolution in case of a sequential machine whose scheme is known.
In other words, by analysing in the state space one determines the sequential machine corresponding to the given scheme.
The main steps in carrying out the analysis are:
08-Mar-20 LD2_04 2019-2020 52
SLC ANALYSISS1. Starting from the given scheme, one identifies the exits of all flip-flops and associates with each a name. These outputs materialise a state variable each.
S2. Equations of all excitation and output functions are determined.
S3. The scheme excitation table is built. This contains the values of the excitation functions for each combination of the state variables and each possible input vector.
S4. Based on the scheme excitation table and flip-flops excitation table, one generates the state transition table, containing the next state vectors for each present state and each possible input vector.
Remark! In case of the D type flip-flops, the excitation andstate transition tables are identical, so one can directly generatethe state transition table.
08-Mar-20 LD2_04 2019-2020 53
SLC ANALYSISS5. It is built the output table containing the output functions values for each combination of the state variables and possible input vector.
S6. The state transition and output tables are merged into a single table.
S7. In order to easily determine the implemented function and possible functioning anomalies, one draws the state evolution diagram.
08-Mar-20 LD2_04 2019-2020 54
SLC ANALYSISExample 1:
08-Mar-20 LD2_04 2019-2020 55
SLC ANALYSIS The excitation and output equations have the following form:
D0=y2 D1=y0 D2=y1 z=y0y2 Because the flip-flops are of type D, the state transition table
is directly obtained.(no need to write columns with the excitation functions)
It can be noticed that the obtained model is a Moore sequential machine (there is no external command input)
08-Mar-20 LD2_04 2019-2020 56
SLC ANALYSIS Evolution of the scheme:
000 111
011
101
110
100
010
001
0 0
1
0
1
1
0
1
C1 C2
One can notice, by analysing the diagram, that:a) There are two cycles (C1 and C2) that could be the useful
cycles in the evolution of the analysed sequential machine. b) There are two trap states 000 and 111 the sequential machine
can’t leave without external input. To eliminate the possibility of blockage in one of the two trap
states and to select the useful cycle C1, it is necessary to introduce an initialisation command.
08-Mar-20 LD2_04 2019-2020 57
SLC ANALYSIS The new scheme with asynchronous initialisation by means of
the INIT# signal
Conclusion: this scheme represents a modulo 3 frequency divider, irrespective of the chosen useful cycle. Only the filling factor varies, in case of the output signal.
08-Mar-20 LD2_04 2019-2020 58
SLC ANALYSISExample 2:
08-Mar-20 LD2_04 2019-2020 59
SLC ANALYSIS The excitation and output equations are:J0= K0=1 J1=y0 K1= z=
1y 0y
1010 yyyy
0111
10
00 1
0
01
08-Mar-20 LD2_04 2019-2020 60
SLC ANALYSIS It results:a) The scheme presents a single functioning cycle which is
obviously the useful cycle.b) The scheme presents the property of self loading, because
there are no trap states and the useful cycles are reached from any state. Nonetheless, for control over the scheme at the initialisation, it is recommended to have an asynchronous initialisation command (INIT#) that changes the state of the scheme into initial state 00.
c) During the useful cycle, for each group of three clock signal pulses it is generated a single output pulse, so this scheme too represents a modulo 3 frequency divider.
08-Mar-20 LD2_04 2019-2020 61
SLC ANALYSIS
0111
10
00 1
0
01
INIT#
08-Mar-20 LD2_04 2019-2020 62
SLC ANALYSIS
Temporal analysisTemporal elements specific to the flip-flops It is necessary to take into considerations a few elements
specific to the flip-flops and presented in the temporal diagram corresponding to CD74HC74, CD74HCT74 circuits.
08-Mar-20 LD2_04 2019-2020 63
SLC ANALYSIS The emphasised elements have the following meaning:tr – rise time of the clock signal;tf – fall time of the clock signal;tWL – clock signal duration on low level;tWH – clock signal duration on high level;tW – clock pulse width tW=tWL+tWH;tTLH, tTHL – transition times of output signal;tPLH, tPHL – propagation delay times of output signal;tSU(H), tSU(L) – minimal setup times for the data signal before
clock signal activation;tH(H), tH(L) – minimal hold times for data signal after clock signal
deactivation;tREM – minimal removal time of reset/set signals before clock
signal activation.
08-Mar-20 LD2_04 2019-2020 64
SLC ANALYSIS
SN74ls74 edge-triggered flip-flop
08-Mar-20 LD2_04 2019-2020 65
SLC ANALYSIS
J,K
tsu th
CP
SN7473 pulse-triggered flip-flop
08-Mar-20 LD2_04 2019-2020 66
SLC ANALYSISSimplified temporal analysis To manually realise the temporal analysis for an SLC, the
following simplifying hypotheses are considered:SH1. All components of the same type induce identical delays.SH2. All signals commute simultaneously.SH3. tPHL=tPLH.SH4. tSU=tH=0. As in the case of CLCs, the analysis is performed by means of
time diagrams. In case of synchronous SLCs it is recommended to place the
set asynchronous and clock signals in the upper part of the diagram.
The temporal analysis is of fundamental importance in case of asynchronous SLCs.
Before performing the actual analysis, the S1 and S2 steps presented at the state space analysis must be performed.
08-Mar-20 LD2_04 2019-2020 67
SLC ANALYSISExample:
08-Mar-20 LD2_04 2019-2020 68
SLC ANALYSIS
0
CLOCK
INIT#
y1
y0
y2
0 66666777731 54444445555576 22233337 22 2
t
t
t
t
t
tz
08-Mar-20 LD2_04 2019-2020 69
SLC ANALYSIS
QUESTIONS?
Top Related