Jan. 6, 2006 VLSI Design '06 1
On the Size and Generation of Minimal On the Size and Generation of Minimal N-Detection TestsN-Detection Tests
Kalyana R. KantipudiVishwani D. Agrawal
Department of Electrical and Computer EngineeringAuburn University, AL 36849 USA
19th International Conference on VLSI Design, Hyderabad, January 3-7, 2006
Jan. 6, 2006 VLSI Design '06 2
Motivation for This Work
• N-detection vectors are known to have a higher coverage of “real defects”.
• Increased test length for N-detection tests directly impacts testing cost.
• Efficient ways to find minimal N-detection test set are still evolving.
• There is no proven lower bound on the size of the N-detection vectors.
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Outline
• Introduction
• Theoretical minimum for an N-detection test set
• ILP based N-detection approach
• Results
• Conclusions
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Minimal Single-Detection Tests• Independence graph: Nodes are faults and edges represent pair-
wise independence relationships. Example: c17[1].• An Independent Fault Set (IFS) is a maximal clique in the graph.• Size of IFS is a lower bound on test set size (Akers et al., ITC-87)
1 2 3 4 5
6 7 8 9 1 0
11
1 2 3 4 5
6 7 8 9 1 0
11
1
4 2
5So, the minimal test set for these 11 faults is ‘4’.
[1]A. S. Doshi and V. D. Agrawal, “Independence Fault Collapsing,” Proc. 9th VLSI Design and Test Symp., Aug. 2005, pp. 357-364.
Jan. 6, 2006 VLSI Design '06 5
Theoretical Minimum of an N-Detection Test Set
• Theorem 1: The size of the largest clique in the independence graph is a lower bound on single detection test set size [Akers et al. ITC-87].
• Theorem 2: A lower bound on the size of the N-detection test set is N times the size of the largest clique in
the independence graph.
1
N test Vecs
5
N test Vecs
2
N test Vecs
4N test Vecs
So, at least 4N vectors are needed to detect each fault ‘N’ times.
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4-Bit ALU: N-Detection Vectors
0
100
200
300
400
500
600
700
Vec
tors
1 2 3 4 5 6 7 8 9 10 20 40 50
N
Atalanta vectors Min. ILP vectors Lower bound
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ILP Based N-Detection Approach
• Use any ATPG to obtain a set of k vectors that detects every fault at least M times, where M N.
• Use Diagnostic fault simulation to get the vector subset Tj for each fault j.
• Assign integer variable ti to ith vector such that,
ti=1 if ith vector included in the minimal set ti=0 if ith vector not included
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Objective and Constraints of ILP
Objective:
k
1iitimize min
Constraints:
jfaults,Nt jTvectori
ji
Nj is the multiplicity of detection for the jth fault.
Nj can be selected for individual faults based on some criticality criteria or on the capability of the initial vector set.
Theorem 3: When the minimization is performed over an exhaustive set of vectors, an ILP solution that satisfies the above expressions is a minimum N-detection test set.
Jan. 6, 2006 VLSI Design '06 9
Minimal 3-Detection Test Set for c17
• ATALANTA generates 4 test sets (M = 4); repeated vectors are removed.
• HOPE is used to perform diagnostic fault simulation on the vector set.
• Simulation information is used to create constraints for the ILP.
sa1
x
sa1
x
sa1
x
sa1
x
sa1
x
sa1
x
sa1
x
sa1
xsa1
x
sa1
xsa1
xsa1
x
sa1
x
sa1
x
sa1
x
X
sa0
X
sa0
X
sa0
X
sa0
X
sa0sa1
x
sa1
x1511
8
21
12
97
6
54
314
13 12
10 1617
18
19
20
22
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Constraint Generation
• Fault 1 is detected by the vectors 1, 2, 15, 16, 22, 24.• Fault 2 is detected by the vectors 1, 2, 3, 4, 5, 6, 7, 8, 9,
15, 16, 22, 24, 28, 29..... so on ....
Now the Objective is:
29
1iitimize min
jfaults,3t
ji Tvectori
and the constraints are:
Constraint_‘F1’: t1+t2+t15+t16+t22+t24 ≥ 3
Constraint_‘F21’: t13+t15+t16+t19+t23+t24 ≥ 3
Jan. 6, 2006 VLSI Design '06 11
Minimum Test Sets from ILP
• The minimum 3-detect test set size is 13 (lower bound = 12).• Vectors are: 2, 6, 7, 11, 14, 15, 16, 17, 18, 21, 23, 24, 28.
Suppose fault ‘21’ is a critical fault to be detected 5 times:
Constraint_‘F21’: t13+t15+t16+t19+t23+t24
• The minimum test set given by ILP has 14 vectors.• Vectors are: 2, 6, 7, 11, 12, 13, 14, 15, 16, 17, 18, 19, 23, 28.
For large circuits the change in test size is negligible.For large circuits the change in test size is negligible.
35
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15-Detection Tests for Benchmarks
0
500
1000
1500
2000
2500
Te
st
se
t s
ize
Lower Bound
Present Work
Previous Result
Hamzaoglu and Patel, IEEE-TCAD, Aug. 2000Lee, Cobb, Dworak, Grimaila and Mercer, Proc. DATE, 2002
Jan. 6, 2006 VLSI Design '06 13
CPU Time for 15-Detection Tests
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
CP
U s
ec
on
ds
Present Work
Previous Result
Ultra-5, * Ultra-10, ** Sun Fire 280R
Lee, Cobb, Dworak, Grimaila and Mercer, Proc. DATE, 2002
Jan. 6, 2006 VLSI Design '06 14
Classifying Combinational Circuits
F1 X
F3 X
F2X
F4 X
Primary Inputs
PO1
PO3
PO4
PO2
TYPE - I: TYPE – II:
c499, c1355, c1908 c880, c2670, c7552
Output cones have large overlap.
Any vector detecting a fault F2 will have high probability of detecting other faults, say fault F3 or F1.
Non-overlapping output cones.
Any vector detecting a particular fault, will have very less probability of detecting any other fault.
`
Primary Inputs
PO1
PO2
PO3
F1X
X F2
XF3
F4X
Jan. 6, 2006 VLSI Design '06 16
Conclusion
• The theoretical lower bound on the N-detection tests is useful in assessing the minimality of such tests.
• ILP is an effective method for minimizing tests, though further improvement is possible.
• The formulation of ILP allows custom selection of multiplicity of detection for individual faults.
• Contributions of this work:– Theoretical lower bound on N-detection tests.– ILP method for deriving minimal N-detection tests.
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