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International Technology Roadmap
for Semiconductors
International Technology Roadmap
for Semiconductors
Assembly and Packaging2007
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Assembly and Packaging Roadmap 2007 Participants
Assembly and Packaging Roadmap 2007 Participants
W. R. Bottoms, Chair William Chen, Co-chairJohn Hunt
Mike Hung, Ph.D
Sreenivasan Koduri
Li Li
Rongshen Lee
Dongho Lee
David Love
Mike Lamson
HeeSoo Lee
Choon Heung Lee
Sebastian Liau
Hongwei Liang
Weichung Lo
Michitaka Kimura
Debendra Mallik
Lei Mercado
Stan Mihelcic
Abhay Maheshwari
Gary Morrison
Jean-Pierre Moscicki
Hikari Murai
Rajen Murugan
Manoj Nagulapally
Hirofumi Nakajima
Keith Newman
Luu Nguyen
Dick Otte
Masashi Otsuka
Bob Pfahl
Ralf Plieninger
Klaus Pressel
Marc Petersen
Gilles Poupon
Charles Richardson
Bernd Roemer
Bill Reynolds
Bidyut Sen
Yong-Bin Sun
Coen Tak
Henry Utsunomiya
Shoji Uegaki
David Walter
Lawrence Williams
M. Juergen Wolf
Jie Xue
Zhiping Yang, Ph.D.
Edgar Zuniga
Seiichi Abe
Joseph Adam
Mudasir Ahmad
Bernd Appelt
Ivor Barber
Muhannad Bakir
Mario Bolanos-Avila
Craig Beddinfield
Kwang Yoo Byun
Carl Chen
Chi Chi Chang
Bob N. Chylak
Sonjin Cho
Jason Cho
Chetan Desai
Kishor Desai
Darvin Edwards
John T. "Jack" Fisher
Darrell Frear
George Harman
Ryo Haruta
Harry Hedler
Harold Hosack
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ITRS A&P Chapter OrganizationITRS A&P Chapter Organization
This Chapter is organized in eight major sections: Difficult Challenges Single Chip Packaging Wafer Level Packaging System-in-Package Packaging for Specialized Functions Advanced Packaging Technologies Equipment Requirements Cross-Cut Issues
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Packaging Technology ChallengesPackaging Technology Challenges
Interconnect ScalingConnect Si features (nm) to circuit board features (cm)
Power DeliveryEfficiently deliver
Power to enable high speed Si performance
Power RemovalEfficiently duct away
dissipated power
High Speed SignalingFacilitate distortion –
free signaling
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Assembly and Packaging Assembly and Packaging
Difficult Challenges▬Pb free transition presents cost, reliability and process
compatibility problems that are not yet fully resolved▬A new generation of DFM & DFT solutions will be required
for complex SiP, SoC 3D packaging▬Thermal issues for complex 3D packaging▬Stress induced changes in electrical properties for very thin
die ▬Reliability for through wafer vias and die layer bonding▬Warpage control for stacked die▬ Interconnect for nano-scale structures▬Handling of ultra thin die and self assembly for very small
die
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The Pace of Change in Packaging is Accelerating
The Pace of Change in Packaging is Accelerating
As traditional CMOS scaling nears it natural limits other technologies are needed to continue progress
This has resulted in an increase in the pace of innovation. Many areas has outpaced ITRS Roadmap forecasts. Among
these are:▬ Wafer thinning and handling of thinned wafers/die▬ Wafer level packaging▬ Incorporation of new materials▬ 3D integration
The consumerization of electronics is the primary driving force.
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Consumer Markets Drive InnovationConsumer Markets Drive Innovation
Consumers now drive more than half of integrated circuit revenue
Assembly and Packaging technology is a primary differentiator for consumer electronics
These factors are driving an unprecedented pace of innovation in:▬New Materials ▬New Technologies▬New Systems Integration architecture
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New Packaging TechnologiesNew Packaging Technologies
Thinned wafers 3D systems integration Wafer level packaging Bio-chips Integrated optics Embedded/integrated active and passive devices MEMS Flexible (wearable) electronics Printable circuits
▬ Semiconductors▬ Light emitters▬ RF▬ Interconnect
Texflex embroidered interconnects (Fraunhofer IZM)
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Wafer ThinningWafer Thinning
Table 102a&b Thinned Silicon Wafer Thickness 200 mm/300 mm
Year of Production 2007 2008 2009 2010 2011 2012 2013 2014 2015
Min. thickness of thinned wafer (microns)(general product)
50 50 50 50 45 40 40 40 40
Min. thickness of thinned wafer (microns)(For extreme thin package ex. Smart card)*
20 20 15 15 10 10 10 10 8
It was easier than we thought.
Handling of Thinned wafers and die will be the limiting factor
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Wafer Level PackagingWafer Level Packaging
One of the fastest growingpackaging architectures
WLP offers portable consumer products :▬ inherent lower cost▬ improved electrical
performance▬ lower power requirements▬Smaller size
Several architectural variations are in use today
Wafer level CSP in the simplest structure Wafer level CSP with copper post and resin mold
Opto wafer level CSP with tapered TSV interconnection
Opto wafer level CSP with beam lead metallurgy
IPD embedded silicon substrate
Build-up substrate through wafer level fabrication
Thin Chip Integration (Embedded device in polymer dielectric)
embedded Wafer Level Ball Grid Array
Stacked devices with Through Silicon Via´s (TSV)
Processor
High-Capacity Memory
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Applications for New MaterialsApplications for New Materials
In this decade most if not all packaging materials will change due to changing functional and regulatory requirements▬ Bonding wire▬ Molding compounds▬ Underfill▬ Thermal interface materials▬ Die attach materials▬ Substrates▬ Solder
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New MaterialsNew Materials
Cu interconnect Ultra Low k dielectrics High k dielectrics Organic semiconductors Green Materials
▬ Pb free▬ Halogen free
Many are in use today Many are in development
Nanotubes Nano Wires Macromolecules Nano Particles Composite materials
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Through Silicon Vias (TSV)Through Silicon Vias (TSV)
Temorarily Carrier Bonding
Temorarily Carrier Bonding
ThinningThinning
Plating (Cu and Solder)Plating (Cu and Solder)
Via-First Approach
Backside UBM/RDL-Plating
Backside UBM/RDL-Plating
Sequential ThinningSequential Thinning
Temorarily Carrier Bonding
Temorarily Carrier Bonding
Via-Last Approach
Via EtchVia Etch
Via Etch or DrillVia Etch or DrillVia Etch or Drill
Substratefront (device side)
Silicon devicefront (device side)
Substratefront (device side)
Silicon devicefront (device side)
Substratefront (device side)
Silicon devicefront (device side)
Via-FillingVia-Filling
Via-Filling + RDL-PlatingVia-Filling + RDL-Plating
* Tested FE-Si-Device
TSVTSV--ProcessProcess FlowFlowPostPost--CMOSCMOS--ProcessProcess**
A Key technology for both wafer level packaging and 3D
integration
From front side From back side
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System in Package (SiP)
“The next step in Assembly and Packaging: Systems Level Integration”
System in Package (SiP)
“The next step in Assembly and Packaging: Systems Level Integration”
Introduction & Motivation The basic elements generic to all SiP System level
integration applications will be defined.
Examples will be used from various application areas to show how the basic elements are incorporated into these applications.
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SiP: Multi-level System IntegrationSiP: Multi-level System Integration
Source: Fraunhofer IZM
Packages may include:Sub-system packages Stacked thin packages including WLP, passives and active chipsMechanical, optical and other non electrical functionsComplete systems or sub-systems with embedded componentsBare die
SiP may include SoC and other traditional packages
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Categories of SiPCategories of SiP
Horizontal P lac ement
S tac kedS truc ture
Interpos er T ype
Interpos er-les s T ype
Wire B onding T ype F lip C hip T ype
Wire B onding T ype
Wire B onding +F lip C hip T ype F lip C hip T ype
T erminal T hroug h Via T ype
E mbedded S truc tureC hip(WL P ) E mbedded + C hip on S urfac e T ype
3D C hip E mbeddedT ype
WL P E mbedded + C hip on S urfac e T ype
PiP, PoP and more
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xx yyzz
ComputingComputing
CommunicationsCommunications
MemoryMemory
Packagexx yyzz
ComputingComputing
CommunicationsCommunications
MemoryMemory
xx yyzz
xx yyzz
ComputingComputing
CommunicationsCommunications
MemoryMemoryComputingComputingComputingComputing
CommunicationsCommunicationsCommunicationsCommunications
MemoryMemoryMemoryMemory
Package
3D Packaging increases Performance Density and enables system level
integration
3D Packaging increases Performance Density and enables system level
integrationNew System in Package (SIP) New System in Package (SIP)
solutions enables rapid solutions enables rapid integration of different integration of different
functionsfunctions
Thru-Si via Stacking
SibleySpacer
256M NAND
Sibley
Wire bonded stacked die
Small form factor for Small form factor for ultramobile PCs, hand-helds, ultramobile PCs, hand-helds,
phones & other consumer phones & other consumer electronicselectronics
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3D Integration3D Integration
Table 101 System-in-a-Package Requirements
Year of Production 2007 2008 2009 2010 2011 2012 2013 2014 2015
Number of terminals—low cost handheld
700 800 800 800 800 800 800 800 800
Number of terminals—high performance (digital)
3050 3190 3350 3509 3684 3860 4053 4246 4458
Number of terminals—maximum RF 200 200 200 200 200 200 200 200 200
Low cost handheld / #die / stack* 7 8 9 10 11 12 13 14 14
high performance / die / stack 3 3 3 4 4 4 5 5 5
Low cost handheld / #die / SiP 8 8 9 11 12 13 14 14 14
high performance / #die / SiP 6 6 6 7 7 7 8 8 8
Minimum TSV pitch 10.0 8.0 6.0 5.0 4.0 3.8 3.6 3.4 3.3
TSV maximum aspect ratio** 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
TSV exit diameter(um) 4.0 4.0 3.0 2.5 2.0 1.9 1.8 1.7 1.6
TSV layer thickness for minimum pitch 50 20 15 15 10 10 10 10 8
Minimum component size (micron) 1005 600x300 600x300 400x200 400x200 400x200 200x100 200x100 200x100
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3D System Integration & Packaging3D System Integration & Packaging
e-CUBE
e-cube application
layer(s)
e-cube radio
e-cube Power
Antenna
rf circuit
Processing unit
Radio digital
baseband
Sensor Function
Power Management
Energy Scavenging(e.g. vibration,solar)
Power storage
Stacked functional Layers with TSV and /or flexible polymer Interposer
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3D Stacked Die Package3D Stacked Die Package
Samsung TSV
35 micron thick
TSV of Tezzaron
TSV of Ziptronix
Elpida (Poly-Si TSV)
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Table 101 System-in-a-Package Requirements Year of Production 2015 2016 2017 2018 2019 2020 2021 2022
Low cost handheld / #die / stack* 14 15 15 16 16 17 17 18high performance / #die / stack 5 6 6 6 7 7 7 8Low cost handheld / #die / SiP 14 15 15 16 16 17 17 18high performance / #die / SiP 8 9 9 9 10 10 10 11
Stacked die SiP packages2014 through 2020
Stacked die SiP packages2014 through 2020
Limited by thermal density
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● ● ● ● ● ● ● ●
● ● ● ●
Substrate thickness: 0.16
Ball pitch: 0.8 mm
1.0
Mold resin thickness on top of die: 0.10 mm
Die attach thickness
0.015
TSV
0.025mm
Embedded
Typical SiP in 2010Typical SiP in 2010
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Interconnect Challenges for Complex SiPs
Interconnect Challenges for Complex SiPs
Evolutionary and revolutionary interconnect technologies are needed to
enable the migration of microsystems from
conventional state-of-art to 3D SiP.
New circuit elements and components place expanded demands on the environment
provided by the package
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Interconnect Requirements may be satisfied by Optical Wave Guide
Solutions
Interconnect Requirements may be satisfied by Optical Wave Guide
Solutions
WaveguideSolder bump
Die
Mirror
VCSEL/PD
Substrate
Polymer pin
SubstrateSubstrate
Lens
Substrate Substrate
Fiber
Board-level integrated optical devices Fiber-to-the-chip
Quasi free-space
optical I/O
Lens assisted quasi free-space optical I/O
Surface-normal optical waveguide I/O
Optical
source/PD
Examples of guided wave optical interconnects
for chip-to-chip interconnection.
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Low k Dielectric will Require Low Stress IO Interconnections
Low k Dielectric will Require Low Stress IO Interconnections
Si die Si die
Innovations in low stress electrical I/O can potentially eliminate the need for underfill
reducing cost and processing complexity as I/O density rises.
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SiP presents new challenges for Thermal management
SiP presents new challenges for Thermal management
High performance and form factor reduction generate high thermal density
Heat removal requires much greater volume than the semiconductor▬ Increased volume means increased wiring length causing
higher interconnect latency, higher power dissipation, lower bandwidth, and higher interconnect losses
▬ These consequences of increased volume generates more heat to restore the same performance
ITRS projection for 14nm node▬ Power density >100W/cm2 ▬ Junction to ambient thermal resistance <0.2degrees C/W
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Thermofluidic Heat Sinks may be the Solution
Thermofluidic Heat Sinks may be the Solution
Conventional
thermal Interconnects
Back-side integrated
fluidic heat sink and
Back and front-side
inlets/outlets
Thermal interface Material
Back-side integrated
fluidic heat sink using
TIM and inlets/outletstube
Die
fluidic I/O
Examples of thermofluidic cooling integration with CMOS technology
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SummarySummary Packaging innovation enables
“More than Moore” ▬ 3D packaging technologies▬ Equivalent scaling through functional diversity
Consumer market demands drive innovation in packaging▬ Size, power, cost, performance, time to market
New materials and architectures are required to meet today’s market demand but will enable many future advances in packaging
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