EEE 533 Semiconductor Device and Process Simulation
Introduction to Silvaco ATHENA Tool and
Basic Concepts in Process Modeling
Part - 2
Instructor: Dragica Vasileska
Department of Electrical Engineering
Arizona State University
EEE 533 Semiconductor Device and Process Simulation
3. Description of the diffusion process
� The diffusion process is a main step in the fabrication of integrated circuits.
� Some characteristic features of the diffusion process are listed below:
� temperature: 900 °C to 1300 °C
� type of diffusion: selective and non-selective
� amount of diffused impurities:determined via solid-solubility limits
Solid-solubility of impurity elements in silicon
EEE 533 Semiconductor Device and Process Simulation
� The process of diffusion is described via the two Fick’s laws:
( )
iiti
citiiitiii
Gt
C
CCZCD
=⋅∇+∂
∂
−µ−∇−=
J
EJ
Ji � flux of diffusing species
Cti � total concentration
Cci � concentration of electrically inactive impurities
Zi � charge state of the i-th particle
Di � diffusion coefficient
µi � mobilityE � electric field
Gi � net generation term which equals zero for impurity
diffusion
EEE 533 Semiconductor Device and Process Simulation
� The electric field term that appears in the expression describing first Fick law should, in principle, be calculated by solving Poisson’s equation, of the form:
where the net concentration of ionized impurities is:
� For simplicity, the potential, and therefore, the electric field are calculated using charge-neutrality, which gives:
( )AD NNnpe
−+−ε
−=ψ∇2
( )∑ −−=i
citii CCZC
=ψ −
iT
n
CV
2sinh 1
EEE 533 Semiconductor Device and Process Simulation
� The magnitude of the diffusion coefficient depends upon the concentration of defects in the crystal
� There are four different types of defects that can be observed in a crystal:
� point defects
� line defects
� area defects
� volume defects
Silicon atoms
Impurity on substitutional siteVacancy
Silicon interstitial
Impurity on interstitial site
Frenkeldefect
Point defects description
EEE 533 Semiconductor Device and Process Simulation
� The position of the interstitial voids in a zincblende lattice is schematically illustrated in the figure below:
EEE 533 Semiconductor Device and Process Simulation
� Listed below are the characteristic features of vacancies:
� Vacancy is a missing atom in the crystalline lattice
� The energy of formation of a vacancy equals 2.3 eV (to break four bonds), and the energy of migration is 0.18 eV
� Since divacancy requires breaking of six covalent bonds, the energy of formation of divacancy is only slightly higher, and is, therefore, commonly encountered
� The # of vacancies per unit volume is given by:
� Since the presence of a vacancy results in four unsatisfied bonds, vacancies are of an acceptor-type with energy levels:
(EV + 0.71 eV) for V-
(vacancy)
(EV + 1.0 eV) for V= (divacancy)
−=
Tk
ENn
B
ss exp
N � total # of atoms in a crystal(5×1022 cm-3)
Es � energy of formation
ns � density of vacancies
EEE 533 Semiconductor Device and Process Simulation
� The characteristic features of interstitials are listed below:
� Interstitial is a Si atom located on one of many interstitial sites
� The energy of formation of an interstitial equals 1.1 eV
� The # of interstitials is calculated in the same manner as the # of vacancies
� Interstitials have four valence electrons that can be donated to the conduction band, and are of a donor-type, with energy level
(EC - 0.91 eV) for V+
� Some characteristic properties of Frenkel pairs:
� The energy of formation of a Frenkel pair is comparable to the energy of formation of an interstitial
� The # of Frenkel pairs is calculated from:
−=
Tk
ENn
B
ff
2exp Ef � energy of formation
of a Frenkel defect
EEE 533 Semiconductor Device and Process Simulation
� The diffusion process in a semiconductor occurs via vacancies and interstitials, which is schematically shown in the figures below:
� The magnitude of the diffusion coefficient is of the following form for the two dopant concentration limiting cases:
(a) low concentration:
(b) high concentration:
−=
Tk
EDD
B
aexp0 Ea � activation energy
+=−
++==−−
+
+
+=
⋅+⋅+⋅+=
ii
ii
ii
i
iiii
Dn
pD
n
nD
n
nD
VDVDVDDD
20
0
Vacancydiffusion
Interstitialdiffusion
EEE 533 Semiconductor Device and Process Simulation
� For doping concentrations close to the solid-solubility limit, the impurities start to cluster and stop diffusing:
� The relationship between the total Ct and the electrically inactive concentration Cc due to clustering effect, is found by solving the following equation:
� The clustering effect is important when the doping concentra-tion is on the order of 3×1020 cm-3 for arsenic.
( ) cm
ctc CkdCCkcm
t
C⋅−−⋅⋅=
∂
∂
Cluster size
Clustering rate Declustering rate
EEE 533 Semiconductor Device and Process Simulation
� Under the assumption of zero electric field and constant diffusion coefficient, one needs to solve the following differential equation using, for example, Laplace transform:
� Depending upon the type of boundary conditions, two possible solutions exist:
� diffusion from an infinite source� diffusion from a finite source
Diffusion from an infinite source
� The initial and boundary conditions for this case are:
� This leads to the following form of the solution:
2
212
x
CD
t
CCD
t
C D
∂
∂=
∂
∂→∇=
∂
∂
0)0,0()0,0( ==>=≥= txCandCtxC s
,2
),(
=
Dt
xerfcCtxC s Dt � characteristic length
EEE 533 Semiconductor Device and Process Simulation
Diffusion from a finite source
� Using a predeposition process, a certain ammount of impurity atoms is added in a very narrow region near the surface. Then the sample is heated and diffusion process takes place.
� The initial and boundary conditions for this case are:
� This leads to the following form of the solution:
.),(000,0
constdxtxCQandx
C
tx
=∫==∂
∂ ∞
≥=
−
π=
Dt
x
Dt
QtxC
4exp),(
2
C/Cs
x
Dt
Infinitesource
C/Cs
x
DtFinite
source
EEE 533 Semiconductor Device and Process Simulation
� Junction depth determination
During the diffusion of, for example, acceptor-type impurities, the net acceptor concentration equals to:
The junction depth is, then, given by the following expressions:
(a) Infinite source:
(b) Finite source:
DAnetA NtxNtxN −= ),(),(
),( txN
x
⋅= −
0
12N
NerfcDtx D
j
π=
DtN
QDtx
Dj ln2
.constND =
),( txN A
p-type n-type
jx
EEE 533 Semiconductor Device and Process Simulation
� Lateral diffusion
The previously described model accurately describes the diffusion process, except near the edges of the mask windows, where impurities also diffuse laterally.
� The ratio of the lateral to vertical penetration is about 75% for concentration independent diffusivities and about 65% to 70% for concentration dependent diffusivities.
� Since electric field intensities are higher for cylindrical and spherical junction regions, avalanche breakdown voltages will be substantially lower when compared to the plane junction case.
2D - diffusion profileshowing the lateral diffusion
EEE 533 Semiconductor Device and Process Simulation
� Impurity redistribution during subsequent oxidation
Dopant impurities near the silicon surface are redistributed during the subsequent thermal oxidation process. The redistribution process depends upon several factors listed below:
� The magnitude of the segrega-tion coefficient:
� The magnitude of the impurity diffusivity in the oxide
� The consumption of the underlying Si layer
2SiOin
Si in
C
Ck =
EEE 533 Semiconductor Device and Process Simulation
� Diffusion constant determination
Decribed below are two methods for the experimental deter-mination of the diffusion constant:
(A) pn-junction method
The requirement here is to make one or more diffusions into semicon-ductors with known background concentration and opposite impurity type. After determining the junction depth, one gets:
(B) Boltzmann-Matano method
This method is used when the depth-dependence of the doping profile is obtained, for example, via SIMS technique. Then, for initially undoped substrates, one has:
( )( ) ( )[ ]
−
≈⇒
=
=
2112
22
21
202
101
ln4
1
2
2
jBjB
jj
jB
jB
xNxN
xx
tD
DtxerfcNN
DtxerfcNN
∫−==
1
102
1 N
NN xdNdN
dx
tD
The diffusion constant is determinedfrom the knowledge of the slope at arbitrary depth and the total # of dif-fused impurities.
EEE 533 Semiconductor Device and Process Simulation
� Most important statements for ATHENA diffusion simulation
DIFFUSE statement
� This statement initiates a time temperature step for oxidation, silicidation and diffusion of impurities
� Important parameters that can be specified here are:
� Surface impurity concentration via: C.ARSENIC, C.BORON, C.ANTIMONY, etc.
� CONTINUE � continuation of the diffusion process
� DRYO2, WETO2, NITROGEN, AMMONIA, ARGON� gas present in the furnace (one type is specified)
� F.02, F.H2, F.H20, F.N2 and F.HCL � flow-rates
� HCL.PC � percentage of HCL in the oxidant stream
� PRESSURE � partial pressure of active species
� TEMPERATURE � furnace temperature
� T.FINAL, T.RATE � final T and ramp-rate
� TIME � amount of time spent in the furnace
EEE 533 Semiconductor Device and Process Simulation
METHOD statement
� This statement is used to set flags for selecting various mathematical algorithms used in the simulation and to select the desired diffusion model complexity
� Important parameters that can be specified here are:
� VACANCIES, INTERSTIT, ARSENIC, .., OXIDANT, VELOCITY, TRAPS, PSI, etc. � parameters used tospecify a single impurity, trap or a potential
� FERMI � the defects are assumed to be a function of the Fermi level only
TWO.DIM � full time-dependent transient simula-tion has to be performed
STEADY � defects are in steady-stateFILL.CPL � full coupling between defects and dopants is included
� CLUSTER.DAM � Stanford cluster model enabled
� HIGH.CONC � doping concentration dependent point defect recombination model terms enabled
EEE 533 Semiconductor Device and Process Simulation
4. Description of the oxidation process
� The oxidation process involves thermal growth of SiO2 or deposition of silicon nitride
� The deposited SiO2 layer can be used for the following purpose:
� diffusion mask for selective dopant diffusion� pn-junction protection from atmospheric influence� dielectric layer in MOS-transistors (gate oxide)� isolation between transistors fabricated on the same
chip (field oxide)
� Some figures of merit for the oxidation process:
� oxidation temperature: 900 °C to 1200 °C
� typical gas flow rate: 1 cm/sec
� depending upon the ambient, one can have:
(a) Dry oxidation process: Si + O2 � SiO2
(b) Wet oxidation process: Si + 2H20 � SiO2 + 2H2
EEE 533 Semiconductor Device and Process Simulation
� During the oxidation process, the underlying Si material is consumed:
Si thickness = 0.44 × (oxide thickness)
� the basic structural unit of thermally grown SiO2 is shown in the figure below:
(a) Basic structural unit of SiO2
(b) Quartz crystal lattice(c) Amorphous structure
EEE 533 Semiconductor Device and Process Simulation
� The kinetics of thermal oxidation is described via the Deal-Grove model that is given below:
F1 = h(C*-C0) - flux of oxidant from the bulk of the gasto the gas-oxide interface
C* = oxidant concentration in the bulkC0 = oxidant concentration at gas/oxide interfaceh = gas-phase mass transfer ratio
F2 = D(C0-Cs)/Xox - flux across the oxide
Cs = oxidant concentration at the SC/oxide interfaceD = diffusion coefficient
F3 = ksCs - oxide/SC oxidation reaction
ks = chemical surface-reaction coefficient
F1 = F2 = F3 = N1dXox/dt
N1 = # of oxidant molecules incorporated into unit volume 0 Xox x
C(x)
C0
Cs
F1
F2 F3
silicon
EEE 533 Semiconductor Device and Process Simulation
� The analytic solution of the kinetic equations gives:
where:
(a) short-time limit behavior:
- the linear rate constant B/A varies as exp(-Ea/kBT) with activation energy Ea of about 2 eV
- B/A has orientation dependence
(b) long-time limit behavior:
- The activation energy for the parabolic rate constantequals to: Ea(dry)=1.24 eV and Ea(wet)=0.71 eV
- does not exhibit orientation dependence
−+
+= 1
4)0(21
2)(
2
2
A
Bt
A
XAtX ox
ox
1
*2,
112
N
DCB
hkDA
s
=
+=
( ) )(/)( τ+≈ tABtXox
BttXox ≈)(
EEE 533 Semiconductor Device and Process Simulation
� For thin oxides, the differential equation that describes the oxide growth is modified to:
� In the SSUPREM4 implementation of the oxidation process, one can distinguish between:
� analytical oxidation models� numerical oxidation models
(A) Analytical oxidation models
The initial silicon surface must be planar. Also:
B/A = L0LpLHClLbaf L0 = intrinsic linear oxidation rate
Lp = pressure dependent coefficient
LHCl = chlorine dependent coefficient
Lbaf = doping-dependent coefficient
B = P0PpPHCl same meaning as above
−
−=+
+=
L
ox
B
Ethth
ox
ox
Th
X
Tk
ThThRR
XA
B
dt
dXexpexp ,
20
EEE 533 Semiconductor Device and Process Simulation
(B) Numerical oxidation models
� Three numerical models have also been implemented in SSUPREM4:
VERTICAL, COMPRESS and VISCOUS
� In all three models, the oxidation equations are solved to obtain the growth rate at each point of the Si/SiO2 inter-face
� COMPRESS and VISCOUS solve:
µ∇2V = ∇P, where: ∇P = hydrodynamic pressuregradient
V = velocity
µ = E/(2+2ν) = viscosity
� The VISCOUS model is more advanced than COMPRESS, since it incorporates strain into the problem.
EEE 533 Semiconductor Device and Process Simulation
� Most important statements for oxidation simulation
OXIDE statement
� All parameters related to the description of the oxidation process are specified here
� Important parameters include:
� DRY02, WET02 � type of oxidation process for which specific coefficients apply
� LIN.L.0, LIN.L.E, LIN.H.0, LIN.H.E, L.BREAK �
specification of linear-rate coefficient B/A� PAR.L.0, PAR.L.E, PAR.H.0, PAR.H.E, P.BREAK
� parabolic rate coefficient B specification
METHOD statement
� ERFC, ERF1, ERF2, ERFG � “Bird’s beak” spec.
� VERTICAL � vertical oxide growth
� COMPRESS � compressible liquid model
� VISCOUS � incompressible liquid model
EEE 533 Semiconductor Device and Process Simulation
� Charged states at the interface and in the oxide
� The electronic properties of the oxide and the oxide/SC interface have profound effect on the properties of the devices
� There are a number of allowed states within the forbidden gap, called Shockley or Tamm states:
� Fast surface states:
- density: 1011 to 1012 cm-2
- time constant: 1 µsec
- responsible for generation-recombination effects at the surface
- increased leakage current when junction penetrates the surface
- Shorter minority carrier lifetimes
- early fall-off in transistor gain
� Slow states:
- behave as traps and are essentially ionized silicon- time constant on the order of seconds and months- do not influence electrical properties, but affect threshold voltage
� Oxygen-ion vacancies and alkali ions
EEE 533 Semiconductor Device and Process Simulation
Location of the oxide charges
• The charges that exist in a realistic MOS structure can be
classified into four different categories:
(1) Mobile ionic charges
(2) Oxide-trapped charges
(3) Fixed oxide charges
(4) Interface-trap charges
+ ++aN +
K
+-
+-
+-
+-
+-
+-
+ + + +
EEE 533 Semiconductor Device and Process Simulation
• Mobile oxide charges: Due to ionic impurities such as Na,
K, etc.
• Oxide-trapped charge: May be positive or negative and is
due to holes or electrons trapped in the bulk of the oxide.
• Fixed oxide charges: Due to structural defects (ionized
silicon) in the oxide layer.
• Interface-trapped charges: Positive or negative charges due
to:
structural, oxidation induced defects
metal impurities
other defects due to bond-breaking processes
Unlike other oxide charges, interface-trapped charge is in
electrical communication with the underlying silicon and
can be charged and discharged.
EEE 533 Semiconductor Device and Process Simulation
• The expression for the voltage drop across the oxide layer
Vox in the presence of a non-zero charge distribution ρ(x) is
found from the solution of the 1D Poisson equation, using
the boundary conditions: ϕox(0)=0 and ϕox(dox)=Vox .
• The final result of this calculation is given below:
• Special cases:
� uniform charge distribution: γ=1/2
� Charges at the SC/oxide interface: γ=1
� Charges at the metal/oxide interface: γ=0
∫ρ
∫ ρ
=γγ−=ox
ox
d
ox
d
ox
oxox
oxoxoxoxox
dxx
dxxx
dC
QdFdV
0
0
)(
)(1
,)(
EEE 533 Semiconductor Device and Process Simulation
• The threshold voltage shift due to workfunction difference
and charges in the oxide is given by:
• Important note: All the charges (mobile ion charges, fixed
oxide charges, oxide trapped charges) except the interface-
trap charges lead to rigid shift of the CV curve.
FBMSox
oxGGG V
qC
QVVV =Φ+γ−=−=∆
1'
Voltage applied to realMOS capacitor with
oxide charges
Voltage applied to idealMOS capacitor
Oxide charges Work functiondifference
Flat-bandvoltage
EEE 533 Semiconductor Device and Process Simulation
• More information on interface-trapped charges:
Most of the interface-trapped charges can be neutralized
by low-temperature hydrogen annealing.
The interface trap density is given by:
Interface trap charges can be:
- acceptor-like (above the intrinsic level)
- donor-like (below the intrinsic level)
=
eVcmdE
dQ
qD it
it 2
charges of #1 <111>
<100>
0 Eg
itD
EEE 533 Semiconductor Device and Process Simulation
FSE
CE
VE
iE
Use simplified model that all of the states below the Fermilevel are full and all of the states above the Fermi level are empty.
The excess negative charges
lead to positive shift.
FSE
CE
VE
iE
The excess positive charges
lead to negative shift.
Depletion: Accumulation:
EEE 533 Semiconductor Device and Process Simulation
Modification of the HF-CV curve due to interface-trapped charges.
HFC
oxC
GV
totC
Interface-traps close to valence band.
Interface-traps close to mid-gap.
Interface-traps close to conduction band.
oxC
accCdeplCinvC itC
Contribution from the charging and
discharging of the interface traps.
Gate
EEE 533 Semiconductor Device and Process Simulation
� Modeling of charge states
� The density of trapped carriers on the discrete set of defects/trap centers is given by:
where:
ββββ
ββββ
αααα
αααα
=β
β
=α
α
+++
+=
+++
+=
∑=∑=
npnp
nptdt
npnp
pntat
m
tt
k
tt
KKGG
GKNp
KKGG
GKNn
ppnn
,
,11
−−γσ=
−σ
γ=
σ=σ=
Tk
EEnVG
Tk
EEnVG
nVKpVK
B
tiinnn
B
tiippp
nnnppp
exp ;exp1
;
αααα: # of acceptor traps; ββββ: # of donor traps
Et : energy level of the trapγ :γ :γ :γ : degeneracy factorVn, Vp : thermal velocitiesσσσσn, σσσσp : capture cross-sections
EEE 533 Semiconductor Device and Process Simulation
� The introduction of traps into the model gives rise to
(a) Additional charge term in the Poisson equation:
(b) Modification of the SRH recombination term
where:
� The ATLAS implementation is via the TRAP statement:
DONOR, ACCEPTOR � trap type
E.LEVEL � trap energy level
DENSITY � density Nt of traps
DEGEN.FACTOR � γSIGN, SIGP � capture cross-sections for electrons and holes
TAUN, TAUP � electron and hole lifetimes (alternative)
( )ttt npq −=ρ
−−+τ+
−
γ+τ
−=
βαβα
βα
βα
Tk
EEnn
Tk
EEnp
npnR
B
tiip
B
tiin
i
,,
,
2
,
expexp1
( ) ( ) 11 ;
−− σ=τσ=τ tppptnnn NVNV
EEE 533 Semiconductor Device and Process Simulation
5. Description of the etching process
� Within the SSUPREM4 software, there is a very rudimentary model for the etching process, which considers etching as a purely geometrical problem
� Etch steps are simulated using the ETCH statement in which the material to be etched and the geometrical shape of the etch region are specified:
� polygonal region� region to the left or right of a line segment� region between top boundary and a line obtained by
translating top boundary down in the y-direction (DRYand THICKNESS parameters)
� All regions of a particular material type (ALL parameter)
� All materials in the defined region will be etched
� Specifying the material to be etched limits the etching pro-cess to the pre-selected material type
EEE 533 Semiconductor Device and Process Simulation
ETCH statement
This statement allows simulation of the etching process. SSUPREM4 only purely geometrical etch model, and ELITEincludes physical etch model.
� Important parameters that can be specified here are:
� SILICON, OXIDE, POLYSILICON, GAAS, PHOTORESIST, INP, … , � material to be etched
� ALL � all of the specified material is removed
� DRY � resulting surface replicates the exposed surface
� LEFT, RIGHT, ABOVE, BELOW � quick means of etching in a trapezoidal region (P1.X, P1.Y, P2.X, P2.Y)
� START, CONTINUE, DONE � arbitrary complex region to be etched
� THICKNESS � thickness to be etched
EEE 533 Semiconductor Device and Process Simulation
6. Description of the deposition process
� Deposition process is described via a simple algorithm that describes conformal deposition
� Parameters that are specified within the DEPOSIT state-ment include:
MATERIAL � specify material to be deposited
NAME.RESIST � type of photoresist to be deposited
THICKNESS � specifies the deposited thickness, in micrometers
DIVISIONS � number of vertical grid spacings in deposited layer
CONC � concentration of impurity (type must be specified also)
MIN.SPACE � minimum spacing between points on the surface
DY � nominal spacing in the layer
YDY � depth at which nominal spacing is applied relative to the surface
MIN.DY � minimum spacing allowed between grid-lines(default value is 10 angstroms)
EEE 533 Semiconductor Device and Process Simulation
7. Description of the epitaxy process
� This process simulates epitaxial deposition of silicon. It is limited to silicon on silicon applications and should not be used when other materials are present
� Parameters that are specified within the EPITAXY state-ment include:
ARSENIC, BORON, PHOSPH � specify material to be deposited
CONC � concentration of impurityDIVISIONS � number of vertical grid spacings in deposited layerDY � nominal spacing in the layerYDY � depth at which nominal spacing is applied relative to the
surfaceMIN.DY � minimum spacing allowed between grid-lines
(default value is 10 angstroms)PRESS � defines the pressure of epitaxial deposition processT.FINAL � final temperature for ramped epitaxial stepsTEMP � defines the temperature of the epitaxial depositionTIME, THICKNESS, RATE � parameters of epitaxial process
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