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Introduction to Lithography for
Nanometer VLSI Manufacturing
Professor Kuen-Yu Tsai
Nano-Detection and Fabrication Systems Group
Dept. of Electrical Engineering, National Taiwan University
2006/12/21
Acknowledgement: Ken-Hsien Hsieh, Philip CW Ng, Yi-Sheng Su, and Meng-Fu You
http://www.ee.ntu.edu.tw/professors#prf676http://www.ee.ntu.edu.tw/professors#prf6768/6/2019 Introduction to Lithography for Nanometer VLSI Manufacturing_v3 Public Kt
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Microlithography
A technology used in semiconductor manufacturing Image a pattern from a photomaskonto a silicon wafer coated
with a light sensitive material called photoresist.
Lithography at the sub-micrometer scale.
Source: Micronic http://www.micronic.se
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Optical Imaging System
Source: DongbuAnam Semiconductor [1]
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Moores Law-Number of transistors on a chip doubles every 2 years
i l l i f i h h 6
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65
45
32
22
16
Potential Solutions for Lithography, 2006
NTU NGL Teamcurrent research
Source: ITRS Lithography 2006
SOURCE S H SEMATECH
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Resolution Improvement by Immersion
Silicon wafer
Photoresist
Lens
sin4
1
sin4
1
sin4
1,
AIR
RESIST
RESISTAIR
RESIST
RESISTDRYMIN
n
n
HP
=
=
=
LIQUIDAIR
RESISTLIQUID
RESISTAIR
RESIST
RESIST
WETMIN
n
nn
n
HP
sin4
1
sin4
1
sin4
1,
=
=
=
Liquid
Photoresist
Silicon wafer
Lens
nwater
= 1.44
SOURCE: Scott Hector, SEMATECH
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Contents
Introduction to Microlithography
Resolution Enhancement Technology (RET)
Distortion; NTUEE OPC Design for Manufacturability (DFM)
What is DFM?
Circuit Model Related to Process-Induced Non-idealPatterning
Next Generation Lithgraphy
EUV E-beam direct-write
Conclusions
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At 90 nm technology, there is no yield without RET.
Resolution Enhancement Technology (RET)
RET uses pre-compensation of pattern in order to try to mitigate the
effects of the lithographic process. Several available RET techniques:
Phase-shifted maskPSM
Optical proximity correction OPC
Target No RET With RET
Off-axis illumination OAI
Source: Mentor Graphics WCR TSMN Boston Tech Symposium Apr. 2005.
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The Contributors to Non-Rectangular Wafer Pattern
Lithography process variations:
Lens aberration, misalignment, defocus, and overexposure
Sub-wavelength non-ideal optical effects due to
Diffraction and polarization effect
Those effects or variations would result in wafer pattern distortion:
Line-end shortening, corner-rounding, and line-edge roughness
Source: A. Balasinski, et al., Impact of sub wavelengthCD tolerance on device performance, SPIE, 2002.
Source: A. Balasinski, A methodology to analyze circuitimpact of processs related MOSFET geometry, SPIE, 2004.
Line-end shortening
Corner-rounding
Line-end roughness
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Optical Proximity Correction (OPC)
Optical proximity correction (OPC) is a photolithographyenhancement techniques commonly used to compensate the maskpattern for image errors due to diffraction or process effects[2].
Typical OPC type
Source: Synopsys [6]Source: DongbuAnam Semiconductor [1]
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NTUEE Model-Based OPC Engine
After NTUEE OPC: Corrected mask
pattern
No OPC: Contours of desired pattern
and wafer pattern
With NTUEE OPC: Contours of
desired pattern and wafer pattern
Segment length= 72 nm
Iteration number: 10
Before OPC: Mask pattern
sdasdasdasdasd
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Contents
Introduction to Microlithography
Resolution Enhancement Technology (RET)
Distortion; NTUEE OPC Design for Manufacturability (DFM)
What is DFM?
Circuit Model Related to Process-Induced Non-idealPatterning
Next Generation Lithgraphy
EUV E-beam direct-write
Conclusions
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Design for Manufacturability (DFM)
A design methodology includes a set oftechniques to
modify the design of ICs in order to improve:
Functional yield, parametric yield, reliability Techniques includes:
Substituting higher yield cells where permitted by timing, power,
and routability. Changing the spacing and width of the interconnect wires,
where possible
Optimizing the amount ofredundancy in internal memories.
Substituting fault tolerant (redundant) vias in a design where
possible.
Historical Mode of Operation for
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BIM PSM
Historical Mode of Operation for
Circuit Design and Fabrication
Organizational, corporatecultural and geographical
barriers
Wafer fab
Circuit architecture
Masks
LayoutTest data Packaged IC
Device models Design rules
Physical
design
Design
SOURCE: Scott Hector, SEMATECH
New Mode of Operation With Design
SOURCE: Scott Hector, SEMATECH
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DFM-aware
physical design
New Mode of Operation With Design
for Manufacturing (DFM) Practices
Wafer fab
Circuit architecture
Masks optimizedbased on design intent
Layout
withcriticalpaths
Device models with processvariation information
Design rules
Statistical
optimization
010203040
Frequency
Process variation information
BIM, ACI CD 7
PSM, ACI CD 8
BIM, ACI CD 7 Packaged IC
DFM guidelines
IP maturitydatabase
DFMscore
Test data
Design
Circuit Model Related to Process Induced
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Circuit Model Related to Process-Induced
Nonideal Patterning
A variation-aware model (e.g. SPICE BSIM4) could be built to
predict circuit performance variability based on circuit design andcharacterized source of manufacturing variation including:
Poor ILS (image log-slope)
Defocus
Misalignment
Process modeling Device modeling
TCAD simulation SPICE modeling
PerformanceVariation-aware modelCircuit layout Lithography process
Variation-aware Circuit device
Aberration in the lens
Overexposure
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Contents
Introduction to Microlithography
Resolution Enhancement Technology (RET)
Distortion; NTUEE OPC
Design for Manufacturability (DFM)
What is DFM?
Circuit Model Related to Process-Induced Non-idealPatterning
Next Generation Lithgraphy
EUV E-beam direct-write
Conclusions
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S f th NGL A ti iti t NTU
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Some of the NGL Activities at NTU
Prof.\TechnologyML2 EUV Immersion Imprint Near-field
Yung-Yaw Chen Yes
Cheewee Liu Yes
Fu-Cheng Wang Yes
Sen-Yeu Yang Yes
Jia-Yush Yen Yes Yes
Lon Wang Yes Yes Yes
Kuen-Yu Tsai Yes Yes Yes Yes
Tien-Tung Chung Yes
Jia-Han Li Yes Yes Yes
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EUV Lithography
Utilize 13.5-nm wavelength light(extreme ultra-violet).
Reflective optics (mirrors with
multi-layer coating). One of the most promising
technology for 32-nm-and-below
mass production. Disadvantages:
High energy loss in reflective optical
system due to the nature of EUV light. Extremely high cost in light sourceand optical components maintenance.
SOURCE: Carl Zeiss
M i l P ll l M k l Li h h
http://www.zeiss.de/C1256A770030BCE0/WebViewAllE/D6279194C2955B2EC12570CF0044E537http://www.zeiss.de/C1256A770030BCE0/WebViewAllE/D6279194C2955B2EC12570CF0044E5378/6/2019 Introduction to Lithography for Nanometer VLSI Manufacturing_v3 Public Kt
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Massively Parallel Mask-less Lithography
(MPML2)
E-beam lithography is capable ofsub-20 nm patterning.
E-beam direct write technique eliminate the cost of
mask fabrication (~2M USD.) and correction (~1 week).
Direct write technique is capable of patterning more
complex patterns (e.g. Fresnel zone plate).
Challenges:
Integrate as many as possible beams into the system.
Design an effective writing strategy to maximize system
throughput.
Electron-resist interaction (proximity effect) correction.
Design a data transfer system to process huge data at one time.
Multiple E beam Maskless
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Multiple E-beam Maskless
Lithography Research Several countries have been seriously involved with research in e-beam direct
write systems.
The main motivation of this research is to develop key technologies for MEMS-based maskless e-beam exposure systems
MPML2, NTU
Schematic of MAPPER system [7] Schematic of MCC, Advantest [8]
Schematics of Canons System [9]
Schematic of REBL, KLA [10]
Not for public disclosure
2006/12/21
Multiple E beam ML2
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Multiple E-beam ML2
Electron Source MEMS-based electron emitters: Provide the electron beam current with enough
brightness during wafer exposure.
Microchannel amplifier array: Provide stable, high-current operation and long-termreliability.
Arradiance Inc.[11]
Multiple E beam ML2
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Multiple E-beam ML2
Electron Optics 2-D and 3-D electromagnetic lens simulation environment is built up.
Control theories can be applied to optimize lens
structures and minimize the beam size.
Electrostatic field of einzel lens and electron
trajectory are simulated under MATLAB and
COMSOL Multiphysics.
Multiple E beam Maskless
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Multiple E-beam Maskless
Lithography Research Electron scattering is the main limitation of EBL resolution. Two types of scattering:
Forward scattering: Electrons scatter by resist atoms.
Backscattering: Electrons bounce back from substrate.
forward scattering
backscattering
Trajectories of 200 electrons with energy of
20keV is simulated by MONTE.
desired pattern
developed pattern
C
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Contents
Introduction to Microlithography
Resolution Enhancement Technology (RET)
Distortion; NTUEE OPC
Design for Manufacturability (DFM)
What is DFM?
Circuit Model Related to Process-Induced Non-idealPatterning
Next Generation Lithgraphy
EUV E-beam direct-write
Conclusions
Conclusions and Suggestions for Students
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C a S gg S
conducting Microlithography-centered Research
Lithography technology is Very important to keep Moores law valid
Highly interdisciplinary Very interesting!!
Be open minded
Start from basics, even high school stuff Really understand simple things Built complex concepts/systems based on simple things
System Engineering concepts can help integration
System theories, control, signal processing, optimization canfacilitate Interdisciplinary Research
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Questions and Answers (5-10min) Any questions about:
Lithography in general
MS at NTU
PhD/Study abroad at Stanford/USA Work at Intel/USA
What my classmates are doing Other?
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References1. Keeho Kim, Optical Lithography, DongbuAnam Semiconductor, Nano Team/ R&D.
2. Wikipedia, OPC article, available athttp://en.wikipedia.org/wiki/Optical_proximity_correction
3. Rajesh Menon, D. J. D. Carter, Dario Gil, and Henry I. Smith,Zone-Plate-Array
Lithography (ZPAL): Simulations for System Design, MIT, NanoStructuresLaboratory (NSL)
4. Rajesh Menon, D. J. D. Carter, Dario Gil, and Henry I. Smith, Zone-Plate-ArrayLithography (ZPAL): Optical Maskless Lithography for Cost-Effective Patterning,Proc. of SPIE, Emerging Lithographic Technologies IX, Vol. 5751,May 2005
5. ITRS Lithography Roadmap, available athttp://public.itrs.net/
6. Synopsys OPC tool, available athttp://www.synopsys.com/products/ntimrg/opc_ds.html
7. SEMATECH Maskless Workshop, Jan. 2005. available at
http://www.sematech.org/resources/litho/meetings/emerging/20050117/8. A. Yamada, ADVANTEST Technology Developments, Maskless Workshop, January
17-19 2005
9. Phillip Ware, Removing The Mask, oe magazine pp. 26-27, march 2002.
10. Marian Mankos, Harald F. Hess, David L. Adler, and Kirk J. Bertsche, Maskless
reflection electron beam projection lithography, US Patent Issued on March 22, 200511. Arradiance, Inc., available at http://arradiance.com/index.html
http://arradiance.com/index.htmlhttp://en.wikipedia.org/wiki/Optical_proximity_correctionhttp://en.wikipedia.org/wiki/Optical_proximity_correctionhttp://public.itrs.net/http://public.itrs.net/http://www.synopsys.com/products/ntimrg/opc_ds.htmlhttp://www.synopsys.com/products/ntimrg/opc_ds.htmlhttp://www.sematech.org/resources/litho/meetings/emerging/20050117/http://www.sematech.org/resources/litho/meetings/emerging/20050117/http://arradiance.com/index.htmlhttp://arradiance.com/index.htmlhttp://www.sematech.org/resources/litho/meetings/emerging/20050117/http://www.synopsys.com/products/ntimrg/opc_ds.htmlhttp://public.itrs.net/http://en.wikipedia.org/wiki/Optical_proximity_correctionTop Related