1
FPGAs used in Industrial Control Systems
Prof. Eric Monmasson, Cergy-Pontoise University, Cergy-Pontoise, France
Email: [email protected]. Marcian Cirstea,
Anglia Ruskin University, Cambridge, UKEmail: [email protected]
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Introduction, Presentation of the Current Trends (30 min, MC, EM)Description of FPGAs (30 min, EM)Holistic Modelling/Design Methodology (30 min, MC)Main Design Rules (30 min, EM)
– Refinement of Control Algorithms by Simulation– Algorithm Architecture Adequation– Reusability, VHDL Coding– Hardware-In-the-Loop (HIL) Validation
Coffee break --------------------------------------------------------------------------------------
1st case studies series: FPGA-based Current Controllers for AC Drives (40 min, EM)– Quasi-Analog Hysteresis Controller– Delta Modulator– PI – SVM Controller– Predictive Controller
2nd case studies series: FPGA-based Intelligent Controllers for AC Drives and AC Generators (40 min, MC)
– Induction Motor Control Using Neural Networks– Stand Alone Generator Set Using Fuzzy-Logic and PWM
Conclusions and Perspectives (10 min, EM, MC)Hands on practical demonstration on two simple examples (30 min, EM, MC)
Overview
ELECTRONIC SYSTEMS ON CHIPTechnical Committee of IEEE Industrial
Electronics Society http://vega.unitbv.ro/~ieee
Mission Statement:This Committee aims to promote professional activities in the area of low power electronics used in the modern industry, with an important focus on the design, development, simulation, verification and testing of digital and analogue circuits integrated as Systems on Programmable Chips, targeting Field Programmable Gate Arrays / Application Specific Integrated Circuits for implementation, and including the use of Hardware Description Languages or high level programming languages hardware compilers, as well as embedded electronic systems and associated software.
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Chair: Dr. Marcian Cirstea, Head of Department of Design & Technology, Anglia Ruskin University, Cambridge, UK.
Email: [email protected]
Special conference sessions organisations subcommitteeCoordinator and Committee Vice-Chair: Dr. Manus Henry, Deputy Director, Invensys University Technology Centre for Advanced Instrumentation at the Department of Engineering Science, the University of Oxford, UK. Dr.Vito Nardi, University of Cassino, Italy.
Special Issues / Sections of Journals subcommitteeCoordinator: Prof. Eric Monmasson, Head of the Institut UniversitaireProfessionnalisé de Génie Electrique et d’Informatique Industrielle (IUP GEII), University of Cergy-Pontoise (UCP), France.Prof. Josep M. Guerrero, Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. Dr. Jeen G. Khor, Senior Design Engineer, INTEL, Penang, Malaysia.
Web page subcommitteeCoordinator: Dr. Andrei Dinu, Goodrich Engine Control Systems, Electromagnetic Systems Technical Centre, Birmingham, UK. Dr. Otilia Boaghe, Phillips Semiconductors, Zurich, Switzerland.
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Conferences / transactions papers review subcommittee
Coordinator: Prof. Dan Nicula, Transilvania University Brasov, Romania.
Prof. Bogdan ‘Dan’ Willamowski, Past President of the Industrial Electronics Society, Auburn University, AL, USA.
Dr. Jeroen Van Den Keybus, Catholic University of Leuven, Belgium.
Dr. Yasuhiro Ota, Partner Robot Development Division, Toyota Motor Corporation, Aichi, Japan.
Prof. Chin-Long Wey, Dean of College of Electrical Engineering and Computer Science, National Central University, Chung-Li, Taiwan.
Dr.Robert Seliga, Electronics Design Engineer, Newage AVK SEG, Stamford, UK.
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Activity Plan 2007Website development to support & promote committee’s work and to provide a point of reference on topics of interest. Guest-Editorship of a special issue of the Transactions on Industrial Electronics: FPGAs used in Industrial Control Systems. Dr. Eric Monmasson and Dr. Marcian Cirstea are joint Guest Editors.Organisation of a “best paper” prize of $500 for this Special IssueOrganisation of special sessions at the forthcoming IEEE IES Conference: ISIE’07. Organising ISIE’08 in CambridgeRefereeing of IEEE Transactions and Conference papers. Contributing to the organisation of other IES conferences by chairing Technical Tracks, refereeing papers, etc. Presenting tutorialsPrinting materials to advertise the committee, as well as its technical activities, as posters / leaflets.
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Traditionally, mathematical models were used to functionally evaluate engineering systems. The development of each system component used then to be separately addressed, often involving the use of other CAD tools and/or different software platforms.
Traditional methods are not able to cope with increased complexity and demands of higher levels of systems integration / faster time to market. Recent advances in CAD methodologies/languages has brought the system’sfunctional description and hardware implementation closer.
Modern Electronic Design Automation (EDA) tools are used to model, simulate and verify a complex engineering system fast, with high confidencein “right first time” correct operation, without producing a prototype.
High performance electronic controllers can also be implemented.
The presentation reveals recent work that was carried out in the area of holistic modelling of engineering systems using HDLs.
Introduction
8
Traditionally, mathematical models were used to functionally evaluate engineering systems. The development of each system component used then to be separately addressed, often involving the use of other CAD tools and/or different software platforms.
Traditional methods are not able to cope with increased complexity and demands of higher levels of systems integration / faster time to market. Recent advances in CAD methodologies/languages has brought the system’sfunctional description and hardware implementation closer.
Modern Electronic Design Automation (EDA) tools are used to model, simulate and verify a complex engineering system fast, with high confidencein “right first time” correct operation, without producing a prototype.
High performance electronic controllers can also be implemented.
The presentation reveals recent work that was carried out in the area of holistic modelling of engineering systems using HDLs.
Introduction
9
Integrated CircuitsOff-the-Shelf Logic - Function pre-set.
PROM, PAL, FPLA - Programmed by fusible links / charge storage.
FPGAs - User programmable Field Programmable Gate-Arrays.
Gate Array Device - Function set at manufacture in the final stage of production (metallization).
Cell Based Device - Function set at manufacture using CAD to speed up design and a library of optimised standard functions.
Full Custom Device - Function set at manufacture - every circuit part is optimally designed. Long development time even with CAD.
More gates / chip ==> reduces cost but requires CAD.
10
Comparative Economics Cost
(relative) full-custom
cell -based
system
gate-array SSI / MSI
Volume 10,000 50,000 ….100,000
True cost formula shows that the final unit cost is:cost = D / N + chip + F
where D=total development cost, N=no. of chips manufactured,chip=unit chip costs in production, F=packaging, testing per chip
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Application Specific Integrated CircuitsApplication Specific Integrated Circuits (ASICs) = any IC designed and built specifically for a particular application.
ASICs allow tailoring the design during development stages of an IC. Advantages:
Reduced Size and CostHigh Speed and Accuracy in Information ProcessingCompact StructureHigh Reliability of Circuit Operation
Two major ASIC technologies: CMOS and BICMOS - millions gates.
RISC and DSP cores are now offered by chip suppliers. They permit the design of single chip customised advanced integrated processors.
Field-Programmable Gate Arrays (FPGAs) are a special class of ASIC'swhich differ from mask-programmed gate arrays in that the programming is done by end-users with no IC masking steps.
12
Introduction
FPGAs have reached high density rate ( > 10 millions gates)Performing Electronic Design Automation (EDA)ToolsThese components allow the programming of specific hardware architecture This leads to a flexible and an efficient solution (software development of dedicated hardware architecture that includes parallelism)System-on-a-Chip (SoC) scale
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Introduction
Many industrial applications– Telecom,– Video,– Signal Processing,– Medical Systems,– Embedded Systems (Aircraft, Automotive),– Electrical Systems:
PWM inverters, Power factor correction AC/DC converters, Multilevel converters, Matrix converters, Active filters,Fault-detection on power grid,Electrical machines control (induction machine drives, multi-machines systems, Neural Network control of induction motors, Fuzzy Logic control of power generators, Speed measurement…
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The decrease of the cost – An architecture based only on the specific needs of the algorithm to implement, – Application of highly advanced and specific methodologies improving implementation
time also called "time to market", – Expected development in VLSI design that will allow integrating a full control system
with its analog interface in a single chip, SoC.The confidentiality– Specific architecture, integrating the know-how of a company, is not easily duplicable.
The embedded systems– Many constraints as in aircraft applications, like limited power consumption, thermal
consideration, reliability and Single Event Upset (SEU) protection.The improvement of control performance– Execution time can be dramatically reduced by designing dedicated parallel architectures,
allowing FPGA-based controllers to reach the level of performance of their analog counterparts without their drawbacks (parameter drifts, lack of flexibility).
– FPGA-based controller can also be adapted in run-time to the needs of the plant by dynamically reconfiguring it.
IntroductionAdvantages:
15
Introduction
DSP
FPGA
(a) (b) (c)
(d)
Algorithm Timing constraints
Alg
orith
m c
ompl
exity
(a) : high data dependency (b) : high level of parallelism of the algorithm(c) : few functions and / or homogenous functions (d) : lot of functions and / or heterogeneous functions
A specific architecture for each control algorithm16
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Speed&
FluxRegulators
Speed&
FluxRegulators
isd
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Flux & SpeedObservation
(Sensorless operating mode)
Flux & SpeedObservation
(Sensorless operating mode)
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Introduction
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• Algorithmic Constraints:
Algorithm Architecture “Adequation ” by means of FPGA
• Vector Control Algorithm:
– SVPWM– Current Regulator– Flux Estimator
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17
Introduction
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How to easily implement a control algorithm on an FPGA-based optimized hardware architecture?
Simulink ModelFPGA board
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This leads to follow up a design methodology
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functional simulation Fixed-point quantization & discrete model
VHDL codingFPGA targetExperimental board
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Introduction
19
Generic FPGA Architecture
C onfigurable Input/O utput
Block
C onfigurable Logic Block
Interconnection Program m able
N etwork
20
Generic FPGA Architecture
Inputs [3:0]
LUT LUT
Chemin Carry Path
Bascule D D
Flip-Flop
Input carry
Clock
Flip-Flop output
Combinatorial output
Output carry
• Logic Cell / Logic Element :
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Head-to-Head
Xilinx Virtex-5– 1v 65nm copper– 207,360 logic cells– 11.6 Mb RAM– 192 48-bit MAC Unit
(25x18 multipliers, 550MHz)
– Up to four PowerPC 405 cores
– MicroBlaze 32-bit soft core
Altera Stratix II– 1.2v 90nm copper– 179,400 logic elements– 9.4 Mb RAM– 96 36x36 multipliers
(384 18x18 multipliers)– 1,170 user I/O pins
– Nios II 32-bit soft processor core
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Head-to-Head – Low Cost
Spartan 3E– 1.2v 90nm copper– 33,192 logic cells– 0.65 Mb RAM– 36 18x18 multipliers– 376 user I/O pins– 8 DCMs
– MicroBlaze 32-bit soft processor core
Altera Cyclone II– 1.2v 90nm copper– 68,416 logic elements– 1.15 Mb RAM– 150 18x18 multipliers– 622 user I/O pins– 4 PLLs
– Nios II 32-bit soft processor core
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Virtex-4 Architecture
1 Gbps SelectIO™ChipSync™ Source synch, XCITE Active Termination
Smart RAM New block RAM/FIFO
Xesium ClockingTechnology
500 MHz
PowerPC™ 405with APU Interface450 MHz, 680 DMIPS
Tri-ModeEthernet MAC
10/100/1000 Mbps
RocketIO™Multi-GigabitTransceivers
622 Mbps–10.3 Gbps
XtremeDSP™Technology Slices
256 18x18 GMACs
Advanced CLBs200K Logic Cells
24
Virtex IV Platforms
ResourceResource
14K14K––200K LCs200K LCsLogic
Memory
DCMs
DSP Slices
SelectIO
RocketIO
PowerPC
Ethernet MAC
LXLX FXFX SXSX
0.90.9––6 Mb6 Mb
44––1212
3232––9696
240240––960960
23K23K––55K LCs55K LCs
2.32.3––5.7 Mb5.7 Mb
44––88
128128––512512
320320––640640
12K12K––140K LCs140K LCs
0.60.6––10 Mb10 Mb
44––2020
3232––192192
240240––896896
00––24 Channels24 Channels
1 or 2 Cores1 or 2 Cores
2 or 4 Cores2 or 4 Cores
N/A
N/A
N/A
N/A
N/A
N/A
25
Altera Stratix
26
Slices and CLBs
Each Virtex™-II CLB contains four slices– Local routing provides
feedback between slices in the same CLB, and it provides routing to neighboring CLBs
– A switch matrix provides access to general routing resources
CIN
SwitchMatrix
BUFTBUF T
COUTCOUT
Slice S0
Slice S1
Local Routing
Slice S2
Slice S3
CIN
SHIFT
27
Distributed SelectRAM Resources
Uses a LUT in a slice as memorySynchronous writeAsynchronous read– Accompanying flip-flops
can be used to create synchronous read
RAM and ROM are initialized duringconfiguration– Data can be written to RAM
after configurationEmulated dual-port RAM – One read/write port– One read-only port
RAM16X1S
O
DWE
WCLKA0A1A2A3
LUTLUT
RAM32X1S
O
DWE
WCLKA0A1A2A3A4
RAM16X1D
SPO
DWE
WCLKA0A1A2A3DPRA0 DPODPRA1DPRA2DPRA3
Slice
LUT
LUT
28
Slice 0
LUTLUT CarryCarry
LUTLUT CarryCarry D QCE
PRE
CLR
DQCE
PRE
CLR
Simplified Slice Structure
Each slice has four outputs– Two registered outputs,
two non-registered outputs– Two BUFTs associated
with each CLB, accessible by all 16 CLB outputs
Carry logic runs vertically, up only– Two independent
carry chains per CLB
29
Altera Stratix
30
Logic Array Blocks (LABs)
31
Logic Element
32
Embedded RAM
Xilinx – Block SelectRAM– 18Kb dual-port RAM arranged in columns
Altera – TriMatrix Dual-Port RAM– M512 – 512 x 1– M4K – 4096 x 1– M-RAM – 64K x 8
33
Xilinx: Embedded Multipliers
18-bit twos complement signed operationOptimized to implement Multiply and Accumulate functionsMultipliers are physically located next to block SelectRAM™memory
18 x 18Multiplier18 x 18Multiplier
Output (36 bits)
Data_A (18 bits)
Data_B (18 bits)
18 x 18signed12 x 12signed8 x 8 signed4 x 4 signed
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Altera: Embedded DSP Blocks
Two DSP Block columns per deviceNumber varies by height of columnCan implement:– Eight 9x9 multipliers– Four 18x18 multipliers– One 36x36 multiplier
Contains adder/subtracter/accumulatorRegistered inputs can become shift register
35
Altera Multiplier Sub-block
36
Virtex: Active Interconnect
37
Virtex Hierarchical Interconnect
38
Altera: MultiTrack Interconnect
Direct link between LABs and adjacent blocksRow interconnects– 4, 8, and 24 blocks left or right
Column interconnects– 4, 8, and 16 blocks up or down
39
Stratix: R4 Interconnect
40
MicroBlaze Processor-Based Embedded Design
Flexible Soft IPMicroBlaze™32-Bit RISC Core
UART 10/100E-Net
Memory Controller
Off-ChipMemory
FLASH/SRAM
Fast Simplex Link
0,1….7
CustomFunctions
CustomFunctions
BRAM Local Memory
BusD-CacheBRAM
I-CacheBRAM
ConfigurableSizes
Arb
iter
Processor Local Bus
Instruction Data
PLBBus
Bridge
PowerPC405 Core
Dedicated Hard IP
Arb
iter
Processor Local Bus
Instruction Data
PLBBus
BridgeBus
Bridge
PowerPC405 Core
Dedicated Hard IP
PowerPC405 Core
Dedicated Hard IP
PowerPC405 Core
Dedicated Hard IPPossible inVirtex-II Pro
Hi-SpeedPeripheral
GB E-Net
e.g.Memory
ControllerHi-Speed
PeripheralHi-Speed
PeripheralGB
E-NetGB
E-Net
e.g.Memory
Controller
e.g.Memory
Controller
Arb
iter OPB
On-Chip Peripheral Bus
CacheLink
SRAM
41
Embedded DevelopmentTool Flow Overview
Data2MEM
Download CombinedImage to FPGA
Compiled ELF Compiled BIT
RTOS, Board Support Package
EmbeddedDevelopment Kit
Instantiate the ‘System Netlist’and Implement
the FPGA
?
HDL Entry
Simulation/Synthesis
Implementation
Download BitstreamInto FPGA
Chipscope
Standard FPGAHW Development Flow
VHDL or Verilog
System NetlistInclude the BSPand Compile theSoftware Image
?
Code Entry
C/C++ Cross Compiler
Linker
Load SoftwareInto FLASH
Debugger
Standard EmbeddedSW Development Flow
C Code
Board SupportPackage
12 3 Compiled BITCompiled ELF
42
Altera Nios II
43
Altera Nios II
44
SoPC Builder
45
Actel Fusion
46
Actel Fusion - ADC
ACMFlash
memory
RTC
Analog multiplexer
AnalogQuad
9
ADC
12 bits
AnalogQuad
8
AnalogQuad
1
AnalogQuad
0
Analog Bloc
ADCSTART
5 bits CHNUMBER[4 :0]
DATAVALIDCALIBRATE
ADCRESULT [11 :0]
AV0AC0AG0
AT0
AV1AC1AG1
AT1
AV8AC8AG8
AT8
AV9AC9AG9
AT9
0143031
Températureinterne
Vcc(1.5V)
SYSCLK = 50MHz
ADCCLK
Freq_div
01
6 MHz
CLK
:
47
Actel ProASIC
48
Actel ProASIC
49
NOTHING EASIER !
In trouble with a chip design ?
50
Design Methodologies – EDA Tools
Traditional
Modern
Everybody hates EDA tools at some stage !!!
51
Design flow
Design Entry (schematic,HDL, state diagram).CompilationApply stimulusSimulationImplementation and LayoutTiming Analysis / VerificationDownload design into siliconTesting the chip
52
Novel Systems Modelling Method- main features and context -
Extends the traditional use of Hardware Description Languages (HDLs) for electronic circuits design, to encompass holistic modelling of more complex engineering systems.
Outcome: design environment that allows all aspects of the system to be simultaneously considered, therefore maximising performance.
Proposed approach correlated with powerful international movement/leading edge research, directed towards system level modelling/design.
The international EDA community, united under ACCELLERA (2000) (http://www.accellera.org/index.html), assumed the mission to drive the worldwide development and use of standards required by systems, semiconductors & design tools.
Clear proof of the internationally identified need for the development of holistic models for complex engineering systems.
Proposed for engineering systems’ holistic modelling: VHDL = Very high speed integrated circuit Hardware Description Language. (IEEE, 1993).
53
Specific Advantages Offered by VHDL
Allows the functional/behavioural description of an engineering system to be combined with a detailed electronic design, on the same CAD platform.
The mathematical aspects of systems and the electronic hardware design are simultaneously addressed, in a unique environment.
It is supported by all major Computer Aided Design platforms
Ability to handle all levels of abstraction. The system can be simulated as an overall model during all stages of the electronic controller design, which can be subsequently targeted for “system on a chip” silicon implementation.
Fast implementation & relatively short time to market of new designs.
Hardware Implementation of Artificial Intelligence is facilitated.
Versatile reusable models / design modules are generated, in accordance with modern principles of design reuse.
54
Advantages of FPGA Controller Prototyping
A cheap & fast VHDL code validation is via a prototype board containing re-programmable devices - Field Programmable Gate Arrays (FPGAs).
Allows electronic controllers’ hardware validation that provides significant information before the decision is taken to invest in an Application Specific Integrated Circuit (ASIC) = IC dedicated specifically to an application.
It shortens the time to correct any design problem and it ensures an error free design before permanent ASIC implementation.
The prototype board can be used for hardware testing other system components.
The general benefits of holistic modelling of systems, combined with the advantages of VHDL and FPGAs, enable the efficient investigation of new engineering system topologies employing complex electronic controllers.
55
Engineering Systems Modelling Approach Summary
•Modelling / Development: VHDL•Electronic Controller Hardware Prototyping: FPGA•Advantages of using VHDL⇒ Efficient design process⇒ Single environment for modelling, simulation & electronic controller design. ⇒ Easy modifications and system integration of designs⇒ EDA platform independence of VHDL designs (ASCII files)⇒ Reusable IP block modelling/design style becomes possible
•Advantages of using FPGAs⇒ Small, compact design⇒ Fast, relatively cheap⇒ Reusable hardware framework for testing a design⇒ Short time to market of product, rapid prototyping 56
Top-Down DesignVHDL allows the designer to develop and simulate ideas fast, without getting caught-up in the details of implementation.
As the design evolves to completion, the language is able to support a complex detailed digital system description.
Top-down design begins with modelling an idea at an abstract level, and proceeds through the iterative steps necessary to further refine this into a detailed system.
A test environment is developed early in the design cycle. Concepts are tested before investment is made in implementation.
As design evolves to new levels of detail, the test environment will check compliance with the original specification.
57
VHDL Description
Evolution of the VHDL language began in 1980's and resulted in the adoption of the VHDL's IEEE Standard (1993). Due to increased demands of higher levels of integration / faster time-to-market, a standard language, that referenced a higher level of design abstraction was needed. This stand-alone specification is not dependent on any specific tool.An entire system, once consisting of many components/circuit boards, can be replaced by one/two integrated circuits.VHDL's flexibility and choice of modelling styles enable a natural progression from idea to implementation, giving the designer the ability to quickly create, simulate, and verify an abstract model. Thus, design concepts can be tested before the investment is made in the hardware implementation.A major feature of VHDL is its inherent ability to handle all levels of abstraction. The designer requires the use of only a single language, as well as a single simulator for all phases of design. 58
Design UnitsEntity: describes the interface between the outside world and the
design. The connection points (PORTs) to the design, the direction and type of data that flows through these points are defined here.
For example, an AND gate with 3 connection points, 2 inputs and 1 output and data type “bit” (values '0' or '1') might look like:
ENTITY and2 IS
PORT (in1,in2: IN bit;
outp: OUT bit);
END and2;
Architecture: defines an entity's behaviour from a simulation point of view. It depends upon the information declared within an entity.
59
A behavioural architecture example for the and2 entity is:ARCHITECTURE arch1 OF and2 ISBEGIN
output <= in1 and in2;END arch1;
A structural architecture of a 3 input AND gate is:ARCHITECTURE struct OF and3 IS
COMPONENT and2PORT(sig1,sig2: IN bit;
sig3: OUT bit);END COMPONENT;SIGNAL internal:bit;
BEGINu1:and2 PORT MAP(sig1=>in1, sig2=> in2, sig3 => internal);u2:and2 PORT MAP(sig1=>in3, sig2=>internal, sig3=>output);END struct; 60
Behavioural DesignIn VHDL behavioural descriptions there is no reference to submodules within a specific VHDL architecture. This does not preclude the use of subprograms within VHDL descriptions, but precludes the use of other VHDL components. Behavioural descriptions are defining the design functionality. A behavioural description of a multiply accumulate device (mac) is:USE WORK.util.ALL;ENTITY mac IS
GENERIC(tco: time := 10 ns);PORT( in1, in2: IN bit_vector(15 DOWNTO 0);
clk, reset: IN bit;out1: OUT bit_vector(31 DOWNTO 0));
END mac;ARCHITECTURE behave OF mac ISBEGIN
PROCESS (clk, reset)VARIABLE reg_in1, reg_in2, reg_mul, accum: integer;
61
BEGIN IF reset = '0' THEN
reg_in1 := 0;reg_in2 := 0;reg_mul := 0;accum := 0;
ELSIF rising_edge(clk) THENaccum := accum + reg_mul;reg_mul := reg_in1 * reg_in2;reg_in1 := vect_to_int(in1);reg_in2 := vect_to_int(in2);
END IF;out1 <= int_to_vect(accum,32) AFTER tco;
END PROCESS;END behave;
Bit_vector is a one dimensional array of bits. The width of the array is determined in the port declaration. The width of in1 and in2 is 16 bits while out1 is 32 bits. They can be visualised as buses. 62
Structural DesignStructural descriptions are categorised by the instantiation & interconnection of VHDL components. They can be viewed as VHDL netlists. The architecture's body instantiates as many declared components as needed, and connects those components by the use of the PORT MAP construct. A structural architecture for the mac entity is:
ARCHITECTURE structure OF mac ISCOMPONENT reg
GENERIC(width: integer := 16);PORT( d: IN bit_vector(width-1 DOWNTO 0);
clk: IN bit;q: OUT bit_vector(width-1 DOWNTO 0));
END COMPONENT;COMPONENT adder
PORT( port1, port2: IN bit_vector(31 DOWNTO 0);output: OUT bit_vector(31 DOWNTO 0));
END COMPONENT;
63
COMPONENT multiplyPORT( port1, port2: IN bit_vector(15 DOWNTO 0);
output: OUT bit_vector(31 DOWNTO 0));END COMPONENT;COMPONENT buf
PORT( input: IN bit_vector(31 DOWNTO 0);output: OUT bit_vector(31 DOWNTO 0));
END COMPONENT;SIGNAL reg_in1, reg_in2: bit_vector(15 DOWNTO 0);SIGNAL mul, reg_mul, adder, accum: bit_vector(31 DOWNTO 0);
BEGINu1: reg GENERIC MAP(16) PORT MAP(in1, clk, reg_in1);u2: reg GENERIC MAP(16) PORT MAP(in2, clk, reg_in2);u3: multiply PORT MAP(reg_in1, reg_in2,mul);u4: reg GENERIC MAP(32) PORT MAP(mul, clk, reg_mul);u5: adder PORT MAP(reg_mul, accum, adder);u6: reg GENERIC MAP(32) PORT MAP(adder, clk, accum);u7: buf PORT MAP(accum, out1);
END structure; 64
Library/Use statementThe Library Statement: A library can be referenced by the identifier. The name of the library must be made visible using the LIBRARY statement:
LIBRARY IEEE; ENTITY test ISEND test;
VHDL implicitly provides two library statements before every design unit, making the libraries STD and WORK available:
LIBRARY STD;LIBRARY WORK;
To make a package in a library visible to a design unit, the package must be specified with a USE statement including: name of a library followed by a dot '.', package name followed by a dot '.', and reference to a package element (type, constant, signal, function, etc.). It ends with semicolon ';'.
USE ieee.std_logic_1164.ALL;Provided implicitly: a USE statement that makes the STANDARD package from the STD library available to all design units:
USE STD.STANDARD.ALL;
65
The VHDL model is converted into a hardware structure with the help of synthesis tools.
First the VHDL model is mapped to a hardware structure described using cells from a technology library. Then the netlistis “placed and routed”.
Usually an optimizer is involved in generating the final result based on silicon area minimisation or speed considerations.
The VHDL code has to be written in a style that is implementable and generates reliable circuits.
Synchronous circuits are preferred.
VHDL Design for Synthesis
66
Flip-flop Output Driving the Clock Input of Another Flip-Flop
d q
> c k q b
d q
> c k q b
Clock Signal Situations
Avoiding Gated Clock by Using a Clock Enable
67
Clock BufferingIn FPGAs the clock tree is already designed and the clock distribution is dealt with automatically be the synthesis tool.For ASIC design it may be necessary to design the clock tree manually.It is important to avoid:Clock skew generated by unequal depth of clock buffering.Unequal load-dependent delays generated by unbalanced clock buffers fan-out.Slow clock edges due to excessive buffer loading.
Incorrect Clock Buffering
68
Correct Clock Buffering
The circuit provides the same buffering depth at all clocked points;All buffers have the same fan-out;The buffers are lightly loaded (less than 50% of maximum fan-out).
69
Shift Registers and Clock BufferingShift registers are particularly sensitive to clock skew. The register operation could be incorrect due to set-up and hold problems.
clk
dd q
>ck qb
d q
>ck qb
d q
>ck qb
d q
>ck qb
d q
>ck qb
d q
>ck qb
clk
dd q
>ck qb
d q
>ck qb
d q
>ck qb
d q
>ck qb
d q
>ck qb
d q
>ck qb
70
Situations to be Avoided when Operating with the Asynchronous Reset
It is recommended to avoid driving the asynchronous reset input of one flip-flop using the output of the other.
d q
>ck qb
d q
>ck qb r
clk
d q
>ck qb
clk
CombinationalLogic
d q
>ck qb r
71
The Recommended Solution for flip-flops with Synchronous Reset
c lk
d q
>ck qb r
d q
>ck qb r
d q
>ck qb r
d q
>ck qb r
rese t
A signal conflict may arise at the interface between a synchronous circuit and an external asynchronous input. It is recommended to synchronize an asynchronous input by passing it through one or more flip-flops.
Synchronizing Asynchronous Inputs
d q
> c k q b
d q
> c k q b
d (e x te rn a l) d ( in te rn a l)
c lk ( in te rn a l)
72
Adders and Multiplexersarchitecture arch of entity1 isbeginoutp <= a + b when sel = '0' else a + c ;
end arch ;a ab c
selMUX
73
Optimised Adder and Multiplexer Circuit
process (sel, a, b, c)variable in_add : std_logic_vector(5 downto 0);
beginif sel = '0' thenin_add <= b ;
elsein_add <= c ;
end if ;outp <= a + in_add ;
end process ;a
b c
sel MUX
74
Modelling Sequential CircuitsTo model sequential logic for synthesis, the clock signal must be used, following some recommendations:– Designate a signal as a clock through its behavioural description (using
IF or WAIT UNTIL statements).– Use at most one clock with at most one active edge.– All procedural statements must completed into a single clock cycle.– Data-dependent loops must be synchronised by clock.
Wait until clk'event and clk = ‘0' and clk'last_value = ‘1' ;
Wait until not clk'stable and clk = ‘0' ;Wait until clk'event and clk = ‘0’ ; Negative clock edge
Wait until clk'event and clk = '1' and clk'last_value = '0' ;
Wait until not clk'stable and clk = '1' ;Wait until clk'event and clk = '1' ; Positive clock edge
Modelling Clock Signals with WAIT Statements
75
Some Remarks on VHDL Design for SynthesisVHDL elements which are not synthesizable: AFTER, WAIT FOR, ASSERT, File operations, REAL signals.Write all input signals in the sensitivity list, otherwise they will be latched.CASE and IF statements must be complete. For std_logic signals the CASE statement needs “OTHERS” and IF needs ELSE. Avoid instantiating too many components because this worsens the size of optimised implementation. Avoid large combinational multipliers and dividers. When complicated equations are used, design the circuit so that all the operands share a single multiplier or divider.Do not use INTEGER without RANGE:
SIGNAL x: INTEGER RANGE 0 TO 255;76
AlgorithmHardware
architecture
?
Definition of a set of steps and rules of a design methodology
Definition of a set of steps and rules for the development of a design methodology
FPGA-based Controller Design main rules
Use of FPGAs for the control of industrial systems
77
Design Methodology
To ensure a more automated and less intuitive approach for the design of FPGA-based control systems
Objectives
Reduction of the development time
Development of a specific library of reusable modules dedicatedto the control of electrical systems
First attempt success guarantee of the designed architecture
78
Modular partitioningof the algorithm
Simulation procedure
Optimization of theconsumed resources
Architecture design
Validation of the architecture
Design Methodology
Different steps
79
Modèle continu
Discrete Model
Per Unit Dicrete Model
Example : dX/dt ≈ (X[k+1]-X[k])/Ts
X/Xb
Continuous Model
Design Methodology
Reduction of the development timeExtraction of reusable modules
Modular partitioning of the algorithm
80
Design Methodology
Continuous Model of a FOC Estimator
81
Φsq = Lsσisq
dθdq/dt = wdq
Φsd = Lsσisd + (Lm/Lr)Φr
Cem = (3/2)p(Lm/Lr) Φr isq
Wdq = w + Lmisq/(TrΦr)
Φr = Lm/(1+Trs) isd
isq =2/√3(sin(θ+150) is1 + cos(θ) is2)
isd =2/√3(sin(θ+60) is1 + sin(θ) is2)
Continuous Model of a FOC Estimator
Design Methodology
Simplification
82
Continuous Model
Discrete Model
Per Unit Discrete Model
Design Methodology
Euler: dX/dt ≈ (X[k+1]-X[k])/Ts
83
Φsq [k] = a9 isq [k]
θdq [k] = θdq [k-1] + a10 wdq [k-1]
Φsd [k] = a7 isd [k] + a8 Φr [k]
Cem [k] = a6 Φr [k] isq [k]
Wdq [k] =a4 w [k] + a5 isq [k] /Φr [k]
Φr[k]=a2 isd [k-1]+ a3 Φr[k-1]
isq[k]=a1(sin(θ[k]+150) is1[k] + cos(θ[k]) is2[k])
isd[k]=a0(sin(θ[k]+60) is1[k] + sin(θ[k]) is2[k])
Digital Model of a FOC Estimatora0 = 2/√3 a1 = 2/√3a2 = Lm Te/Tra3 = 1 - Te/Tra4 = 1a5 = Lm/Tra6 =(3/2)pLm/Lra7 = Ls σa8 = Lm/Lra9 = Ls σa10 = Te
Design Methodology
84
Continuous Model
Discrete Model
Per Unit Discrete Model
Design Methodology
85
Φsq[k] = A9 isq[k]
θdq[k] = θdq[k-1] + A10wdq[k-1]
Φsd[k] = A7 isd[k] + A8 Φr[k]
Cem[k] = A6Φr[k] isq[k]
Wdq[k] = A4 w[k] + A5 isq[k]/Φr[k]
Φr[k] = A2 isd [k-1] + A3 Φr[k-1]
isq[k] =A1(sin(θ[k]+150) is1[k] + cos(θ[k]) is2[k])
isd[k] =A0(sin(θ[k]+60) is1[k] + sin(θ[k]) is2[k])
Per Unit Digital Model of a FOC Estimator A0 = a0A1 = a1A2 = a2Ib/ΦbA3 = a3A4 = a4wb/wdqbA5 = a5Ib/(wdqbΦb)A6 = a6A7 = a7Ib/ ΦbA8 = a8A9 = a9Ib/ΦbA10 = a10wdqb
Design Methodology
86
abc to dqTransformation
(1)
Low PassFilter
(2)
ωdq, TL, Φsd et ΦsqEstimator
(3)Integrator
(4)
is1
is2
isd
isq
Φr
ωdqω
isd
θdq
TL Φsd Φsq
Design Methodology
Example 1 : FOC Estimator algorithm
Library
Modular partitioning of the algorithm
87
Table(1)
TL*
Isd*
Isq*
dq to abcTransformation
(2)
θ
HysteresisController
(3)
is1*
is2*
is3*
Sa
Sb
Sc
is1 is2 is3
Design Methodology
Example 2 : Sliding Mode Torque Control algorithm
Creation of a specific Electrical System dedicated library
Library
Modular partitioning of the algorithm
88
Design Methodology
Current Control, Torque Control Speed Control, …
Full Control AlgorithmsLevel 3Level 3
PI, PID, PPI, Hysteresis controller, …
Regulation
PWM, SVM, …
Modulation
abc-to-αβ, αβ-to-abc, abc-to-dq, dq-to-abc…
Vector Operators
PLL, Torque Estimator, Flux Estimator…Estimation
Level2Level2
Level 1Level 1Registers, multiplexers,
demultiplexers, …
Basic Operators
Adder, multiplier, sine-cosine, cordic, …
Arithmetic Operators
89
Design Methodology / Web Site
90
Library of IP modules dedicated to the Control of Electrical Systems
VHDL ProgramsMatlab Simulink ModelsData-sheets
Design Methodology
91
Design Methodology
Verification of the algorithm functionalitySimulation procedure
Modular partitioning of the algorithm
Choice of the suitable sampling period and fixed-point format
92
Design Methodology
Induction motor
IFO Controller +
VSI
Estimator algorithm
Example 1 : Per Unit FOC Estimator functional model
1) Development of a continuous functional continuous model
Verification of the algorithm functionality
93
Design Methodology
Torque control algorithm
VSI SM
Example 2 : Per Unit Sliding Mode Torque Control functional model
94
Design Methodology
Choice of the sampling period and fixed-point format of the digital algorithm
2) Development of a discrete fixed-point specification model
Example1 : FOC Estimator specification model
95
Design Methodology
Example2 : Sliding Mode Torque Control specification model
96
Design Methodology
Example2 : Sliding Mode Torque Control specification model
97
Design Methodology
dq-to-abc transformation specification model
Dq-to-abc transformation Data Flow Graph (DFG)
+ +
5π/6 π/3
+
π/2
Sin Sin Sin
x x
Sin
x x
isa[k] isb[k]
θdq[k]
+ +
x x
A0A1
isd[k]isq[k]
U[p/Q0]
U[p/Q0]
U[p/Q0] U[p/Q0] U[p/Q0]
U[p/Q0] U[p/Q0]
S[n/Qn-1]S[n/Qn-1] S[n/Qn-1] S[n/Qn-1]
S[n/Qn-2]S[n/Qn-2] S[n/Qn-2]
S[n/Qn-2] S[n/Qn-2] S[n/Qn-2]S[n/Qn-2]
S[n/Qn-1] S[n/Qn-1]
Lots of possibilities in terms of parallelism 98
Design Methodology
Reduction of the consumed resources
Simulation procedure
Modular partitioning of the algorithm
Optimization procedure
99
Design Methodology
A1
A2
x1
x2
y
S[n/Qn-1]
S[n/Qn-1] x
+
F F
J
S[n/Qn-1]
S[n/Qn-1]S[n/Qn-1] S[n/Qn-1]
S[n/Qn-1]
S[n/Qn-1]S[n/Qn-1]
S[n/Qn-1]
Factorization • Hardware resources• Execution time
Defactorization • Hardware resources• Execution time
S[n/Qn-1]
x1 A1 A2 x2
S[n/Qn-1]S[n/Qn-1]
S[n/Qn-1]S[n/Qn-1]
S[n/Qn-1]
y
x x
+
100
Design Methodology
Generation of optimized hardware architecture (A3 methodology)
FF0 : Factorization Frontier 0
FF1 : Factorization Frontier 1
14Sine
16Multiplication
35Addition
FDFGDFGOpérations
abc-to-dq transformation Factorized Data Flow Graph (FDFG)
F
0π/3π/25π/6
+
SinFD
A0A1
D
x F D
F
J
+ +
isa[k]
isb[k]
θdq[k]
isd[k]isq[k]
FF0
FF1
S[n/Qn-1]
U[p/Q0]
S[n/Qn-1]
U[p/Q0]
S[n/Qn-2]
U[p/Q0]
U[p/Q0] S[n/Qn-1]
S[n/Qn-2] S[n/Qn-1]
S[n/Qn-2]
101
Design Methodology
Simulation procedure
Modular partitioning of the algorithm
Optimization procedure
Architecture Design
102
Design Methodology
1) Modular Hardware Architecture Design
Inputs[k] Inputs [k+1] Inputs [k+2]
StartInput Data
Outputs [k] Outputs [k+1] Outputs [k+2]
EndOutput Data
Clk
TClkLatency*TClk
Data-path
Control unit
S1
Module name
Input Data Output Data
Start End
ClkReset
S2S3
S3
Generic Second Level Module Architecture
Generic Timing Diagram
Specific Library
103
Design Methodology
InputData
Global Data-path
OutputData
Module Name
Sub-Module 1
Start1 Start2 Start3 StartnEnd1 End2 End3 Endn
Start End
Clk
Sub-Module 3
Sub-Module 2
Reset
Sub-Module n
Global Control UnitSel en
Third Level Module Architecture
2) Design of the whole algorithm architecture
Specific Library
104
Design Methodology
Sequencer
Data-path
LP_Filter
isa
isb
isd
isq
Φr
ωdq
ω
isdθdq
ωdq, TL, Φsd and ΦsqEstimator
Sequencer
Data-pathabc-to-dq
transformation
Sequencer
Data-path
Integrator
Sequencer
Data-path
TL Φsd Φsq
Global data-path
Global sequencer
FOC Estimator Architecture
Example : FOC Estimator algorithm architecture
105
Design Methodology
3) VHDL coding of the architecture
106
System Level
Behavioral Level
RTL or Synthesis Level
Physical Level
Simulation Simulation
Synthesis
Behavioral HDL
Circuit Specifications
Simulation Simulation
Analog HDL
Test Bench
Mixed Simulation Environment
FPGA
ASIC
Design Methodology
3) VHDL coding – TOP DOWN Approach
107
Reuse and IP Behavioral Model
Blocks
LibraryLibrary
RTL or Synthesize Level
Physical Level
Behavioral Level
System Level
LibraryLibrary Reuse and IP RTL or Synthesize
Model Blocks
Design Methodology
3) VHDL coding - Reusability
108
Design Methodology
Simulation procedure
Modular partitioning of the algorithm
Optimization procedure
Architecture Design
Validation of the architecture
109
Design Methodology
FPGA Target
Configuration process
Stimuli Patterns
TxRx
Architecture to be tested
Serial interface
Host-PC Results Comparison Results
Reception
Simulation Results ‘Hardware in the loop’ Results
First attempt success guarantee
Functional model simulation
1) Hardware in the loop test
110
Design Methodology
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35-5
-4
-3
-2
-1
0
1
2
3
4
5
isd
isq
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35-5
-4
-3
-2
-1
0
1
2
3
4
5
isd
isq
Simulation results (isd(A) and isq(A)) Hardware in the loop results (isd(A) and isq(A))
time(s) time(s)
Example : Hardware in the loop results of the FOC Estimator
Start-up and a speed reversal at 0.27s of a 1 Kw induction machine controlled by a classical Indirect Field Oriented Strategy.
111
Design Methodology
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35-8
-6
-4
-2
0
2
4
6
8
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35-8
-6
-4
-2
0
2
4
6
8
Simulation results (T(Nm)) Hardware in the loop results (T(Nm))
time(s) time(s)
112
Design Methodology
Simulation results Φr(Wb)
time(s)0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Hardware in the loop results Φr(Wb)
time(s)0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Slight difference between simulation and hardware in the loop results
113
Design Methodology
2) Experimental test
FPGA (Actel Fusion) 114
Design Methodology
FPGA (Actel Fusion)
115
Conclusion
Algorithm Hardwarearchitecture
Design Methodology
Advantages :
• Less intuitive and more automatic approach
• Reduction of the development time
• Optimization of the consumed resources
• Reusability of the design
• Development of a specific library
• First attempt success guarantee116
FPGA-Based Current Controllers for
Synchronous Machine Drive
Advantages & Features
1st Case Studies Series:
117
Control Algorithm Execution Time
(a)
(b)
(c)
(k-1)Ts (k)Ts (k+1)Ts
(k-1)Ts
TADC
(k)Ts
(k+1)Ts
(k+1)Ts
TC
(k)Ts
(a)
(b)
(c)
(k-1)Ts (k)Ts (k+1)Ts
(k-1)Ts
TADC
(k)Ts
(k+1)Ts
(k+1)Ts
TC
(k)Ts
(a) General purpose microcontroller:- µc limitations !
(b) DSPcontroller:- VSI limitations
(c) FPGA-based controller:- Quasi-analog behavior
118
Experimental Set-up
InterfaceInterface
Vf
Amplification
Electrical SupplyElectrical Supply
ADC
Controlled Controlled InverterInverter
Synchronous MachineSynchronous Machine
Encoder
isbisb
θ
FPGAFPGA
Controller
Serial Interface
ADC Interface
isa
Sa Sb Sc
ReferencesRS232
isa isbADC Control
Host PC
isbisa
Encoder Interface
θdq
119
Voltage Source Inverter
Encoder
Current sensors
SM
Experimental Set-up
120
Experimental Set-up
FPGA Spartan3
400.000 GatesAD Conversion Board
VSI Interface
Board
121
Current Controllers Based on ON-OFF Regulators
122
Current Controllers Based on ON-OFF regulators
Simplest current regulation schemes
Tow Main groups
Variable switching frequency ON-OFF regulators
Limited switching frequency ON-OFF regulators
Well adapted for analog controls Well adapted for analog & digitalcontrols
123
Variable Switching Frequency ON-OFF regulators
Example 1 : Independent three phase free running hysteresis regulators
Sa
Vrd
SM
SbSc
isa*
isb*
isc*
isa isb isc
isd*
isq*
Encoder
θdq
dq-to-abc
p
E
124
Variable Switching Frequency ON-OFF regulators
Example 1 : Independent three phase free running hysteresis regulators
wait
Start_AD=’1’wait
End=’1’
Start_OO=’1’
Start=’1’
Reset
End_AD=’1’
Global control unit FSMGlobal control unit
ADInterface
dq-to-abc2 level hysteresis
comparators
isa*
isb*
isc*
isd*
isq*
Algorithm control unit
Start End
SaSb
Sc
isaAD
isbADAD Control
Clk Clk
ON-OFF Current controllerClk
θdq
Clk
isaisbisc
Clk
End_ADStart_AD
Start_OO End_OO
∆H
Hardware Architecture
TS = TAD = 2.4 µs
Tex= TAD+ tIP+ tH2 = 2.74 µs
Controller computation time
Ts
Tex
Application Sa,b,c[k-1]
tAD tIP tH2
tAD tIP tH2
tAD tIP tH2
Application Sa,b,c[k] Application
Sa,b,c[k+1]
Sample isa[k-1]isb[k-1] θdq[k-1]
Sample isa[k]isb[k] θdq[k]
Sample isa[k+1]isb[k+1] θdq[k+1]
125
Variable Switching Frequency ON-OFF regulators
Low execution time
Effects of sampling and delays are very negligible
∆H
∆isaisa
∆isaisa
∆H
Execution time = 50 Execution time = 50 µµss Execution time = 2.74 Execution time = 2.74 µµss
∆H
∆isaisa
∆H
∆isaisa
126
Variable Switching Frequency ON-OFF regulators
Low execution time
Effects of sampling and delays are very negligible
∆H
∆isa
isaisb
Execution time = 50 Execution time = 50 µµss Execution time = 2.74 Execution time = 2.74 µµss
∆H
∆isa
isa
isb
∆H
∆isb
∆H
∆isb
127
Variable Switching Frequency ON-OFF regulators
Sa
Vrd
SM
SbSc
isa*
isb*
isc*
isaisb isc
isd*
isq*
Encoder
θdq
dq-to-abc
p
E
Table
abc-to-αβ
abc-to-αβ
+-
+-
isα*
isβ*
∆isα
∆isβ
isα
isβ
∆isb<∆iscisa
*
isb*
isaisb
Example 2 : Space vector based regulator with three level hysteresis comparators and look-up table working in the α-β reference frame
128
Variable Switching Frequency ON-OFF regulators
Example 2 : Space vector based regulator with three level hysteresis comparators and look-up table working in the α-β reference frame
wait
Start_AD=’1’wait
End=’1’
Start_OO=’1’
Start=’1’
Reset
End_AD=’1’
Global control unit FSM
TS = TAD = 2.4 µs
Tex= TAD+ tIP +tC+ tH3+tT = 2.92 µs
Controller computation time
tAD tIP tC tH3 tT
tAD tIP tC tH3 tT
tAD tIP tC tH3 tT
Ts
Tex
Application Sa,b,c[k-1]
Application Sa,b,c[k]
Application Sa,b,c[k+1]
Sample isa[k-1]isb[k-1] θdq[k-1]
Sample isa[k]isb[k] θdq[k]
Sample isa[k+1]isb[k+1] θdq[k+1]
isα*
isβ*
isa*
isb*
isc*
dq-to-abc abc-to-αβ
abc-to-αβ
Sα
Sβ
isα isβ
3 level hysteresis comparators Table
isb* isc
* isb isc
Clk
isd*
isq*
θdq
AD Interface
isaAD
isbADAD Control
SaSb
Sc
∆hα&∆hβ
Global control unit
Algorithm control unit
Start End
Clk
Clk
Clk
isaisbisc|∆isb|<|∆isc|
Clk Clk
Clk
Clk
Clk
Start_OO End_OO
End_ADStart_ADON-OFF Current controller
Hardware Architecture
129
Variable Switching Frequency ON-OFF regulators
Low execution time
Effects of sampling and delays are very negligible
∆Hα
∆isα
isα
∆isβisβ
∆Hβ
Execution time = 50 Execution time = 50 µµss Execution time = 2.92 Execution time = 2.92 µµss
∆Hα
∆isαisα
∆Hβ
∆isβ
isβ
130
Variable Switching Frequency ON-OFF regulators
Low execution time
Effects of sampling and delays are very negligible
∆Hα
∆isα
isα
∆isαisα
∆Hα
Execution time = 50 Execution time = 50 µµss Execution time = 2.92 Execution time = 2.92 µµss
∆Hα
∆isαisα
∆Hα
∆isα isα
131
Limited Switching Frequency ON-OFF regulators
Example 1 : Independent three phase free running hysteresis regulators
Sa
Vrd
SM
Sb
Sc
isa*
isb*
isc*
isa isb isc
isd*
isq*
Encoder
θdq
dq-to-abc
p
ETs
132
Limited Switching Frequency ON-OFF regulators
Example 1 : Independent three phase free running hysteresis regulators
wait
Start_AD=’1’wait
End=’1’
Start_OO=’1’
Start=’1’
Reset
End_AD=’1’
Global control unit FSM
TS = tAD = 100 µs
Tex= tAD+ tIP+ tH2 = 2.74 µs
Controller computation time
Application Sa,b,c[k]
Sampleisa[k]isb[k] θdq[k]
Ts
FsStart
Tex
tAD tIP tH2 tAD tIP tH2
Ts
Sampleisa[k+1]isb[k+1] θdq[k+1]
Application Sa,b,c[k+1]
Global control unit
ADInterface
dq-to-abc2 level hysteresis
comparators
isa*
isb*
isc*
isd*
isq*
Algorithm control unit
Start End
SaSb
Sc
isaAD
isbADAD Control
Clk Clk
ON-OFF Current controllerClk
θdq
Clk
isaisbisc
Clk
End_ADStart_AD
Start_OO End_OO
∆H
Hardware Architecture
133
Limited Switching Frequency ON-OFF regulators
Low execution time
Effects of sampling and delays are very negligible
isa
Execution time = 50 Execution time = 50 µµss Execution time = 2.92 Execution time = 2.92 µµss
isa
THD=14.9% THD=8.9%
Square current vector error (∆isα²+∆isβ²) Square current vector error (∆isα²+∆isβ²)
134
Limited Switching Frequency ON-OFF regulators
Example 2 : Space vector based regulator with three level hysteresis comparators and look-up table working in the α-β reference frame
Vrd
SM
isa*
isb*
isc*
isaisb isc
isd*
isq*
Encoder
θdq
dq-to-abc
p
E
Table
abc-to-αβ
abc-to-αβ
+-
+-
isα*
isβ*
∆isα
∆isβ
isα
isβ
∆isb<∆iscisa
*
isb*
isaisb
Sa
Sb
Sc
Ts
135
Limited Switching Frequency ON-OFF regulators
Example 2 : Space vector based regulator with three level hysteresis comparators and look-up table working in the α-β reference frame
wait
Start_AD=’1’wait
End=’1’
Start_OO=’1’
Start=’1’
Reset
End_AD=’1’
Global control unit FSM
TS = tAD = 2.4 µs
Tex= tAD+ tIP +tC+ tH3+tT = 2.92 µs
Controller computation time
Ts
Application Sa,b,c[k]
Sampleisa[k]isb[k] θdq[k]
Fs
Start Tex
tAD tIP tC tH3 tT tAD tIP tC tH3 tT
Ts
Application Sa,b,c[k+1]
Sampleisa[k+1]isb[k+1] θdq[k+1]
isα*
isβ*
isa*
isb*
isc*
dq-to-abc abc-to-αβ
abc-to-αβ
Sα
Sβ
isα isβ
3 level hysteresis comparators Table
isb* isc
* isb isc
Clk
isd*
isq*
θdq
AD Interface
isaAD
isbADAD Control
SaSb
Sc
∆hα&∆hβ
Global control unit
Algorithm control unit
Start End
Clk
Clk
Clk
isaisbisc|∆isb|<|∆isc|
Clk Clk
Clk
Clk
Clk
Start_OO End_OO
End_ADStart_ADON-OFF Current controller
Hardware Architecture
136
Limited Switching Frequency ON-OFF regulators
Low execution time
Effects of sampling and delays are very negligible
isa
Execution time = 50 Execution time = 50 µµss Execution time = 2.92 Execution time = 2.92 µµss
isa
THD=11.1% THD=8.9%
Square current vector error (∆isα²+∆isβ²) Square current vector error (∆isα²+∆isβ²)
137
Current Controller Based on PI Controllers
138
Current Controller Based on PI Controllers
Sa
Vrd
SM
SbSc
Vsa*
Vsb*
Vsc*
isa isb isc
Vsd*
Vsq*
Encoder
θdq
dq-to-abc
p
E
PWM Modulator
dq-to-abc
isd
isq
isd*
isq*
+-
+-
139
Current Controller Based on PI Controllers
abc-to-dq
isd*
isq*
AD Interfaceis1AD
is2AD
AD Control
Global control unit
Algorithm controller
StartEnd
Clk
Clk
Clk
Vector current controller
isaisb
Clk
Start_VC End_VC
End_ADStart_AD
PIClk
Clk
PI
dq-to-abc
Clk
Vsd*
Vsq*
PWM
Vsa*
Vsb*
Vsc*
Clk
θdq
Sa
Sb
Sb
isqisd
Hardware Architecture140
Current Controller Based on PI Controllers
Case 1 : Synchronized PWM
Application Vsa,b,c
*[k]Sampleisa[k]isb[k] θdq[k]
tPWM/2Tex tPWM/2
Carrier
Start
End_VC
Ts = tPWM/2
tAD tVC tAD tVC tAD tVC
Application Vsa,b,c
*[k+1]Sampleisa[k+1]isb[k+1] θdq[k+1]
Application Vsa,b,c
*[k+2]Sampleisa[k+2]isb[k+2] θdq[k+2]
TS = TPWM / 2 Tex= tAD+ tVC = 3.28 µs
Vector Control computation time
141
Current Controller Based on PI Controllers
Case 1 : Synchronized PWM
11 >
2 >
1) Ch 1: 200 mVolt 250 us 2) Ch 2: 2 Volt 250 us
Carrier
Ts
11 >
2 > 1) Ch 1: 200 mVolt 10 us 2) Ch 2: 2 Volt 10 us
1 >
2 > 1) Ch 1: 200 mVolt 10 us 2) Ch 2: 2 Volt 10 us
Carrier vertex
Start End_VCTex Start End_VCTex
Carrier vertex
142
Current Controller Based on PI Controllers
Case 2 : Non Synchronized PWM
Application Vsa,b,c
*[k]Sample
isa[k]isb[k] θdq[k]
tk tk+1 tk+2 tk+m tk+m+1 tk+m+2
Tex
Carrier
Ts
Application Vsa,b,c
*[k+m]Sampleisa[k+m]isb[k+m] θdq[k+m]
11 >
2 >
1) Ch 1: 200 mVolt 2.5 us 2) Ch 2: 1 Volt 2.5 us
Start End_VC
Carrier
Ts Tex
TS = 5 µs Tex= tAD+ tVC = 3.28 µs
Vector Control computation time
143
Current Controller Based on PI Controllers
isa
THD=11.1%
isbCarrier Frequency = 1KHz
Carrier Frequency = 1KHz
THD=11.1%
isa
Carrier Frequency = 3KHz
isa
isb
isa
isb
Experimental Results
THD=4.1%
144
Current Controller Based on PI Controllers
Experimental Results
11 >
2 >
1) Ch 1: 1 Volt 25 ms 2) Ch 2: 1 Volt 25 ms
isd
isq
Vsa
Vsb
145
Predictive Current Controller
146
Predictive Current Controller
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
−+⎥
⎦
⎤⎢⎣
⎡
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
−−
−=
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
rd
sq
sd
dqsq
sr
sq
sd
sq
sd
sqdq
sq
sd
dqsq
sd
sd
sq
sd
iVV
tLM
L
Lii
Tt
LL
tLL
T
dtdidt
di
)(10
001
1)(
)(1
ωω
ω
Sate model of the synchronous machine in the dq rotor reference frame
Digital Prediction Equations
⎩⎨⎧
+=−=
⎪⎪⎩
⎪⎪⎨
⎧
−+−=+
−+−=+
][][][][][][][][
][)1(])[][(]1[
][)1(])[][(]1[
kikMkikLkekikLke
where
kiTT
kekVLT
ki
kiTT
kekVLT
ki
rddqsrsddqsdsq
sqdqsqsd
sqsq
ssqsq
sq
ssq
sdsd
ssdsd
sd
ssd
ωωω
147
Predictive Current Controller
⎥⎥⎦
⎤
⎢⎢⎣
⎡⎥⎦
⎤⎢⎣
⎡−
=⎥⎥⎦
⎤
⎢⎢⎣
⎡j
s
js
dqdq
dqdqj
sq
jsd
VV
VV
β
α
θθθθ
)cos()sin()sin()cos(
7 different stator voltage vectors Vsdqj=[Vsd
j Vsqj]t (j=0..7)
7 different directions tj(j=0..7) and errors ∆j(j=0..7)
⎩⎨⎧
+=−=
⎪⎪⎩
⎪⎪⎨
⎧
−+−=+
−+−=+
][][][][][][][][
][)1(])[][(]1[
][)1(])[][(]1[
kikMkikLkekikLke
where
kiTTkekV
LTki
kiTTkekV
LTki
rddqsrsddqsdsq
sqdqsqsd
sqsq
ssq
jsq
sq
sjsq
sdsd
ssd
jsd
sd
sjsd
ωωω
]1[][]1[ * +−=+∆ kikiki jsdqsdq
jsdq
rrr][]1[][ kikikt sdq
jsdqj
rrr−+=
148
Predictive Current Controller
d
q
isdq[k]
isdq*[k]
t0,7 t4
t5
t6t2
t3
t1
∆isdq1[k+1]
isdq1[k+1]
isdq[k]isdqj[k+1]
isdq*[k]
∆isdqj[k+1]
tj[k]
Predicted current error vector Predicted current error vector ∆∆isdqisdqjj Example of different prediction possibilitiesExample of different prediction possibilities
149
Predictive Current Controller
SM
Vrd
θdq
Optimization
E
isd*
isd
isq
esd esq
ωdq
(∆isdqj)(j=0..7)
Sa
Sb
Sc
Prediction
Couplingterms
isq*
pθm
d/dt
isa
isbabc-to-dq
Predictive Controller Principle
150
Limited Switching Frequency ON-OFF regulators
Hardware architecture
wait
Start_AD=’1’wait
End=’1’
Start_OO=’1’
Start=’1’
Reset
End_AD=’1’
Global control unit FSM
TS = 100 µs
Tex= tAD+ tPr = 4.52 µs
Predictive Controller computation time
AD Interface
isaAD
isbADAD Control
SaSb
Sc
Global control unit
Algorithm controller
Start End
Clk
ClkPredictive current controller
Start_Pr End_Pr
End_ADStart_AD
EAD
abc-to-dq
Clk
Couplingterms
Clk
Prediction& optimization
Clk
isd*
isq*
E
isd
isq
esd
esq
Clk
Speed Estimator
Clk
p
θoffset
θdq
++
θm
isa
isb
ωdq
Application Sa,b,c[k]
Sampleisa[k] isb[k] θdq[k]
FsStart
Ts
Tex Ts
tAD tPr tAD tPr
Sampleisa[k+1]isb[k+1] θdq[k+1]
Application Sa,b,c[k+1]
151
Current Controller Based on PI Controllers
Experimental Results
isa
THD=8.8% isb
THD=8.8%
isa
isa
isb
Vsa
Vsb
152
Current Controller Based on PI Controllers
Experimental Results
+ Isn
- Isn
+ Isn
- Isnisd
isq
isd
isq
153
FPGA-Based speed control for
Synchronous Machine Drive using PPI controller
154
Problem Positioning
Objective : Development of a high performance FPGA-based speed controller
Most important criteria for the speed control
Fast speed dynamic
Accurate speed response
Quick speed recovery from disturbances
155
Speed Controller Design
Vsd
isd
Vrd
ird
Vsqisq d
q
θdq Sa
ωdq
sqsd
sdssd dtd
iRV ωφφ
−+=
sdsq
sqssq dtd
iRV ωφφ
++=
rdsrsdsdsd iMiL +=φ
sqsqsq iL=φ
sdsrrdrdrd iMiL +=φ
)(23
sdsqsqsde iipT φφ −=
Synchronous machine model
156
Speed Controller Design
Current controller
Sa
Vrd
SM
Sb
Sc
isa*
isb*
isc*
isa isb isc
isd*
isq*
Encoder
θdq
dq-to-abc
p
E
157
Speed Controller Design
Current controller
Current Controller Timing Diagram
TAD TCC TAD TCC
Ts=100 µs Ts=100 µs
tk tk+1
Tex=2.74µs
Sample isa,b[k]θdq[k]
tk+Tex
Application Sa,b,c[k]
tk+1+Tex
Sample isa,b[k+1]θdq[k+1]
Application Sa,b,c[k+1]
time
isa isb
isa
isb
isq
isd
Isn
- Isn
158
Speed Controller Design
Speed controller synthesis
Current Control Loop
Speed Control LoopInternal Loop (Proportional controller)
External Loop (PI controller)
isq1
1+sT isq
KvPIω* +-
+-
ωωiisq
*
pMsrird-+
fJsp+
Tr
159
Speed Controller Design
Speed controller synthesis
Internal Loop (Proportional Controller)
Impose the controlled system poles at the desired positions
Internal speed control loop transfer function
isq
rdsrv
isq
isq
rdsrv
i
JTiMpKs
Ts
JTiMpK
²5.11²
²5.1
++=
ωω
ξ=1
Proportional Gain
2)2
1(
1
isq
i
Ts +
=ωω
Re
Im
ξ=1
Roots Locus 160
Speed Controller Design
Speed controller synthesis
PIω* +-
ω2)2
1(
1
isqTs +
External Loop (PI Controller)
- Zero steady-state error
- Impose the shape and the dynamic of the speed response
External speed control loop transfer function
isq
rdsrvp
isq
isq
rdsrvp
JTiMpKK
sT
s
JTiMpKK
²5.12
1²
²5.1
*ω
ω
ωω
++=
isq1
1+sT isq
KvPIω* +-
+-
ωωiisq
*
pMsrird-+
fJsp+
Tr
2ξωn ωn2
161
Speed Controller Design
Speed controller synthesis
Current Controller
Speed ControllerSa
400V/50Hz
Vrd
SM
Sb
Sc
isa*
isb*
isc*
isa isb isc
isd*
0
isq*
Kv
Encoderd/dt
Speed Estimator
θdq
dq-to-abc+
-
+
-ω*
Internal Loop
External Loop
162
Speed Controller Design
Speed estimator design
)]1[][
(1024
4][T
kkk mm −−=
θθπω
SM1024 points
Absolute Encoder
10 bits(P9 P8…..P1 P0)
Backward difference
Variable sampling periodOperating mode synchronized with state changes of the LSB of theencoder
+ 1
kTSensek 1
10244][ πω =
Denotes the time spent for one unit displacement of the encoder
Determined via the state changes of the two LSB P0 and P1
163
Speed Controller Design
Speed estimator design
P0Counter 0 1 2 nk 0 1 2 nk+1
Tk T(k+1)
1/Fc
c
kk F
nT =
Tk ComputationSense Computation
-1(negative)1011
+1(positive)0011
-1(negative)0110
+1(positive)1110
-1(negative)0001
+1(positive)1001
-1(negative)1100
+1(positive)0100
SenseP1[k+1]P0[k+1]P1[k]P0[k]
kTSensek 1
10244][ πω =
Denotes the time spent for one unit displacement of the encoder
Determined via the state changes of the two LSB P0 and P1
164
Speed Controller Design
Speed estimator design
Speed Estimator Hardware ArchitectureSpeed Estimator Hardware Architecture
Compteur
nk
Fcompt
Rc
- +
0en2
en3
ω
en0
en1
en0
en1
Sense Computation
XORd0
P0 P1
ETAT0
ETAT1en0=’1’
ETAT2Fcompt=’1’
Sω
|ω|
-|ω|
ETAT3en2=’1’
ETAT4en3=’1’
ETAT5en1=’1’Rc=’1’
Reset
Clk Start=’1’
Clk
Clk
Clk d0=’0’
d0=’1’
Clk
Clk
Clk
kTSensek 1
10244][ πω =
Data-Path
Control Unit
165
Speed Controller Design
Speed controller architecture
Speed Controller Timing Diagram
TAD TCC TAD TCC
Ts=100 µs Ts=100 µs
tk tk+1
Tex=3.45µs
Sample isa,b[k]θdq[k]
tk+Tex
Application Sa,b,c[k]
tk+1+Tex
Sample isa,b[k+1]θdq[k+1]
Application Sa,b,c[k+1]
time
FPGA-based Speed controller
Global control unit
Speed controller control unit
AD InterfaceP-PI
(dq/123)3 Phases hysteresis controller
Speed estimator
²θm
θoffsetθ
ω
Clk Clk Clk Clk
Clk
C1C2C3
Clk
Clk
isd*=0
ω*
Start End
is1 is2 is3
is1_ADis2_AD
AD control
isq*
is1*
is2*
is3*
TSCTSC
Note : The speed estimator works independently from the other modules and is synchronized to the state changes of the LSB of the encoder
166
Speed Controller Design
InterfaceInterface
Vrd
Amplification A/DEncoder
isbisc
θdq
FPGAFPGA
Speed Controller
Serial Interface
AD Interface
isa
Sa Sb Sc
ReferencesRS232
isa isbAD Control
Host-PC
isaisb
Spartan3 Xc3s400 (400.000 gates)
400V/50Hz
Experimental Set-up
167
Speed Controller Design
Experimental Results
Step Speed Response Speed tracking performance
ω=200 rad/s
ω=0 rad/s
ω=-200 rad/s
ω=200 rad/s
ω=-200 rad/s
ω=200 rad/s
ω=200 rad/s
ω=0 rad/s
168
Speed Controller Design
Experimental Results
isa
isb
Current waveforms
isa
isb
Current waveforms for a reversal speed operation
Response to a step of a rated load torque
TL=5Nm
169
Conclusions
A full FPGA-based speed controller for SM drive has been presented
A very efficient P-PI speed regulator has been synthesized
An original speed estimator has been developed, it allows to obtain the best accuracy
An original speed estimator has been developed, it allows to obtain the best accuracy
The obtained experimental results give proof of the ability of the developed speed control system to achieve an efficient and robust speed control under different operating conditions
170
Induction Motor Experimental Set-up
IMIM400V/50Hz
LOAD
Encoder
10
AD Control
ReferencesRS232
12
12
Gate pulses
AD Interface
UART
isaisbisc
θ
FPGA
ADcontrolleralgorithm
VSI Interface
Induction Motor Experimental Set-up
VSIInterface
and Control Boards
IM
L E
Laboratoire Systèmes Électriques172
Induction Motor Experimental Set-up
VSI Interface
Board
AD Converters Board
FPGA Spartan 2
100.000 Gates
173
Induction Motor Experimental Set-up
Load Incremental Encoder
Induction Machine
Load Control VSI
University of Aleppo
174
Induction Motor Experimental Set-up
VSI Interface Board
ADC Board
FPGA Spartan 3 400.000 Gates
175
2nd Case Studies Series:
FPGA-based Intelligent Controllers for AC Drives and AC Generators:
* A PWM control system modelling / design / FPGA implementation using VHDL
Modelling an induction motor drive system using an FPGA PWM neural controller
Modelling a diesel driven generator employing fuzzy-logic/PWM FPGA control
176
* PWM Control System Design Using VHDL
SYNCHRONISATION: (Carrier-triangular / M odulator-sinusoidal)Counter output bus
Triangular waveform generator M ax_count
M ax_count Clock (Reversible up-down counter)
Start Reset OUT_SIGNAL CONTROL COM PARATOR
Clock (PW M )
Next Address M emory generator
(Sinewave)
177
Three-Phase Sinusoidal PWM Pattern Generation
178
Block diagram of the 3-phase PWM circuit
179
Complete VHDL Code - 1 Phase PWM Generatorlibrary ieee;use ieee.std_logic_1164.all;entity pwm is
port(out_signal: out std_logic;clock,start: in std_logic;Max_count: in integer);
end pwm;architecture behav of pwm is
signal counter_out_bus : integer;signal next_pulse,reset: std_logic;signal val_max, adr, data: integer;
begincounter_rev: process(clock,reset)
variable direction: std_logic :='1';variable v: integer :=0;
beginif reset'event and reset='1' then
v:=1;elsif clock'event and clock='1' then
if direction='1' thenif v<val_max then v:=v+1;
elsev:=v-1;direction:='0';
end if;elseif v>-val_max thenv:=v-1;
elsev:=v+1;direction:='1';
end if;end if;
end if; counter_out_bus<=v;end process;adr_gen: process (next_pulse,reset) 180
beginif adr >=0 and adr<18 then
data<=d(adr);else
data<=0;end if;
end process;control: process(start,clock,counter_out_bus,
Max_count)variable temp_Max_count: integer;
begin if Max_count'event then
temp_Max_count:=Max_count;end if;
if start='1' and start'event thentemp_Max_count:=Max_count;val_max<=temp_Max_count;reset<='1';next_pulse<='0';
elsif start='1' and clock='0' andclock'event then
beginif reset='1' then
adr<=0;elsif next_pulse'event and
next_pulse='1' thenadr<=(adr+1) mod 18;
end if;end process;comparator:
process(counter_out_bus,data)begin
if data<counter_out_bus thenout_signal <= '0';
elseout_signal <= '1';
end if;end process;memory: process(adr)type mem_data is array (0 to 17) of integer;variable d : mem_data :=(-250,-230,-190,-100,0,100,190,230,250,250,230, 90,100,0,-100, -190,-230,-250);
181
architecture arch_test of test iscomponent pwm
port(out_signal : out std_logic;clock,start: in std_logic;Max_count: in integer);
end component;signal clock: std_logic :='0';signal start: std_logic := '0';signal Max_count: integer;signal out_signal: std_logic;
beginMax_count<=300, 500 after 40 ms;clock <= not clock after 1 us;start <= '1' after 5 ns;
x: pwm port map(clock=>clock,start =>start, Max_count=>Max_count,
out_signal=>out_signal);end arch_test;configuration conf_test of test is
for arch_testend for;
end conf_test;
reset<='0';end if;if counter_out_bus=-val_max and
clock='0' and clock'event thennext_pulse<='1';val_max<=temp_Max_count;
elsif clock='1' thennext_pulse<='0';
end if;if start='0' then
reset<='1';end if;
end process;end behav;library ieee;use ieee.std_logic_1164.all;entity test isend test;
end behav;
182
Simulation Results of the 3-phase PWM circuit
183
Achievements• Original design of a 3-phase PWM generator, successfully modelled, designed and simulated using VHDL.
•Important original aspect = the (64x2) ROM, efficiently targeted by a three-way routing circuit.
•The functional simulation results proved the correct controller operation, followed by practical tests that validated the circuit.
•A plethora of other synchronous and asynchronous modes can be tested, since the circuit is very flexible in producing a range of carrier frequencies between 5 KHz to 427 KHz.
•The amplitude modulation index, which was set to 1 for this particular test, can be varied in the full range between 1 and 0.
•In terms of silicon usage, the circuit proposed is the optimum choice. The memory size is the minimum one required to efficiently describe the 0-phase sinewave. 184
1. Modelling of an induction motor drive system using PWM neural controller
185
The RLe Equivalent Circuit of the Induction Motor
( )[ ] ( )
⎪⎪⎪⎪
⎩
⎪⎪⎪⎪
⎨
⎧
==
Ψω+−=+ω+−=
=
−=
s
s
srer
srr
r
mssm
srrer
srr
r
m
s
r
2mrs
iiuu
jiRLLiLiLjiR
LLe
RRL
LLLL
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The Neural PWM Controller
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Speed Control PrinciplesThe control is achieved in polar coordinates (module and angle).The rotor speed is controlled by compensating the slip frequency.Slip frequency is kept constant for any load torque & any rotor speed.The slip frequency depends on the angle α between e and is,,, controlled by means of:
* stator frequency* stator current amplitude
The current amplitude Is is corrected according to the position of vector ein the complex plane.The stator frequency fs follows the reference speed profile. Very fast stator frequency changes have to be avoided because they cause slow transient response.
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Basic Control Algorithm
Improved Control Algorithm
Simulation
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Neural PWM Controller –VHDL Design for Implementation
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Simulation /Test Results – PWM Neural Controller
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Test Results - Motor
Speed control at step torque riseControlled versus natural torque characteristic
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Achievements
Induction motor drives can be controlled using neural algorithms, implying a smaller number of calculations than vector control.
The proposed speed control algorithm can be expressed as a set of mathematical equations written in polar co-ordinates.
The angle and sector calculations are carried out by hardware implemented neural networks.
The entire control scheme has been modelled and designed in VHDL, synthesised and implemented into Xilinx XC4010 FPGA.
The implementation offers a cost-effective solution for industrial applications without high dynamic requirements.
Test results have confirmed correct operation of the controller.
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2. MODELLING A STAND ALONE DIESEL DRIVEN GENERATOR SET USING
FUZZY-LOGIC AND PWM CONTROL
SynchronousGenerator
Diesel Engine
PWM ControlPWM ControlFuzzyFuzzy ControlControl
VDC
Fuel Control
RECTIFIER PWM INVERTER
C
STAND-ALONE
GENERATOR
3 phaseoutput
FPGA FPGA ControllerController
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Project Background♦In a given synchronous machine the operational speed is dependent onthe desired output frequency.
♦Variable speed operation of generators increases design freedom: speedis not determined by the desired electrical frequency.
♦It allows engine-generators systems to be operated at speeds whichoptimise desired parameters such as noise, vibrations, fuel efficiency, engine emissions.
♦The research aim is to design and build a control system for a stand alone variable speed PM synchronous generator.
♦This has been developed on the basis of fuzzy logic, using VHDL and is implemented in Xilinx FPGA.
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PWM Inverter Simulation Results
-300
0
300
600Vout
Vdc
time [ms]196
Fuzzy Variable Speed Governor• Fuzzy Variable Speed Governor (FVSG) - controller based on fuzzy logic.
• Designed using VHDL for easy correction and future integration with othercomponents to extend the system.
•System configuration allows variable speed operation of the generator.
valve engine generator rectifier inverter
Fuzzifier
FuzzyInferenceMachine
Fuzzy Rule Base
Defuzzifier
xx 11
xx 22
a.c.output
FVSGFVSG
PWMControl
ddt
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DC Voltage Fuzzy Controlled Response to Load Current Step Increase
0
200
400
600
800
1000
1200
1400
1 21 41 61 81 101 121 141 161 181 201 221 241 261 281 301 321 341 361 381
ILOAD =10A
ILOAD =20A
DC Voltage (Normalised to 1000)
Load Current
Reference Voltage
time (sampling units)
Voltage (normalised)
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050
100150200250300350
0 5 10 15 20 25 30 35 40 45
time [sec]
d.c.
vol
tage
[vol
t]
Experimental Test Results
050
100150200250300350
0 5 10 15 20 25 30 35 40 45
time [sec]
d.c.
vol
tage
[vol
t]
Without controller With controller
Step Change in a.c. Load Current – d.c. Voltage response
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AchievementsPWM controller
•voltage control using PWM is a simple and effective strategy forobtaining and maintaining the desired output voltage parameters.
Fuzzy logic•an effective design solution for the speed governor.•able to produce a competent control system without the need for a precise mathematical model of the plant.•the controller is reconfigurable by changing the rule base.•design can be easily extended to include more parameters.
VHDL•design, modelling & simulation performed on a single platform•the same design tool can be used for hardware implementation•reusable design modules are produced•new developments of the design can easily be performed
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General Conclusions•A novel modelling technique is proposed for the holistic investigation of engineering systems. This is based on Hardware Description Languages (VHDL).
•The sample systems were developed from idea, through modelling / simulation, to complete systems commissioning, in short time, giving further advantages:
easy integration of electronic controllers in complex engineering system models. reliable framework for design verificationhigh confidence in correct first time operation allows rapid FPGA prototyping of electronic controllersgives multiple choices for controller’s final implementation technologyhigh degree of flexibility
•A CAD platform independent model & design are developed and therefore valuable IPs can be produced, in co-relation with the modern principles of design reuse.
•Concurrent engineering basic rules (unique EDA environment and common design database) are fulfilled.
•Estimation: HDL based holistic modelling methodologies will be increasingly used in the future and expanded to encompass other areas of engineering systems.
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Recent DevelopmentsHandelHandel--CC – a novel compiler for Hardware-Software co-design from Celoxica.
C/C++ System ModelHandel-C compiler Assembly code compiler
VHDL hardware description Microprocessor software code
RosettaRosetta is a language for modelling/describing engineering systems– Presently the focus is on complex electronic systems -> SOC– Being explored for complex mechanical systems– Defines systems by writing and composing models with respect to domains.– Consists of a syntax (a set of legal descriptions) and a semantics (a meaning
associated with each description)
MilleniumMillenium MachineMachine – new EPSRC (UK) funding initiative for holistic modelling of engineering systems (systems of systems). 202
General Conclusions
• The simultaneous increase of the control algorithm complexity and the chip density implies the use an efficient design methodology. • A modeling technique is proposed for the holistic investigation of power electronic systems. This is based on System Level Modeling Languages or HDL and allows rapid FPGA prototyping of the control systems.• Three main design rules are presented.
• the algorithm refinement, • the modularity, • the systematic search for the best compromise between the control performances and the architectural constraints (see A3 section).
• Full and timely examples are presented to illustrate the benefits of FPGA implementation when using the proposed design approach. • It is demonstrated that in both cases a low cost FPGA-based controller can greatly improve the control performance, especially due to the reduction of execution time, while keeping a high level of flexibility.
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Perspectives• In the near future, the complexity of the control systems will continue to grow.
• The tasks devoted to the control algorithm will no longer be limited to regulation but will have to manage diagnosis and fault-adaptive on line control.
• The research effort on the theory and the applications of dynamic reconfiguration is crucial.
• Network-on-a-Chip (NoC)• SoC design that can include digital control and its analog interface (sensors, ADC, power drivers, etc.).
• Co-design issue must be addressed, since the borders between software and hardware are rapidly vanishing. The main problem in this case is to propose automatic rules of partitioning, based on relevant
quantitative indicators.
• Another interesting direction of research is based on the following observation: a control algorithm, when implemented in an FPGA, can have a very short execution time due to the high degree of parallelism of its architecture. At the same time, the constraints imposed by the power electronic components imply a sampling period that is much higher than the execution time. The resulting “wasted time” could be advantageously employed.
• Several examples of relevant FPGA utilizations in this context were presented. They consist of predictive control, over-sampling strategies, multi-plants control, etc. All these very promising control paradigms must still be improved.
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Bibliography•M.N. Cirstea, A. Dinu, J. Khor, M. McCormick, "Neural and Fuzzy Logic Control of Drives and Power Systems", Elsevier Science Ltd., 2002.•M.N. Cirstea, A. Dinu, D. Nicula: "A Practical Guide to VHDL Design", EdituraTehnica, Bucharest, Romania, 2001, ISBN: 9733115398.•A. Dinu: "FPGA Neural Controller for Three Phase Sensorless Induction Motor Drive Systems", PhD Thesis, De Montfort University, 2000.•J. Khor, "Intelligent Fuzzy Logic Control of Generators", PhD Thesis, De Montfort University, UK, 1999.•A. Zregh: “Holistic Modelling of Stand Alone Generators”, MPhil thesis, De Montfort University, UK, 2003. •B.K Bose: “Modern Power Electronics & AC Drives”, Prentice Hall, 2002.•M. P. Kazmierkowski, R. Krishnan, F. Blaabjerg, J. D. Irwin (Editors): “Control in Power Electronics: Selected Problems”, Academic Press, 2002. •D.L. Perry: "VHDL", McGraw-Hill, 1998.•Xilinx home page: http://www.xilinx.com/•Celoxica home page: http://www.celoxica.com/•Rosetta home page: http://www.sldl.org/
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