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Interconnect Delay Models
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Basic Circuit Analysis Techniques
• Output response
• Basic waveforms – Step input
– Pulse input
– Impulse Input
• Use simple input waveforms to understand the impact ofnetwork design
Network structures & state
Input waveform & zero-states
Natural response v N (t)(zero-input response)
Forced response v F (t)(zero-state response)
For linear circuits: )()()( t vt vt v F N +=
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unit step function
u(t)= 0
1
0<t
0≥t
1
pulse function of width T
0
1/ T
-T/2 T/2
−−+= )
2()
2(
1)(
T t u
T t u
T t P T
unit impulse function
∫ − =
>
=
≠=→
ζ
ζ δ
ζ
δ
δ
1)(
0anyfors.t.
0forsingular
0for0)(
0when)(:)(
dt t
t
t t
T t P t T
dt t duδ(t)
dx xt ut
)(or
)()(
definitionBy
=
= ∫ ∞−δ
Basic Input Waveforms
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• Definitions:
– (unit) step input u(t) (unit) step response g(t)
– (unit) impulse input δ(t) (unit) impulse response h(t)
• Relationship
• Elmore delay
∫ ∫ =→=
=→=
∞−
t t
dx xht g dx xt u
dt
t dg t h
dt
t dut
0)()()()(
)()(
)()(
δ
δ
Step Response vs. Impulse Response
(Input Waveform) (Output Waveform)
∫ ∫
∞ ∞⋅=⋅=
0 0
)()(' dt t t hdt t t g T D
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Analysis of Simple RC Circuit
)()()(
)())(()(
)()()(
t vt vdt
t dv RC
dt
t dvC
dt
t Cvd t i
t vt vt i R
T
T
=+⇒
==
=+⋅
first-order linear differential
equation withconstant coefficients
statevariable
Input
waveform
±v(t)C
R
v T (t)
i(t)
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Analysis of Simple RC Circuit
0)()(
=+ t vdt
t dv RC zero-input response:
(natural response)
step-input response:
match initial state:
output responsefor step-input:
v 0
v 0 u(t)
v 0 (1-e RC/T )u(t)
RC t
N Ke(t)v RC dt
dv(t)
v(t)
−
=⇒−=
11
)()()(
0 t uvt v
dt
t dv RC =+
)()()()( 00 t uv Ket vt uvt v RC t
F +=⇒=−
)()1()( 0 t uevt v RC t −
−=
0)( 0)0( 0 =+⇒= t uv K v
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Delays of Simple RC Circuit
• v(t) = v0
(1 - e-t/RC) under step input v0
u(t)
• v(t)=0.9v0 ⇒ t = 2.3RCv(t)=0.5v0 ⇒ t = 0.7RC
• Commonly used metricTD = RC (Elmore delay to be defined later)
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Lumped Capacitance Delay Model
• R = driver resistance
• C = total interconnect capacitance + loading capacitance
• Sink Delay: td
= R·C
• 50% delay under step input = 0.7RC• Valid when driver resistance >> interconnect resistance
• All sinks have equal delay
driver
3 N
2 N
+ N
Rd
Cload
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( )g0d
gintdloaddD
CLCR
CCRCRt
+⋅⋅=
+⋅=⋅=
driver
3 N
2
N
+ N
Lumped RC Delay Model
• Minimize delay ⇔ minimize wire length
Rd
Cload
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Delay of Distributed RC Lines
......!4!2
1
2)cosh(
cosh
1)(
42
+++=
+
=
=
−
x x
ee
x
sRC s sV
x x
out
V out (t) V out (s)Laplace
Transform
RVIN VOUT
C
VOUTVIN
R
C
0.5
1.0
VOUT
DISTRIBUTED
LUMPED
1.0RC 2.0RC time
Step response of distributed and lumped RC networks.
A potential step is applied at VIN, and the resulting VOUT
is plotted. The time delays between commonly usedreference points in the output potential is also tabulated.
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Delay of Distributed RC Lines (cont’d)
Output potential range Time elapsed
(Distributed RCNetwork)
Time elapsed
(Lumped RCNetwork)
0 to 90% 1.0 RC 2.3 RC
10% to 90% (rise time) 0.9 RC 2.2 RC
0 to 63% 0.5 RC 1.0 RC
0 to 50% (delay) 0.4 RC 0.7 RC
0 to 10% 0.1 RC 0.1 RC
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Distributed Interconnect Models
• Distributed RC circuit model
– L,T or Π circuits
• Distributed RCL circuit model
• Tree of transmission lines
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Distributed RC Circuit Models
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0 Z
0 Z
Distributed RLC Circuit Model
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Delays of Complex Circuits under Unit Step Input
• Circuits with monotonic response
• Easy to define delay & rise/fall time
• Commonly used definitions
– Delay T 50% = time to reach half-value, v(T 50% ) = 0.5V dd
– Rise/fall time T R = 1/v’(T 50% ) where v’(t): rate of change of v(t)
w.r.t. t – Or rise time = time from 10% to 90% of final value
• Problem: lack of general analytical formula for T 50% &
T R !
t
1
0.5
v(t)T 50%
T R
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t
Delays of Complex Circuits under Unit StepInput (cont’d)
• Circuits with non-monotonic response
• Much more difficult to define delay & rise/fall time
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)(of changeof rate:)('
(monotone)responseoutput:)(
t vt v
t v
0.5
1
T 50%
v(t)
t
t
v’(t)
medianof v’(t)
(T 50% ) v'(t)
dt t tvT D
of mean
)('0∫ ∞
=
Elmore Delay for Monotonic Responses
• Assumptions:
– Unit step input
– Monotone output response
• Basic idea: use of mean of v’(t)to approximate median of v’(t)
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• T 50% : median of v’(t), since
• Elmore delay T D = mean of v’(t)
def.)(by)(of valuefinalof half
)(')('%50
%500
t v
dt t vdt t vT
T
=
=∫ ∫ +∞
∫ ∞
=0
)(' tdt t vT D
Elmore Delay for Monotonic Responses
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Why Elmore Delay?
• Elmore delay is easier to compute analytically in most cases
– Elmore’s insight [Elmore, J. App. Phy 1948]
– Verified later on by many other researchers, e.g.
• Elmore delay for RC trees [Penfield-Rubinstein, DAC’81]
• Elmore delay for RC networks with ramp input [Chan, T-
CAS’86]• .....
• For RC trees: [Krauter-Tatuianu-Willis-Pileggi, DAC’95]
T50% ≤ TD
• Note: Elmore delay is not 50% value delay in general!
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Elmore Delay for RC Trees
• Definition
– h(t) = impulse response
– TD = mean of h(t)
=
• Interpretation
– H(t) = output response (step process)
– h(t) = rate of change of H(t)
– T50%= median of h(t)
– Elmore delay approximates the median of h(t) bythe mean of h(t)
∫ ∞
⋅0
dtth(t)
median
of v’(t)
(T 50% )v'(t)
dt t tvT D
of mean
)('0∫ ∞
=
h(t) = impulse response
H(t) = step response
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Elmore Delay of a RC Tree
[Rubinstein-Penfield-Horowitz, T-CAD’83]
ion!contradict 0)('
atcapacitorthechargecurrentsallSince
resistorsviaconnects&)()(Since
at0istonodeanyfromcurrenttheThen,
at)(achievenodeLet
0)(' s.t. Then,0)(thatAssume
0)0(
atnodeanyof voltagemin.thebe)(Let
nodeeveryat0)(responseimpulse
))()('( nodeeveryat0)('
in treenodeeveryforinmonotonicis)(
treeRCatoappliedisinputstepawhen
1min
minmin
min1min1
1min
11minmin
1min01
0min
min
min
⇒≥
→
≥
≥
<<∃<
≥+
≥⇔
=≥⇔
t h
iii
iit ht h
t ii
t t hi
t ht t t h
h
t t h
it h
t ht ivit v
it t v
i
i
ii
i
Lemma:
Proof:
Apply impulse func. at t=0:
imin
i
current i→imin
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Elmore Delay in a RC Tree (cont’d)
∫ ∫
∫ ∫
∑∑
∑
∑
∑
∞
∞→∞→
∞∞
∞
∈
−+⋅−=−⋅=
−⋅=⋅=
=⋅=
⋅=
⋅==−
=
=
∩
00
00
0
i
))(1()1)((lim])()([lim
)(|)()('
)()(
)andbetweenres.path(common)capo(current t
)inscap'allcurrent to(ondropvoltageThe)(1
)( nodeof cap.current toThe
nodedelay toElmore
&input tofrom
pathcommonof resistance:
atrootedsubtree: ;nodeinput tofrompath:
dt t vT T vdt t vT T v
dt t vt t vdt t t vT
dt
t dvC R R
dt
t dvC
P P k
S R P t v
dt
t dvC i
C RT
i
k j P P
R
i si P
ii
T
T
ii
T
iii D
k
k k kiki
k
k k
k
k i
P k
ik ii
i
k
k ki D
k j
jk
ii
i
i
i
input
i
k
jS i
path resistance Rii
R jk
Theorem :
Proof :
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Elmore Delay in a RC Tree (cont’d)• We shall show later on that
i.e. 1-v i (T) goes to 0 at a much faster rate than 1/ T when T →∞
• Let
0))(1(lim =⋅−∞→
T T viT
)(
)](1[))(1(lim
)(
)](1[
)(
)()(
)](1[)(
0
0
0
∑∫
∑
∑ ∑∑
∫ ∑
∫
=∞=
−+−=∴
=∞
−−=
=
=
−=
∞
∞→
k
k kii
iiT
D
k
k kii
k k
k k kik ki
k
k k ki
t
k
k k kii
t
ii
C R f
dt t vT T vT
C R f
t vC RC R
t vC R
dxdx
xdvC Rt f
dx xvt f
i
(1)
vi(t)
1
0 t
area ∫ −=t
ii dx xvt f 0
)](1[)(
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)&(since Then,
)(
Recall Let
2
kiiikikk p D R
ii
k
k ki R
k
k ki D
k
k kk p
R R R RT T T
RC RT
C RT C RT
ii
i
i
≥≥≤≤
=
==
∑
∑∑
Some Definitions For Signal Bound Computation
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Signal Bounds in RC Trees
• Theorem
ii
i Ri R
i Ri D
i
i
i
p p
Ri p
i
ii
i
R D
T t
T
T T
p
R
i
p
D
R p
T t
T
T T
p
D
R D
Ri
D
i
T T t ee
T
T
t v
t T
t T
T T t ee
T
T
T T t t T t
T t v
t
−≥⋅−
≤
≥−
−
−≥⋅−
−≥≥+
−≥
≥
−−
−−
)(
)(
1
)(
0 1
boundsUpper
1
)whentrivial-(non 0 1 )(
0 0
boundsLower
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Proofs of Signal Bounds in RC Trees
• Lemma:
• Lemma:
monotonic)is)((Since
0 )(
)(
)()(
)](1[)](1[
),min( ),max(
)](1[)](1[
t v
dt
t dvC R R R R
dt
t dvC R R
dt
t dvC R R
t v Rt v R R R R R
R R R R R R
t v Rt v R
j
j
j
j jiki jk ii
j j
j
j jiki
j
j jk ii
ikik ii
jiki jk ii
jiki jk jikiii
ikik ii
≥−=
−=
−−−⋅≥⋅∴
≥≥
−≥−
∑
∑ ∑
Proof:
(2)
)](1[)](1[ t v Rt v R ikk k ki −≤− (3)
S C
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Proofs of Signal Lower Bounds in RC Trees
t t vt f t t t
t f t f t vt t
t v
et f T
t f T e
T t (t t f T
T t (t t t
T dt
t df
t f T T
T
t f T
dt
t df
t vT
t f T
t vT t f T t vT
t vC Rt f T
ii
iii
i
T t t
i D
i DT t t
R
t
t i D p
R
i
i D p
R
i Di
i p
i D
i pi Di R
k
k k kii D
i R
i
i p
i
i
ii
i
ii
ii
i
⋅−≥==
−≤−−
≥−
−≥
−≤−−≤−
≤⋅−
≤
−
≤=−≤
−
−≤−≤−
−=−
−−−−
∑
)](1[)( ,0Let
)()()](1)[(
monotonicis)(sinceAlso,
)(
)( i.e.
)|))(ln() :tofromgIntegratin
1)(
)(
11 Thus,
)()(
)(1
)(
i.e.
)](1[)()](1[ :(3)&(2)From
))(1()( :(1)From
43
34434
)(
1
2)(
121221
1212
2
1
f i(t 4 )-f i(t 3 )
(t4-t3)[1-vi(t4)]
t3 t4
(4)
(5)
(7)
(6)
P f f Si l L B d i RC T
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Proofs of Signal Lower Bounds in RC Trees
p p
i R p
i pi
p
i
ii
p
ii
i
i
i
i
i
i
iii
T
t
T
T T
p
DT
t
p
Di
T t
Di p
i Di R
T t
Di D
iii R p
R p
R
D
i
R
D
i
i Di Di R
eeT
T e
T
T t v
eT t vT
t f T (t)vT
eT t f T
t t t
t f t f t vT T
t t T T t t
T t
T t v
T t
T t v
t t vT t f T t vT
−−−−
−
−
⋅−=−≥∴
≤−
++
−≤−
≤−
==
−≤−−
=+−=
+−≥∴
+≤−⇒
−−≤−≤−
)(
3
321
3
43
11)(
)](1[
:)10()9()8(
)(]1[
(4)of half -leftFrom
)(
(5)of half -leftinand 0Let
)()()](1)[(
(6)inLet
1)( )(1
)](1[)()](1[
(7)and(4)of half -leftFrom
3
3
3
(8)
(9)
(10)
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Delay Bounds in RC Trees
[ ]
[ ]
[ ] p
D
i
i p
Di p R p
R
i
D
p
R
i
i p
R
R R D
i p
T
T t v
t vT
T T T T t
T t v
T t
T
T t v
t vT
T T T T t
t vT T t
i
i
i
i
ii
iii
−≥−
+−≤
−−
≤
−≥−
+−≥
−−≥
1)(when)(1
ln
)(1
:boundsUpper
1)(henw)(1
ln
)(1
:boundsLower
iD
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Computation of Elmore Delay & Delay Bounds
in RC Trees
• Let C(T k ) be total capacitance of subtree rooted at k
• Elmore delay
fashion
up-bottomainyrecursivelelinear timincomputed becanformulathreeall*
:boundlower
)(
:boundupper
)(
2∑
∑
∑
⋅=
⋅=
⋅=∈
k ii
k ki R
k k k p
pk
k k D
R
C RT
T C RT
T C RT
i
i
i
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Comments on Elmore Delay Model
• Advantages – Simple closed-form expression
• Useful for interconnect optimization
– Upper bound of 50% delay [Gupta et al., DAC’95, TCAD’97]
• Actual delay asymptotically approaches Elmore delay as inputsignal rise time increases
– High fidelity [Boese et al., ICCD’93],[Cong-He, TODAES’96]
• Good solutions under Elmore delay are good solutions underactual (SPICE) delay
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Comments on Elmore Delay Model
• Disadvantages
– Low accuracy, especially poor for slope computation
– Inherently cannot handle inductance effect• Elmore delay is first moment of impulse response
• Need higher order moments
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