Intel® QuickAssist Technology Components
Neal Oliver, PhDPrincipal EngineerIntel Corporation
QATS002
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• Intel® QuickAssist Architecture Overview• Selected Intel® QuickAssist Architecture Components
• Intel® Embedded Processor for 2008 (Tolapai)• Hardware Architecture• Software Architecture• Use Cases
• Intel® QuickAssist FSB-FPGA Accelerator Platform (FAP)• System Architecture• Accelerator Hardware Module (AHM)• Design Flow
• Intel® QuickAssist Technology Accelerator Abstraction Layer (AAL)• AAL services and features• Software Architecture
Agenda
Single Chip Solutions - VPN/FirewallIntel’s response to customer need foracceleration on Intel platforms
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Intel® QuickAssist Technology – Comprehensive Approach to Acceleration
• Multiple accelerator and attach options with software and ecosystem support
• Performance and scalability based on customer needs and priorities
Intel’s response to customer need to deploy accelerators on Intel® architecture platforms.
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Intel® Embedded Processor for 2008 (Tolapai)
Single Die integrates- IA 32 based Core @ 600, 1066 and
1200MHz- DDR2 memory controller (MCH)- PCI Express* Technology- Standard IA PC peripherals (ICH)- 3x Gigabit Ethernet MACs- 3x TDM high-speed serial interfaces for
12 T1/E1 or SLIC/CODEC connections- Intel® QuickAssist Integrated Accelerator
Vital Statistics- 148 Million transistors- 1,088-ball FCBGA w/1.092 mm pitch - 37.5 mm x 37.5 mm package
Single Chip Solutions - VPN/FirewallSystem-on-Chip (SoC) enabling performant, effective system solutions
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Intel® Embedded Processor for 2008 (Tolapai) System Architecture
CurrentEquiv Solution
Intel® Embedded Processor for 2008 (Tolapai)
EnetWan/Lan
ATA
MCH
Intel® Pentium® MProcessor
ICH Sec Co-Proc
ATA Tolapai*
Enet PhyWan/Lan
Additional Area, Cost,
Core Utilization,
Architecture - Lookaside
Only
Additional Area, Cost
•IA SoC optimized for Power/Performance
•In-line network/security acceleration
•Integrated I/O devices
•IA SW compatibility
•Highest Compute Cycles Available/$
Single Chip Solutions - VPN/FirewallSoC reduces area, cost, power
Tolapai = Intel® embedded processor for 2008 (Tolapai)
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HW Architecture
‡ Enabling software required.
IMCH
PCI Express*Interface
(x1)
(Gen1,1x8, 2x4 or
2x1 root complex)
IA Complex
IICH
SATA 2.0(x2)
USB 2.0(x2)
UART (x2)GPIO (x37)SMBus(x2)
LPC1.1
APIC, DMA, Timers, Watch Dog Timer, RTC, HPET (x3)
Memory Controller HubFSB
EDMA
Memory Controller
TDMInterface
‡
(12 E1/T1)
Local Expansion
Bus(16b @ 80 MHz)
MDIO (x1)CAN (x2)SSP (x1)
IEEE-1588
AccelerationServices Unit
‡
SecurityServices Unit
‡
(3DES, AES, (A)RC4, MD5, SHA-x, PKE,
TRNG)
256 KBASU SRAM
GigEMAC
#2
GigEMAC
#0
GigEMAC
#1
Transparent PCI-to-PCI Bridge
IA3
2 C
ore
25
6K
L2
Cach
e
DDR2 (400/533/667/800,
64b with ECC)
Acceleration and I/O Complex
IA CPU Core w/ 256KB L2 cache- Intel® Pentium® M processor derivative
Integrated Memory Controller- 1 channel 64-bit DDR2- 4 channel DMA engine- PCI Express* (1x8, 2x4, or 2x1)
Intel® QuickAssist Acceleration - Multi-core, Multi-threaded Engines- 256KB Internal SRAM- Security Hardware Acceleration for
Bulk: AES, 3DES, (A)RC4Hash: MD5, SHA-xPublic Key – RSA, DSA, DHInternal True Random Number Generator (TRNG)
Integrated I/O Interfaces- 3x TDM (12 T1/E1)- 3x GbE MAC (RGMII or RMII)- 1x Local Expansion Bus (16b)- 2x Controller Area Network (CAN)- 1x Sync Serial Port (SSP)- 2x UART, 37x GPIO,- 2x SMBus/I2C, LPC- 2x USB, 2x SATA- WDT, RTC
Single Chip Solutions - VPN/FirewallSoC integrates processor, chipset,accelerators
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‡ Enabling software required.
IMCH
PCI Express*Interface
(x1)
(Gen1,1x8, 2x4 or
2x1 root complex)
IA Complex
IICH
SATA 2.0(x2)
USB 2.0(x2)
UART (x2)GPIO (x37)SMBus(x2)
LPC1.1
APIC, DMA, Timers, Watch Dog Timer, RTC, HPET (x3)
Memory Controller HubFSB
EDMA
Memory Controller
TDMInterface
‡
(12 E1/T1)
Local Expansion
Bus(16b @ 80 MHz)
MDIO (x1)CAN (x2)SSP (x1)
IEEE-1588
AccelerationServices Unit
‡
SecurityServices Unit
‡
(3DES, AES, (A)RC4, MD5, SHA-x, PKE,
TRNG)
256 KBASU SRAM
GigEMAC
#2
GigEMAC
#0
GigEMAC
#1
Transparent PCI-to-PCI Bridge
IA3
2 C
ore
25
6K
L2
Cach
e
DDR2 (400/533/667/800,
64b with ECC)
Acceleration and I/O Complex
Packet Processing Flows
Classic IA (blue)- GigE Rx DMA packets to
DRAM (includes IA snoop)- IA interrupt- IA CPU runs protocol- IA CPU controls GigE TX
Fastpath (red)- GigE Rx DMA packets to
DRAM - Interrupt routed to
accelerator - Accelerator operates on
packet - Forwarding/filtering and
security functions can be handled w/o IA CPU intervention
- Accelerator controls GigE Tx
Exception Packets (green)- Move packet to coherent
DRAM (includes IA snoop)- Accelerator signals IA CPU
Single Chip Solutions - VPN/FirewallProcessing flows preserve legacy,provide next-gen performance
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IO/Acceleration/Security IO/Acceleration/Security Access LibraryAccess Library
High Level SW Model
IA CoreIA Core
Acceleration/Security Services (or Unit)Acceleration/Security Services (or Unit)
……APIAPI
Driver/ShimDriver/Shim
OS/StackOS/Stack
Customer App
Intel® Embedded Processor for 2008 (Tolapai) Architecture Overview
Single Chip Solutions - VPN/FirewallSoftware framework goal: enablescalable software solutions
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Application
Intel® Embedded Processor for 2008 (Tolapai) Software Architecture
Drivers for Linux* (Red Hat) and FreeBSDIntel® QuickAssist Technology Security API- Low level crypto
API – PKCS #11 compliant
- High level protocol support
Integrated with middleware frameworks- OpenSSL- OCF- FreeS/WAN, etc.Packet Packet
ClassifyClassifyMod ExpMod Exp AuthenticationAuthentication
Bulk Bulk
CryptoCrypto
IPSecIPSec SSL/TLSSSL/TLS IKEIKEProtocol
Acceleration
Low Level Acceleration
Accelerators
IA Acceleration Drivers
Intel® QuickAssist Technology Security API
FreeS/WAN
Shim Layer
Open SSL
Shim Layer
OCF
Shim Layer
Combined Operation
Bulk processing Bulk processing Encrypt and Encrypt and
HashHash
RandRand
Public Key Public Key –– RSA, DH, DSARSA, DH, DSA
Single Chip Solutions - VPN/FirewallConvenient, efficient access to security accelerators
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User Data App IPTCP Auth. State Bulk Keys
L5-7 L4 L3
MAC&PL
L2&1
Encrypt & Hash
Authenticate
Tolapai
GbE
Intel®QuickAssistAcceleration Technology
IA 32 Core
IICH
IMC
H
Intel® QuickAssist Acceleration Technology Security Applications – Single Chip VPN/FW
Traditional Solutions
High PerformanceRISC or CISC
PCIX
Security Co-Processor
72 Bit DDR2
Tolapai with Acceleration
1 GbENIC
Single Chip Solutions - VPN/Firewall
layerlayer
Tolapai = Intel® Embedded Processor for 2008 (Tolapai)
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Intel® Embedded Processor for 2008 (Tolapai) - Summary
The Tolapai System-on-a-Chip enables single chip, small form factor developments, bringing x86 performance and cost effectiveness to new applications!The Intel® QuickAssist Integrated Accelerator within Tolapai draws its identity from the QuickAssist Software Services Modules, enabling customers to develop complete communications, or security solutions in a single chip design.The Tolapai Integrated Accelerators make possible single chip solutions such as SMB IP PBX, and VPN/Firewall.
Single Chip Solutions - VPN/FirewallSoC brings X86 performance andCost-effectiveness to new apps
Tolapai = Intel® Embedded Processor for 2008 (Tolapai)
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FSB-FPGA Accelerator Platform (FAP)
Field Programmable Gate Arrays (FPGA) allow the development of domain-specific
hardware-based, parallel algorithms that execute significantly faster than
equivalent algorithm in software
Front Side Bus (FSB) provides
a high performance, low latency interconnect between AHM and CPU
Single Chip Solutions - VPN/FirewallFSB provides high-bandwidth accessto third party vendor (TPV) accelerators
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What are FSB-FPGA Accelerators?- FPGA Accelerator Hardware Modules (AHMs) that plug into
Intel® Xeon® processor socketsAttach directly to the Front Side Bus (FSB)FSB provides the highest performance, lowest latency interconnect
AMB AMB AMB
AMBIntelIntel®® Expandable Expandable Server Platform for Server Platform for
2007 (2007 (CanelandCaneland))
FSB – FPGA Modules
AMB AMB AMB AMB
AMB AMB AMB
AMB
AMB AMB AMB
AMB
AMB AMB AMB AMB
IntelIntel®® Entry Two Entry Two Socket Platform for Socket Platform for
2007 (2007 (BensleyBensley)/ )/ IntelIntel®® Workstation Workstation
Two Socket Two Socket Platform for 2008 Platform for 2008
((StoakleyStoakley))
FSB – FPGA Modules
7000 Series 5000 SeriesAMB AMB AMB AMB
AMB AMB AMB
AMBAMB AMB AMB AMB
AMB AMB AMB
AMBAMB AMB AMB AMB
AMB AMB AMB
AMBAMB AMB AMB AMB
Single Chip Solutions - VPN/FirewallIntel® Xeon® Server Platforms –DP & MP
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Multiple AHMs
- Multiple FPGA modules can be connected in a ring topologyPartition complex algorithms across multiple accelerator modulesHigher degrees of parallelization for even higher performanceConnect to external I/O sources
AMB AMB AMB
AMBIntelIntel®® Expandable Expandable Server Platform Server Platform
for 2007 for 2007 ((CanelandCaneland))
FSB – FPGA Modules
AMB AMB AMB AMB
AMB AMB AMB
AMBAMB AMB AMB AMB
AMB AMB AMB
AMBAMB AMB AMB AMB
AMB AMB AMB
AMBAMB AMB AMB AMB
FSB – FPGA Modules
FSB – FPGA Modules
Multi-Gigabit Serial Links
Single Chip Solutions - VPN/FirewallFlexible hardware configuration
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Shared Memory: SMP
In a typical SMP system, all CPUs can see system memory, but they can’t see each other because they don’t occupy address spaceCPUs usually communicate through shared memory and signal each other using Inter-Processor Interrupts (IPIs)
XEON XEON
Memory Controller Hub
Inter-ProcessorInterrupts
(IPI)
SystemMemory SHARED
MEMORY
Single Chip Solutions - VPN/FirewallHow SMP architectures work
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Shared Memory: CPU+AHM
A similar technique is used to communicate with FSB-attached AHMsThe AHM device driver allocates (and pins) system memory for AHM device registers, command/response queues and shared workspacesThe physical address of the device register memory area is sent to the AHMCPU communicates with AHM through this memory-based interface
FSB
FSB
Single Chip Solutions - VPN/FirewallAHM Core participates in FSB protocol
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FAP System ArchitectureAccelerator Hardware Modules (AHM) contains FPGAs, SRAM, flash memory and control logic. AAL will support multiple AHMs from different vendors. AHMs may also be interconnected with serial links.Accelerator Function Units (AFU) implement accelerated algorithms on compute FPGAs.Management AFU supports FPGA reconfiguration and other platform services on the bridge FPGA.AHM Core logic provides FSB interface logic, low-level AHM device interface and multiple AFU engine interfaces.Workspace memory is reserved area of system memory managed by AHM driver
- Memory is allocated, pinned (to prevent swapping) and mapped into application’s virtual address space. Both application and AFU can access this memory directly
Accelerator Abstraction Layer (AAL) provides generic accelerator discovery, configuration and messaging servicesAFU proxies implement AFU specific message formatting and API.Domain Specific Libraries may be used to provide a more abstract interface on top of AALApplications access accelerator functionality through the domain specific library or directly to AAL.
Single Chip Solutions - VPN/FirewallFAP architecture provides criticalfunctions of FSB protocol
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AHM Architecture
Single Chip Solutions - VPN/FirewallAHM Core implements criticalfunctions of FSB agent
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AFU Engine Interface
One pair of Command and Data FIFOs in each directionSeparate CSR and Bulk data transfer interfacesCommand FIFO holds Cmd_Hdrindicating the type of transferData FIFO holds data corresponding to each Cmd_HdrBenefits- High performance- Use FPGA vendor FIFO macro
implementation- Simple FIFO interface can also be
used to cross clock boundaries- Variable burst size, 64B to 4MB- Supports bursting with/without wait
states- Receiver controls dataflow
CS
R W
rite
CS
R W
rite
Dat
a
CS
R U
pdat
eD
ata
CS
R U
pdat
e
SP
L2A
FU
Cm
d S
PL2
AFU
D
ata
AFU
2SP
L C
md
AFU
2SP
L D
ata
Simple Accelerator Interface
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AFU Design Flow
Multiple languages will be available for developing FPGA accelerator algorithms- VHDL / Verilog- High Level Languages
C, C++, Java
- Matlab*
Intel is working with a variety of 3rd-Party tool vendors to provide FPGA software development kits
VHDL / VerilogHigh Level Language
(C, C++, Java)
DSP Flow(ie: Matlab)
Compilers Compilers
Simulation
Synthesis
FPGA
VHDL
Gates / EDIF
Flexible Design Choices
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FPGA Acceleration Platform (FAP) - Summary
FAP enables FPGA, tool and hardware vendors to provide customers with a complete solution for integrating FSB-FPGA acceleration into their applications- Comprehensive Approach To Acceleration- Flexible Hardware Configuration- Zero-Copy Programming Model- Simple AFU Interface, flexible design choices
Single Chip Solutions - VPN/FirewallFAP brings FPGA acceleration toIntel platforms
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Accelerator Abstraction Layer (AAL)
AAL allows FAP accelerators in an Intel platform to be managed as a uniform set of resources
- Independent of attach technology (e.g. FSB, PCI Express* Technology)
- Independent of the acceleration workload- Defines a common host programming model- Provides a common presentation of the services using
existing interconnect interfacesTightly coupled accelerators: FSBLoosely coupled accelerators: PCI Express Technology
Single Chip Solutions - VPN/FirewallAAL presents accelerators as uniformresources to application programmer
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AAL Services
Installation and configuration of accelerators on the platform- Uniform interface for installers to register the packages
they are installing - Uniform interface for applications / libraries to
query, enumerate, find and load installed packages Communication between applications and accelerators- Asynchronous programming model with event dispatcher
and delivery: optimized for concurrent task processing- Protection of shared resources allowing multiple
applications to use one accelerator: support for multiple threads
- Dynamic binding to acceleration packages: provides maximum flexibility without changing framework
Single Chip Solutions - VPN/FirewallAAL services satisfy requirements ofenterprise deployments
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AAL Software Architecture
Application
AAS AFU(n) Proxy
AIA(n)
ISystem, IFactory IAFU Callback IProprietary*
IAFUFactory
Open, Close, Read, Write, IOCTL, MMap, …
IRegistrar
Read, park thread
IRegistrar IEDS
IPIP Callback Proprietary*
User Mode
Kernel Mode
33rdrd Party / Party / StandardStandard
IntelIntel
FSB AHM Driver(n)
Single Chip Solutions - VPN/FirewallAAL callback model provides distributedProgramming features
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AAL Interfaces
Installation and Configuration- AFU Registration Interface (IRegistrar)
Used by installer to register AFU packagesAdministrative privilege required
- AAL System Interface (ISystem)Called once per process to initialize AAL
- AAL Factory Interface (IFactory)Called to create AFU proxy object instances
Communication- AAL Event Delivery Service (IEDS)
Used to deliver events and support different threading models- AIA Interface (IAFU)
Implemented by AFU proxy to support data exchange with AHMUser level privilege since device driver validates all workspacememory references
Single Chip Solutions - VPN/FirewallComponent model integrates withenterprise software frameworks
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Accelerator Abstraction Layer (AAL) - Summary
Intel’s AAL provides a uniform programming interface for accelerators- Integration with enterprise software frameworks- Management of accelerators as resources- Concurrent programming model across FPGA and
attachment technologies
Single Chip Solutions - VPN/FirewallUsing AAL protects your softwareinvestment
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Additional sources of information on this topic:
Other Sessions / Chalk Talks / Labs –QATS001 – Overview of Intel® QuickAssist Technology
For an overview of Intel® embedded processor for 2008 (Tolapai) with Intel® QuickAssist Technology go to: www.intel.com/go/soc
Accelerators in Action: Visit the I/O & Application AccelerationCommunity in the showcase to see technology demonstrations from Intel and other industry-leading companies
More web based info:http://www.intel.com/go/quickassist
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https://intel.wingateweb.com/SHchina/catalog/controller/catalog
These can also be found from links on www.intel.com/idf
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Tolopai, FAP, AAL and other code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Intel, Intel Inside, Intel® QuickAssist Technology, Intel® Xeon®, and the Intel logo are trademarks of Intel Corporation in the United States and other countries. *Other names and brands may be claimed as the property of others.Copyright © 2008 Intel Corporation.
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Risk FactorsThis presentation contains forward-looking statements that involve a number of risks and uncertainties. These statements do not reflect the potential impact of any mergers, acquisitions, divestitures, investments or other similar transactions that may be completed in the future, with the exception of the Numonyx transaction. Our forward-looking statements for 2008 reflect the expectation that the Numonyx transaction will close during the first quarter. The information presented is accurate only as of today’s date and will not be updated. In addition to any factors discussed in the presentation, the important factors that could cause actual results to differ materially include the following: Factors that could cause demand to be different from Intel's expectations include changes in business and economic conditions, including conditions in the credit market that could affect consumer confidence; customer acceptance of Intel’s and competitors’ products; changes in customer order patterns, including order cancellations; and changes in the level of inventory at customers. Intel’s results could be affected by the timing of closing of acquisitions and divestitures. Intel operates in intensely competitive industries that are characterized by a high percentage of costs that are fixed or difficult to reduce in the short term and product demand that is highly variable and difficult to forecast. Additionally, Intel is in the process of transitioning to its next generation of products on 45 nm process technology, and there could be execution issues associated with these changes, including product defects and errata along with lower than anticipated manufacturing yields. Revenue and the gross margin percentage are affected by the timing of new Intel product introductions and the demand for and market acceptance of Intel's products; actions taken by Intel's competitors, including product offerings and introductions, marketing programs and pricing pressures and Intel’s response to such actions; Intel’s ability to respond quickly to technological developments and to incorporate new features into its products; and the availability of sufficient components from suppliers to meet demand. The gross margin percentage could vary significantly from expectations based on changes in revenue levels; product mix and pricing; capacity utilization; variations in inventory valuation, including variations related to the timing of qualifying products for sale; excess or obsolete inventory; manufacturing yields; changes in unit costs; impairments of long-lived assets, including manufacturing, assembly/test and intangible assets; and the timing and execution of the manufacturing ramp and associated costs, including start- up costs. Expenses, particularly certain marketing and compensation expenses, vary depending on the level of demand for Intel's products, the level of revenue and profits, and impairments of long-lived assets. Intel is in the midst of a structure and efficiency program that is resulting in several actions that could have an impact on expected expense levels and gross margin. We expect to complete the divestiture of our NOR flash memory assets to Numonyx. A delay or failure of the transaction to close, or a change in the financial performance of the contributed businesses could have a negative impact on our financial statements. Intel’s equity proportion of the new company’s results will be reflected on its financial statements below operating income and with a one quarter lag. Intel’s results could be affected by the amount, type, and valuation of share-based awards granted as well as the amount of awards cancelled due to employee turnover and the timing of award exercises by employees. Intel's results could be impacted by adverse economic, social, political and physical/infrastructure conditions in the countries in which Intel, its customers or its suppliers operate, including military conflict and other security risks, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates. Intel's results could be affected by adverse effects associated with product defects and errata (deviations from published specifications), and by litigation or regulatory matters involving intellectual property, stockholder, consumer, antitrust and other issues, such as the litigation and regulatory matters described in Intel's SEC reports. A detailed discussion of these and other factors that could affect Intel’s results is included in Intel’s SEC filings, including the report on Form 10- K for the fiscal year ended December 29, 2007.
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