Download - [IEEE 2013 International Conference on Communication and Computer Vision (ICCCV) - Coimbatore, India (2013.12.20-2013.12.21)] 2013 International Conference on Communication and Computer

Capacitance and Frequency Scaling Based Energy Efficient Image Inverter Design on FPGA

Teerath Das, Bishwajeet Pandey, Md Atiqur Rahman, Tanesh Kumar, Tanvir Siddiquee Department of Computer Science

South Asian University Delhi, India

[email protected], [email protected]

Abstract- In this work, Capacitance scaling and Frequency scaling is done in order to make energy efficient Image Inverter design. Frequency scaling results variations in power consumption and the Junction temperature of Image Inverter. There is 93.33% change in Logic power, 98.06% change in Signals power, 99.00%change in IOs power, 92.02% change in Leakage power and 77.6% change in Junction temperature. Clocks power, Logic power and Signal powers are independent of the capacitance scaling while the frequency is constant. At the same time IOs power, Leakage power as well as the Junction temperature varies. Along with fixed 1GHz frequency it is found that there is 71.92% increment on IOs power while capacitance is incremented by 90%. At the same time there is a 2.4% increment found in Leakage power while Junction temperature faces an change of 7.14%. Keywords—Frequency Scaling, Capacitance Scaling, Image Inverter, Energy Efficient Design, I/Os Power, FPGA.

I. INTRODUCTION An image which is inverted in four direction up, down, left and right is said to be an Inverted image. Inverted image results from 180 degrees rotation of an Image, about a line from the object to the observer. Reversed image is also called an Inverted image. There are various systems developed to scale Capacitance. The basic idea is to vary the capacitance while keeping the other parameter constant of the inverter and observe the changes in power consumption. Similarly there are different methods of frequency scaling as well. In this paper our focus is in observing changes in power consumption along with frequency scaling while keeping the other parameters constant of our Image inverter.

Figure 1: Circuit diagram of Image Inverter.

This Energy Efficient Image Inverter is implemented in Verilog. We apply capacitance and frequency scaling to reduce the overall power consumption of Image Inverter. The FPGA which is in use is 28nm Kintex-7 FPGA.

II. LITERATURE REVIEW Human and Application specific Processor Power Efficiency (HAPPE) is an adaptive user and application specific dynamic CPU frequency scaling technique is proposed in [1] to achieve energy efficiency. We are integrating the idea of capacitance scaling[2] along with frequency scaling. In [2], there is a study and analysis of gate capacitance scaling of graphene field effect transistors with gate dielectric with 2 different seed layers, oxidized aluminum and oxidized titanium. That gives us the idea to incorporate capacitance scaling in our image inverter design. Capacitance scaling system for different measurements of 10 nF (nano Farad) to 100nF, ceramic-dielectric Four Terminal Pair (4TP) capacitance standards over the 100Hz to 100kHz frequency range is analyzed in [3]. In our work, we are extending the frequency range to 1GHz-100GHz. in [4], Frequency scaling depends on the propagation effects with respect to frequency. Comparison between attenuation two different frequency is objective in [4]. [5] describes development of capacitance scaling system. The component of Capacitance Scaling System are as following: 4 terminal pair LCR meter, 1 inductive voltage divider, and 1 1000 pF air dielectric capacitor [5]. It can calibrate capacitors up to 1 pF in the frequency range from 50 Hz-100 kHz. Our range of both capacitance and frequency is beyond this range.

III. ARCHITECTURE OF IMAGE INVERTER


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1st ICCCV - 13 December 20 - 21, 2013 - Coimbatore, India

Figure 3 and Figure 4 show the RTL schematic and Technology Schematic of Image Inverter. It has 4 inputs and 3 outputs. We are taking RGB image from 3 inputs bus and provide inverted RGB image from 3 output Bus.


IV. RESULTS AND DISCUSSION OF CAPACITANCE SCALING Clock power, Logic power and Signal powers are independent of the capacitance scaling. But the IOs power, Leakage power as well as the Junction temperature varies with varying capacitance. The observations are in Watt(W). Capacitance Scaling is discussed in [2,3,5].

A. Power Consumption With 50pF Capacitance Table 1: Power Consumption with 50pF Capacitance

1 GHz 10 GHz 50 GHz 100 GHz Clocks 0.006 0.062 0.309 0.617 Logic 0.002 0.008 0.018 0.030

Signals 0.003 0.020 0.080 0.155 IOs 1.353 13.533 67.665 135.330

Leakage 0.082 0.131 1.028 1.028 Total 1.447 13.754 69.099 137.159

Junction Temp(c) 28.0 53.2 125.0 125.0 There is 99.02% change in Clocks power while Frequency is incremented from 1GHz to 100GHz with a fixed capacitance of 50pF. Whereas Logic power faces an change of 93.33%, Signals power 98.06%, IOs power 99.00%, Leakage power 92.02% and Junction temperature faces an change of 77.6% as shown in Table 1. With 50pF, we are showing Clock Power in Figure 4.

Figure 4: Clock Power Consumption at 50pF

B. Power Consumption With 40pF Capacitance Table 2: Power Consumption with 40pF Capacitance


Signals 0.003 0.020 0.080 0.155 IOs 1.137 11.370 56.851 113.702

Leakage 0.082 0.119 1.028 1.028 Total 1.230 11.579 58.285 115.532

Junction Temp(c)

27.5 48.7 125.0 125.0

While the capacitance is fixed at 40pF and frequency is increased to 100GHz from 1GHz., the increment in the power consumption are as follows: Clocks power: 99.02%, Logic power: 93.33%, Signals power: 98.06%, IOs power: 99.00%, Leakage power: 92.02% and Junction temperature: 78.00% as shown in Table 2. With 40pF, we are showing Logic Power in Figure 5.

Figure 5: Logic Power Consumption at 40pF

C. Power Consumption With 30pF Capacitance Table 3: Power Consumption with 30pF Capacitance


Signals 0.003 0.020 0.080 0.155 IOs 0.921 9.207 46.037 92.074

Leakage 0.081 0.108 0.951 1.028 Total 1.013 9.405 47.395 93.904

Junction Temp(c)

27.1 44.3 122.2 125.0

With 30pF capacitance, the change in the power consumption are as follows when the frequency varies. Clocks power: 99.02%, Logic power: 93.33%, Signals power: 98.06%, IOs power: 98.99%, Leakage power: 92.12% and Junction temperature: 78.32% as shown in Table 3 and Figure 6.

Figure 6: Signals Power Consumption at 30pF

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With 30pF, we are showing Signal Power in Figure 6.

D. Power Consumption With 20pF Capacitance Table 4: Power Consumption with 20pF Capacitance


Signals 0.003 0.020 0.080 0.155 IOs 0.704 7.045 35.223 70.447

Leakage 0.081 0.099 0.491 1.028 Total 0.796 7.234 36.121 72.277

Junction Temp(c)

26.6 39.8 99.1 125.0

With a 20pF constant capacitance, the increment in the power consumption are as follows when the frequency is scaled. Clocks power: 99.02%, Logic power: 93.33%, Signals power: 98.06%, IOs power: 99.00%, Leakage power: 92.12% and Junction temperature: 78.72% as shown in Table 4.

Figure 7: IOs Power Consumption at 20pF

E. Power Consumption With 10pF Capacitance Table 5: Power Consumption with 10pF Capacitance


Signals 0.003 0.020 0.080 0.155 IOs 0.488 4.882 24.410 48.819

Leakage 0.081 0.092 0.248 1.028 Total 0.580 5.064 25.064 50.649

Junction Temp(c)

26.2 35.4 76.4 125.0

The increment in the power consumption with a fixed capacitance of 10pF and frequency is increased to 100GHz from 1GHz are as following: Clocks power: 99.02%, Logic power: 93.33%, Signals power: 98.06%, IOs power: 99.00%, Leakage power: 92.12% and Junction temperature: 79.04% as shown in Table 5.

Figure 8: Leakage Power Consumption at 10pF

F. Power Consumption With 5pF Capacitance Table 6: Power Consumption with 5pF Capacitance


Signals 0.003 0.020 0.080 0.155 IOs 0.380 3.801 19.003 38.005

Leakage 0.080 0.089 0.179 0.598 Total 0.471 3.979 19.589 39.406

Junction Temp(c)

26.0 33.2 65.2 105.8

With 5pF capacitance the change in power consumption are as follows when the frequency is increased to 100GHz from 1GHz. Clocks power: 99.02%, Logic power: 93.33%, Signals power: 98.06%, IOs power: 99.00%, Leakage power: 86.62% and Junction temperature: 75.42% as shown in Table 6.

Figure 9: Junction Temperature at 5pF Capacitance.

V. RESULTS AND DISCUSSION OF FREQUENCY SCALING

FrequencyOperatingDevicePower It has been observed that with a fixed capacitance if the input frequency is varied there are variations in different power consumption parameters along with the Junction temperature. The observation is described below. Frequency Scaling is discussed in [1,4]. We are scaling frequency from 1 GHz to 10GHz then finally 100 GHz.

A. Power Consumption With 1GHz Frequency Table 7: Power Consumption with 1GHz Frequency

5 pF 10 pF 20 pF 30 pF 40 pF 50 pF Clocks 0.006 0.006 0.006 0.006 0.006 0.006 Logic 0.002 0.002 0.002 0.002 0.002 0.002

Signals 0.003 0.003 0.003 0.003 0.003 0.003 IOs 0.380 0.488 0.704 0.921 1.137 1.353

Leakage 0.080 0.081 0.081 0.081 0.082 0.082 Total 0.471 0.580 0.796 1.013 1.230 1.447

Junction Temp(c)

26.0 26.2 26.6 27.1 27.5 28.0

With 1GHz frequency, it is found that there is 71.92% increment in IOs power while capacitance in incremented by 90%. At the same time there is a 2.4% increment found in Leakage power while Junction temperature faces an increment of 7.14% as shown in Table 7 and Figure 10.

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Figure 10: Junction Temperature and Power Consumption at 1GHz

B. Power Consumption With 10GHz Frequency Table 8: Power Consumption with 10GHz Frequency


Signals 0.020 0.020 0.020 0.020 0.020 0.020 IOs 3.801 4.882 7.045 9.207 11.370 13.533

Leakage 0.089 0.092 0.099 0.108 0.119 0.131 Total 3.979 5.064 7.234 9.405 11.579 13.754

Junction Temp(c)

33.2 35.4 39.8 44.3 48.7 53.2

With 10GHz device operating frequency, there is 71.92% increment on IOs power while capacitance in incremented by 90%. At the same time there is a 3.2% increment found in Leakage power while Junction temperature faces an increment of 37.59% as shown in Table 8 and Figure 11.


C. Power Consumption With 50GHz Frequency Table 9: Power Consumption with 50GHz Frequency


Signals 0.080 0.080 0.080 0.080 0.080 0.080 IOs 19.003 24.410 35.223 46.037 56.851 67.665

Leakage 0.179 0.248 0.491 0.951 1.028 1.028 Total 19.589 25.064 36.121 47.395 58.285 69.099

Junction Temp(c)

65.2 76.4 99.1 122.2 125.0 125.0

Again while frequency is 50GHz, there is 71.92% increment on IOs power while capacitance in incremented by 90%. At the same time there is an 82.95% increment found in Leakage

power while Junction temperature faces an increment of 47.84% as shown in Table 9 and Figure 12.


D. Power Consumption With 100GHz Frequency Table 10: Power Consumption with 100GHz Frequency


Signals 0.155 0.155 0.155 0.155 0.155 0.155 IOs 38.005 48.819 70.447 92.074 113.702 135.330

Leakage 0.598 1.028 1.028 1.028 1.028 1.028 Total 39.406 50.649 72.277 93.904 115.532 137.159

Junction Temp(c)

105.8 125.0 125.0 125.0 125.0 125.0

Finally when frequency is 100GHz there is 71.92% increment on IOs power while capacitance in incremented by 90%. At the same time there is a 41.82% increment found in Leakage power while Junction temperature faces an increment of 15.36% as shown in Table 10 and Figure 13.

Figure 13: Junction Temperature and Power Consumption at 1THz

VI. CONCLUSION Capacitance scaling and Frequency Scaling are effective technique for energy efficient design. With Frequency Scaling, there is 99.00% change in IOs power, 99.02% change in Clock Power, 93.33% change in Logic Power, 92.02% change in Leakage Power, 98.06% change in Signal Power and 77.6% change in Junction Temperature. Capacitance Scaling is an effective technique to reduce IOs power, Leakage power as well as the Junction temperature. With Capacitance Scaling, there is no change in Clock Power, Logic Power and Signal Power. There is 71.92% increment in IOs power while

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capacitance is incremented by 90%. At the same time there is a 41.82% increment found in Leakage power while Junction temperature faces a change of 15.36%.

VII. FUTURE SCOPE We are implementing this image inverter on 28nm FPGA. There is open scope to redesign this circuit on 16nm Future ultra scale FPGA. Here, frequency and capacitance scaling is applied to get energy efficient design. there is wide scope to redesign this circuit using other energy efficient design technique like clock gating, power gating, mapping, IO standard, LVCMOS IO standard and HSTL IO Standard.

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[3] S. Zamurovic, A.D. Koffman, B.C. Waltrip, Y. Wang , "Evaluation of a Capacitance Scaling System", IEEE Transactions on Instrumentation and Measurement, Volume:56 , Issue: 6, pp. 2160-2163, 2007

[4] O. Brisseau, L. Barthes, C. Mallet, T. Marsault, "Effect of microphysical characteristics of rain on frequency scaling in microwave band", IEEE International Geoscience and Remote Sensing Symposium, Volume:7, pp.4121-4125, 2003

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[6] 6 Series FPGA SelectIO Resources User Guide UG361 (v1.4) June 21, 2013http://www.xilinx.com/support/documentation/user_guides/ug361.pdf

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[8] N. Gong , J. Wang ,R. Sridhar, ‘’Application-driven power efficient ALU design methodology for modern microprocessors’’, 14th International Symposium on Quality Electronic Design (ISQED), Page(s): 184 – 188, 2013

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