8/8/2019 Hsk Slides
1/93
VHDL (First Unit)
8/8/2019 Hsk Slides
2/93
VHDL 2Identifiers, data objects and data types
Chapter2
Identifiers
Data
objects Data types
constants Signals Variables
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
3/93
Identifiers
How to create names?
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
4/93
Identifiers
Used to represent an
object (constant, signal
or variable ,entity,
architecture)
Two types
Basic identifier
Extended identifier
Chapter2
Identifiers
Data
objects Data types
constants Signals Variables
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
5/93
Rules for Basic Identifiers
Names for users to identify data objects:
signals, variables etc.
First character must be a letter last character cannot be an underscore
Not case sensitive
Two connected underscores are not allowed Examples of identifiers: a, b, c, axy, clk ...
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
6/93
Example:
a,b,equals are Identifiers of signals
1 entity eqcomp4 is
2 port (a, b: in std_logic_vector(3 downto 0);
3 equals: out std_logic);
4 end eqcomp4;
5
6 architecture dataflow1 ofeqcomp4 is
7 begin
8 equals
8/8/2019 Hsk Slides
7/93
Extended Identifier
They were add in VHDL93 in order to makethe code more compatible with tools.
Characteristics: Contain special characters
Begin with numbers
Same name as keywords
Start with (/),followed by a sequence ofcharacters ,followed by another backslash(/)
Case sensitive
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
8/93
Examples
/a+b/
/3 state/
/type/ Entity example is
port(in_port: in bit;
Bit_port:out bit);
End example
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
9/93
Data objects
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
10/93
Data objects
Constant
Signals
variables
Chapter2
Identifiers
Data
objects Data types
Constants
(Global)
Signals
(Global)
Variables
(Local)
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
11/93
Data objects: 3 different objects
1 Constants: hold values that cannot be changed within a
design.
e.g. constant width: integer 8
2 Signals: to represent wire connections e.g. signal count: bit_vector (3 downto 0)
-- count means 4 wires; they are count(3),count(2), count(1),
count(0).
3 Variables: internal representation used by programmers;
do not exist physically.
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
12/93
Recall:
if a signal is used as input/output declared in
port
It has 4 modes
VHDL 2. Identifiers, data objects and datatypes ver.9b
Modes in
port
IN out inout buffer
e.g.
entity eqcomp4 is
port (a, b: in std_logic_vector(3 downto 0 );
equals: out std_logic);
end eqcomp4;
BUFFER - An output which is also used internally and has a limited fan-out.
We will not use mode BUFFER. This will make it easier to use entities in
hierarchical designs as VHDL is a strongly typed language.
8/8/2019 Hsk Slides
13/93
Syntax to create data objectsIn entity declarations
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
14/93
Constants with initialized values
constant CONST_NAME: :=;
-- Examples:
constant CONST_NAME: BOOLEAN := TRUE;
constant CONST_NAME: INTEGER :=31;
constant CONST_NAME: BIT_VECTOR (3 downto 0) := "0000";
constant CONST_NAME: STD_LOGIC := 'Z';
constant CONST_NAME: STD_LOGIC_VECTOR (3 downto 0) := "0-0-"; --
- is dont care
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
15/93
Signals with initialized values
signal sig_NAME: type_name [: init. Value];
-- examples
signal s1_bool : BOOLEAN; -- no initialized value
signal xsl_int1: INTEGER :=175;
signal su2_bit: BIT :=1;
BY DEFAULT value TLEFT (leftmost value i.e false)
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
16/93
Variables with initialized values
variable V_NAME: type_name [: init. Value];
-- examples
variable v1_bool : BOOLEAN:= TRUE;
variable val_int1: INTEGER:=135;
variable vv2_bit: BIT; -- no initialized value
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
17/93
Signal and variable assignments
SIG_NAME
8/8/2019 Hsk Slides
18/93
Exercise 2.1: Find identifiers, I/O signals, variables, constants,
arrays, and list their data_types.
1-- a, b: out bit:
2-- CLK, ASYNC ,LOAD, : in STD_LOGIC;
3-- DIN: in STD_LOGIC_VECTOR(3 downto 0);
4-- DOUT: out STD_LOGIC_VECTOR(3 downto 0);
5 process (CLK, ASYNC) 6 begin
7 if ASYNC='1' then
8 DOUT
8/8/2019 Hsk Slides
19/93
Note:
User can design the type for a data object.
E.g. a signal can have the type bit
E.g. a variable can have the type std_logic
Only same type can interact.
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
20/93
Exercise 2.2:
declare a signal with type bit in line 2
1 Architecture test2_arch of test2
2 ???????????
3 begin 4 ...
5
6 end test_arch
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
21/93
Exercise 2.3: Where to specify the types for signals. Draw the
schematic of this circuit.
1 entity nandgate is
2 port (in1, in2: in STD_LOGIC;
3 out1: out STD_LOGIC);
4 end nandgate; 5 architecture nandgate_arch ofnandgate is
6 signal connect1: STD_LOGIC;
7 begin
8 connect1
8/8/2019 Hsk Slides
22/93
Types must match
1 entity testis port (
2 in1: in bit;
3 out1: out std_logic );
4 end test;
5 architecture test_arch oftestis
6 begin
7 out1
8/8/2019 Hsk Slides
23/93
Revision (so far we learned)
Data object
Constants, signal, Variables
Signal in port (externalpins)
In
Out
Inout
Buffer
Chapter2
Identifiers
Data
objects Data types
Constants
(Global)
Signals
(Global)
Variables
(Local)
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
24/93
Exercise 2.4: Revision
What kinds of data objects are in1 and out1?
What is the data type for signal out1
?
1 entity nandgate is
2 port (in1, in2: in STD_LOGIC;
3 out1: out STD_LOGIC);
4 end nandgate; 5 architecture nandgate_arch ofnandgate is
6 signal connect1: STD_LOGIC;
7 begin
8 connect1
8/8/2019 Hsk Slides
25/93
Different data types
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
26/93
Data types
Chapter2
Identifiers
Data
objects Data types
Constants
(Global)
Signals
(Global)
Variables
(Local)
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
27/93
Chapter2
Identifiers
Data
objects Data types
Constants
(Global)
Signals
(Global)
Variables
(Local)
VHDL 2. Identifiers, data objects and datatypes ver.9b
Datatypes
Enumeration:Red, blue
Boolean:TRUE,FALSE
Bit:0,1
Charactera,b
String:text
Integer:13234,23
Float:0.124
standard logic:
Std_logic_vector
Different data types
8/8/2019 Hsk Slides
28/93
Data types
VHDL 2. Identifiers, data objects and datatypes ver.9b
enumeration
Integer
Physical
floating
scalar
array
recordcomposite
Bit
Bit_vector
Boolean
Std_ulogic
predefined
Numeric types
Discretetypes
8/8/2019 Hsk Slides
29/93
Scalar type
Is a type whose values have no elements.
Values cannot contain composite elements.
All values are in order.Each value of discrete ornumeric have positional number associated
with it.
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
30/93
Enumerated Types
An enumeration type is defined by listing (enumerating) allpossible values explicitly.
Declaration Format:
TYPE type_name IS (enumeration_ident_list);
type std_ulogic is (U,0,1,Z,W,L,H,-);
then we can declare
signal carry:std_ulogic:=U;
The definition explicitly enumerates all possible values that anobject of this type can assume
User defined values consisting of identifiers, character literals.
Every value has position number, starting from 0 and fromleftmost element also next number is one greater than leftnumber.
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
31/93
Predefined enumeration types
TYPE bit IS (`0','1');
TYPE boolean IS (false,true); TYPE severity_level IS
(note,warning,error,failure);
TYPE character IS (`a','b','c',...);
VHDL 2. Identifiers, data objects and datatypes ver.9b
Used with assert statements
8/8/2019 Hsk Slides
32/93
More Examples
TYPE Two_level_logic IS (`0','1');
TYPE Three_level_logic IS (`0','1','Z');
TYPE micro_op IS load,add,sub,mul);
TYPE Opcode IS
(Add,Add_with_carry,Sub,Sub_with_carr
y,Complement);
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
33/93
Difference between to and downto
Given:
signal a : std_logic_vector( 2 downto 0);
Create a 3-bit bus c using toinstead ofdownto in the
declaration.
Draw the circuit for this statement: c
8/8/2019 Hsk Slides
34/93
Answer
signal c : std_logic_vector(0 to 2);
c
8/8/2019 Hsk Slides
35/93
Exercises
Declare an emulation type of the traffic light..
Declare an emulation type of the 7 notes of
music. Answer:type traffic_light is (yellow, green, red, yellow_green); signal tr1: traffic_light; -- so tr1 is a signal and can be one of the 5 cases.
VHDL 2. Identifiers, data objects and datatypes ver.9b
8/8/2019 Hsk Slides
36/93
Integer type
Integers are the set of positive and negative whole numbers.
Upper and lower range constraints must be integer range.
Declaration format:
TYPE type_name IS RANGE int_range_constraint;
Predefined integer type:
TYPE integer IS RANGE 2147483648=[ -2 (31) ] TO 2147483647= [2 (31) -1];
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
37/93
RANGE RANGE
Identifies subset of values.
May be used with type declarations or object declarations
Format:
RANGE begin direction end
Direction may be:
Ascending - TO
Descending - DOWNTO
Examples:
TYPE day IS RANGE 1 TO 31;
TYPE voltage IS RANGE 12 DOWNTO -12;
SIGNAL in_volts: voltage RANGE 5 DOWNTO 0; -- object declaration
with range a subset of the full range of voltage.
When the range clause does not appear in an object declaration, the object
assumes the full range of the type which appears in them declaration.
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
38/93
Integer type (depends on your tool; ituses large amount of logic circuits for
the implementation of integer/float
operators) E.g.
Maximum range from -(2^31-1) to (2^31-1)
e.g. variable a: integer range -255 to 255
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
39/93
Floating type
Floating Points are the set of positive and negative numbers which contain
a decimal point.
Upper and lower range constraints must contain a decimal point.
Declaration format:
TYPE type_name IS RANGE range_constraint;
Predefined floating point type:
TYPE real IS RANGE -1.79769E308 TO 1.79769E308;
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
40/93
Floating type
-1.0E38 to 1.0E38
For encoding floating numbers, but usually
not supported by synthesis tools ofprogrammable logic because of its huge
demand of resources.
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
41/93
Physical type
Describes objects in terms of a base unit, multiples of
base unit, and a specified range.
Declaration format:
TYPE type_name IS RANGE range_constraints
UNITS
base_unit;
[ -- multiples;]
END UNITS;
8/8/2019 Hsk Slides
42/93
Examples
Predefined physical type:
TYPE time IS RANGE -2**(31-1) TO 2**(31-1)
UNITS
fs; --femtosecond =10-15
sec ps =1000 fs; --picosecond =10-12 sec
ns =1000 ps; --nanosecond =10-9 sec
us =1000 ns; --microsecond =10-6sec
ms =1000 us; --millisecond =10-3sec
sec =1000 ms; --second
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
43/93
Example cont
min =60 sec; --minute
hr =60 min; --hour
END UNITS;
Example:
TYPE Resistance IS RANGE 1 TO 10E9
UNITS
ohm; --the base unit.
kohm=1000 ohm; --secondary unit, multiple of base unit.
END UNITS;
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
44/93
Boolean, Bit Types
Boolean (true/false), character, integer, real,string, these types have their usual meanings.In addition, VHDL has the types: bit, bit_vector,
The type bit can have a value of '0' or '1'. Abit_vector is an array of bits.
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
45/93
Examples of some common types
Type BOOLEAN is (FALSE, TRUE)
type bit is (0 ,1);
type character is (-- ascii string) type INTEGER is range of integer numbers
type REAL is range of real numbers
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
46/93
Std_ulogic standard
Type STD_ULOGIC, defined in the package STD_LOGIC_1164,is an
enumeration type as:
(U--- uninitialized
x--- forcing unknown
0--- forcing 0
1--- forcing 1
z--- high impedance
w---weak unknown
L---Weak 0
H--- Weak 1
---- Dont care);
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
47/93
DefineArray or a bus
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
48/93
Array type
Multiple values of same type under single identifier.
One or more dimensions
the position of each element in an array is given by a scalar value
called index. referenced by indices.
Indices type must be integer or enumeration.
Declaration format:
TYPE array_type_name IS ARRAY range_constraints) OF type;
Predefined array types:
TYPE string IS ARRAY (positive RANGE ) OF character; TYPE bit_vector IS ARRAY (natural RANGE ) OF bit;
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
49/93
Example:
TYPE Column IS RANGE 1 TO 80;
TYPE Row IS RANGE 1 TO 24;
TYPE Matrix IS ARRAY (Row,Column) OFboolean;
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
50/93
Constrained or unconstrained.
Boundaries of constrained array are stated:
TYPE array_1 IS ARRAY (integer RANGE -10 TO 25) OFbit;
TYPE array_1_too IS ARRAY (-10 TO 25) OF bit;
(NOTE: integer is optional)
Boundaries of unconstrained array are left open:
TYPE array_2 IS ARRAY (integer RANGE ) OF bit;
When we declare object of unconstrained type , wehave to provide a constraint that specifies the indexbounds.
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
51/93
example
Type sample isarray(natural range ) ofinteger;
Now create an object of this unconstrained
type, Variable short_ sample: sample(0 to 63);
This indicate that index value for the variableshort_ sample are natural numbers in theascending range 0 to 63.
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
52/93
Array Subtypes:
Subsets of specified array types.
Do not define a new array type.
TYPE that SUBTYPE is based on must be an unconstrained array.
Declaration format: SUBTYPE name IS (array_name RANGE range_constraint);
Example:
TYPE data IS ARRAY (natural RANGE ) OF bit;
SUBTYPE low_range IS (data RANGE 0 TO 7);
SUBTYPE high_range IS (data RANGE 8 TO 15);
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
53/93
Advantage of subtypes
There are several advantages of subtypes. The primary
advantage is to clarify what is being done in the model. They
make it easier to visualize what is being stored and why by
breaking large groupings of values into smaller groupings.
Each "smaller grouping" can have a name which moredescriptively tells what values it represents.
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
54/93
Array Initialization:
1.Initial values for a one-dimensional array type
signal must be placed in a set of parenthesis
and should follow the := symbol in the signal
declarations. The initial values of individual
array elements should be separated by
commas.
SIGNAL sq4: bit_nibble :=(`1','0','1','1');
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
55/93
Array Initialization cont..
2. Nested sets of parentheses as should be used for multi-
dimensional arrays. In this case, the top level set of parentheses
corresponds to the left-most range of the array.
TYPE bit_4by8 IS ARRAY(3 DOWNTO 0, 0 TO 7) OF BIT;
SIGNAL sq_4_8: bit_4by8 :=
(
(`0','0','0','0','1','1','1','1'),
(`0','0','0','1','1','1','1','1')(`0','0','1','1','1','1','1','1')
(`0','1','1','1','1','1','1','1')
);
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
56/93
Exercise???
What are aggregates?
How an aggregate can be used to provide an
initial value to an array object?
How aggregate specified in constant
declaration?
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
57/93
Record Type
A second composite type is the records type. Arecord consists of multiple elements that may beof different types.
The syntax for a record type is the following:
type name is
record
identifier :subtype_indication;
: identifier :subtype_indication;
endrecord;
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
58/93
As an example type MY_MODULE is
record
RISE_TIME :time;
FALL_TIME : time;
SIZE : integer range 0to 200; DATA : bit_vector (15downto 0);
endrecord;
signal A, B: MY_MODULE;
To access values or assign values to records, one can use one of the following methods:
A.RISE_TIME
8/8/2019 Hsk Slides
59/93
Other Example
type pin_type isrange 0 to 10;
Typemodule is
record
SIZE : integer range 0to 200;
Critical delay: Time;
No_inputs : pin_type;
No_outputs : pin_type;
endrecord;
signal nand_comp: MODULE;
Nand_comp := (50,20ns,3,2);
To access values or assign values to records, one can use one of the followingmethods:
Nand_comp . No_inputs := 2;
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
60/93
Entity
Entitydeclaration
describes the input/outputports of a module
VHDL 2. Identifiers, data objects and data
types ver.9b
entity reg4 is
port ( d0, d1, d2, d3, en, clk : in bit;
q0, q1, q2, q3 : out bit );
end entity reg4;
entityname portnames portmode (direction)
porttypereservedwords
punctuation
8/8/2019 Hsk Slides
61/93
Conti..
Omit entity at end of entity declaration
VHDL 2. Identifiers, data objects and data
types ver.9b
entity reg4 is
port ( d0, d1, d2, d3, en, clk : in bit;
q0, q1, q2, q3 : out bit );
end reg4;
8/8/2019 Hsk Slides
62/93
Modes
The NAME_OF_ENTITY is a user-selected identifier
signal_names consists of a comma separated list of one or more user-
selected identifiers that specify external interface signals.
mode: is one of the reserved words to indicate the signal direction:
in indicates that the signal is an input out indicates that the signal is an output of the entity whose value can
only be read by other entities that use it.
buffer indicates that the signal is an output of the entity whose value
can be read inside the entitys architecture
inout the signal can be an input or an output.
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
63/93
Architecture
Architecture body
describes an implementation of an entity
may be several per entity
Behavioralarchitecture describes the algorithm performed by the module
contains
process statements, each containing
sequential statements, including signal assignment statements and
wait statements
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
64/93
Delays
Three types
Inertial delay
Transport delay
Delta delay
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
65/93
Delay models
Inertial delay
Default delay model
Suitable for modeling delays through devices such as gates
Transport Delay
Model delays through devices with very small inertia, e.g., wires
All input events are propagated to output signals
Delta delay
What about models where no propagation delays are specified?
Infinitesimally small delay is automatically inserted by the simulator to
preserve correct ordering of events
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
66/93
Transport delay
architecture transport delay ofhalf_adderis signal s1, s2: std_logic:= 0;
begin
s1
8/8/2019 Hsk Slides
67/93
Delta delay
library IEEE;
use IEEE.std_logic_1164.all;
entity combinational is
port (In1, In2: in std_logic;
z : out std_logic); end entity combinational;
VHDL 2. Identifiers, data objects and data
types ver.9b
architecturebehaviorofcombinational
signal s1, s2, s3, s4: std_logic:= 0;
begin
s1
8/8/2019 Hsk Slides
68/93
IN1
IN2
Z
S1
S2
S3
S4
10 20 30 40 50 60 70
10 2 3
In2
S2
S3
Z
Internal ordering established
by the simulator
Delta
time
8/8/2019 Hsk Slides
69/93
Models
Data flow
Behavioral model
Structure model
Mixed model
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
70/93
Data flow model
View of data as flowing through design, from input to output
An operation is defined in terms of a collection of data
transformation
Set of concurrent statements
It used the logical equations
Level of abstraction is algorithmic or gate
Need Boolean equation as design specification
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
71/93
example
library IEEE;
use IEEE.std_logic_1164.all;
entity combinational is
port (In1, In2: in std_logic;
z : out std_logic); end entity combinational;
VHDL 2. Identifiers, data objects and data
types ver.9b
architecture dataflow ofcombinational
signal s1, s2, s3, s4: std_logic:= 0;
begin
s1
8/8/2019 Hsk Slides
72/93
Difference:signal variable
Aredeclaredviasignaldeclaration
statementorentityportdefinitions.
Maybeanydatatype
Similarto hardwareandarenotupdated
untiltheendoftheprocess.
Usesignalsfor hardwaredescriptions
Signalsmaybeslower
Ifuassignseveralvaluestoasignal in
oneprocess, onlythefinalvalue isused.
Isdeclaredwithinablocks,
process,procedure orfunction.
Anyscalaroraggregatedatatype. Are immediatelyupdated
Theyareutilized inbehavioral
descriptions.
Variablesallow quick simulation
Whenyouassignavaluetoavariable
,theassignmenttakes immediately.Avariablemaintains itsvalueuntilspecify
newvalue.
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
73/93
Variable vs. signalExample:signal
Example:variable
y ARCHITECTURE test1 OF mux IS
y SIGNAL x : BIT := '1';
y SIGNAL y : BIT := '0';
y BEGIN
y PROCESS (in_sig, x, y)
y BEGIN
y x
8/8/2019 Hsk Slides
74/93
Exercise????
VHDL 2. Identifiers, data objects and data
types ver.9b
Differentiate between concurrent andsequential statements
8/8/2019 Hsk Slides
75/93
Concurrent statements
process statement -- behavior
concurrent procedure call -- behavior
concurrent signal assign. -- data flow
component instantiation -- structure
generate statement -- structure
block statement -- nesting
concurrent assertion stmt -- error check
8/8/2019 Hsk Slides
76/93
Behavioral model
Architecture body
describes an implementation of an entity
may be several per entity
Behavioralarchitecture
describes the algorithm performed by the module contains
process statements, each containing
sequential statements, including
signal assignment statements and
wait statements
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
77/93
Syntax of process in behavioral model
y PROCESS statements are collections of actions executed in sequence. These actions are calledsequential statements. The types of actions include assigning values to signals, conditionalexecution, repeated executions etc.
y [process_label:] process [ (sensitivity_list) ] [is]
y [process_declarations]
y begin
y
list of sequential statements such as:y signal assignments
y variable assignments
y case statement
y exit statement
y if statement
y loop statement
y next statement
y null statement
y procedure call
y wait statement
y endprocess[process_label];
8/8/2019 Hsk Slides
78/93
Sensitivity list
Sensitivity list is a list of signals to which the process is
sensitive to. A process gets active (or executed) only when
there is an event on at least one of the signals in the
sensitivity list.
All asynchronous input signals and clock signal gets
included in the sensitivity list.
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
79/93
Example half adder
y library IEEE; use IEEE.STD_LOGIC_1164.all;
y entity ha_beha_en isy port( A : in BIT; B : in BIT;
y S : out BIT; C : out BIT );
yend ha_beha_en;
y architecture ha_beha_ar ofha_beha_en isy Begin
y process_beh:process(A,B)y begin
y S
8/8/2019 Hsk Slides
80/93
Full adder
VHDL 2. Identifiers, data objects and data
types ver.9b
A H
A
H
A
cin
B
sum
cout
In3
In2
In1
ports
sum
carry
a
bout
b
8/8/2019 Hsk Slides
81/93
EXAMPLE OF FULL ADDER
y library ieee;
y use ieee.std_logic_1164.all;
y entity FULL_ADDERis
y port (A, B, Cin : in std_logic;
y Sum, Cout : out std_logic);
y endFULL_ADDER;
y
y architecture BEHAV_FA ofFULL_ADDERis
ysignalint1, int2, int3: std_logic;
y begin
y -- Process P1 that defines the first half adder
y P1: process(A, B)
y begin
y int1
8/8/2019 Hsk Slides
82/93
Structure model
y Define the components used in the design
y Describe the interconnection of these
components
y Structural models can be easily generated
from schematics
y Structural descriptions can be nested
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
83/93
VHDL 2. Identifiers, data objects and data
types ver.9b
-- top level
-- bottom level
full_adder.vhd
half_adder.vhd
or_2.vhd
and2.vhd xor2.vhd
o Nested structural descriptions to produce hierarchical models
o Behavioral models of components at the bottom level must exist
Hierarchy and Abstraction
8/8/2019 Hsk Slides
84/93
Structure model (brief)
Structuralarchitecture
implements the module as a composition of subsystems
contains
signal declarations, for internal interconnections
the entity ports are also treated as signals component instances
instances of previously declared entity/architecture pairs
port maps in component instances
connect signals to component ports
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
85/93
Architecture of structure modelling
architecture architecture_name ofNAME_OF_ENTITY is
-- Declarations
component declarations
signal declarations
begin -- Statements
component instantiation and connections
:
end architecture_name;
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
86/93
Component declaration
component component_name [is]
[port (port_signal_names: mode type;
port_signal_names: modetype;
:
port_signal_names: modetype);]
end component [component_name];
Component Instantiation and
8/8/2019 Hsk Slides
87/93
Component Instantiation and
interconnections The syntax for the components instantiation is as follows,
instance_name : component name
portmap(port1=>signal1, port2=> signal2, port3=>signaln);
portmap(signal1, signal2,signaln);
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
88/93
VHDL 2. Identifiers, data objects and data
types ver.9b
Full adder with structure
In1 H
A
H
A
c_in
In2
sum
c_out
s2
s3
s1
8/8/2019 Hsk Slides
89/93
Entity declaration of full adder
Entity full_adder is
Port(In1,In2,c_in: in std_logic; Sum,c_out: out std_logic);
End full_adder;
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
90/93
Full adder with structure model
VHDL 2. Identifiers, data objects and data
types ver.9b
architecture structural offull_adderis
component half_adderis -- the declaration
port (a, b: in std_logic; -- of components you will use
sum, carry: out std_logic);
end component half_adder;
component or_2 isport(a, b : in std_logic;
c : out std_logic);
end component or_2;
signal s1, s2, s3 : std_logic;
begin
H1: half_adderport map (a => In1, b => In2, sum=>s1, carry=>s3);
H2:half_adderport map (a => s1, b => c_in, sum =>sum,carry => s2);
O1: or_2 port map (a => s2, b => s3, c => c_out);
end architecture structural;
unique name of the components
component typeinterconnection of the component
ports
component instantiation statement
8/8/2019 Hsk Slides
91/93
Exercise???
Difference between component declaration
and component instantiation.
Difference between actual and formals.
What are different types of associations.
VHDL 2. Identifiers, data objects and data
types ver.9b
8/8/2019 Hsk Slides
92/93
Structure Example exercise
int_clk
d0
d1
d2
d3
en
clk
q0
q1
q2
q3
bit0
d_latch
d
clk
q
bit1
d_latch
d
clk
q
bit2
d_latch
d
clk
q
bit3
d_latch
d
clk
q
gate
and2
a
b
y
8/8/2019 Hsk Slides
93/93
Concurrent signal assignment
The syntax is as follows:
Target_signal
Top Related