Echo Generation
The DSP kit has sampling frequency of approx. 8KHz.
For echo generation the mathematical expression used was:
( )
( )
( )
x(n) = s(n)
Where, d is the delay i.e. takes as 1.5 seconds.
x(n) is the current input.
So d = 12,000 samples i.e. 12000/8000 = 1.5 seconds
The program is given below:
.def code
.mmregs
.text
.c54cm_off;
.arms_off;
.cpl_off;
.noremark 5573
config .usect "config",20,1; configuration data of AIC23
code:
BSET SXMD; set SXMD bit8 of ST1_55
BCLR M40; clear M40 bit10 in ST1_55
BCLR #11,ST0_55; clear the carry
BSET #11,ST1_55; disable all maskable interrupts
BCLR #05,ST1_55; turn C54 compatibility off
BCLR #15,ST2_55; turn DSP mode on
BCLR #14,ST1_55; DP direct addressing mode. Direct accesses
;to data space are made relative to
the data page register (DP).
;;;;;;;;Change-2
BSET CDPLC ;Circular Addressing
;*************************
******
; Open the codec
;*******************************
;This configures the McBSPs to communicate with an AIC23 codec.
;McBSP1 is used in Master SPI format as the control channel with clocks being
;coming from the internal sample rate generator. McBSP2 is the data
;channel. It is used in slave mode using the codec's bi-directional
;DSP data format. Each sample consists of one frame with two 16-bit
;elements corresponding to left and right. Clocks and frame syncs on
;the data channel are generated by the AIC23 external to the DSP.
;======== mcbspCfg1 ========
;Create a mcbsp configuration object use for the mcbsp1 talking
;to the aic23 codec. The format is SPI with 16-bit frames. All clocks
;and frame syncs are generated internally.
; AR0 -> McBSP1 registers.
AMOV #2C04h,XAR0;
MOV #0100h,port(*AR0+) ;
;port(*AR0);SPCR2_1
MOV #1000h,port(*AR0+); || port(*AR0);SPCR1_1
MOV #0000h,port(*AR0+);RCR2_1
MOV #0000h,port(*AR0+);RCR1_1
MOV #0000h,port(*AR0+);XCR2_1/
MOV #0040h,port(*AR0+);XCR1_1
MOV #2013h,port(*AR0+);SRGR2_1
MOV #0063h,port(*AR0+);SRGR1_1
ADD #6h,AR0 ;
MOV #1A0Ah,port(*AR0);PCR_1
SUB #6h,AR0;
;Start McBSP by setting Trasmitter bit to 1
MOV #2C04h,AR0;SPCR2_1
MOV #0101h,port(*AR0);
;;;;;Change-3
MOV #0h,BSAC ; Offset for circular addressing od CDP
MOV #12000,BKC ;Size of Block for Circular Addressing
AMOV #004000h,XCDP ;starting address for CDP
;*******************************
;configuration of the AIC23 registers
;*************************************************************************
; Configure the DMA Channel 0 to send the register values to AIC via McBSP1
; Channel 0 is used for data transfer from SARAM port to McBSP #1 port
;************************************************************************
;DMA Global Control Register
AMOV #0E00h,XAR1;
MOV #4h,port(*AR1); Global Control Register FREE=1
; AR1 -> DMA channel_0
AMOV #config,XAR4 ;AR4 -> Source
AMOV #2C03h,XAR5 ; AR5 -> Destination
AMOV #0C00h,XAR1 ; AR1 -> DMA channel_0 register
MOV #0601h,port(*AR1+);CSDP_0
MOV #1046h,port(*AR1+);CCR disable channel-0 and cofigure
;the reg with auto-
increment of address
MOV #8h,port(*AR1+); CICR_0;
MOV #0h,port(*AR1+); clear the CSR register
MOV XAR4,AC0 ;
SFTS AC0,#1,AC1;
MOV AC1,port(*AR1+);Source byte address
MOV HI(AC1),port(*AR1+);Source 'config'
MOV XAR5,AC0 ;
SFTS AC0,#1,AC1;
MOV AC1,port(*AR1+);Peripheral byte address
MOV HI(AC1),port(*AR1+);Destination DXR1_0
MOV #0Bh,port(*AR1+);DMA_CEN Number of 16bit word to be transferred
;/transmitted
MOV #01h,port(*AR1+);DMA_CFN Number of frames per block
MOV #0h,port(*AR1+);DMA_CEI
MOV #0h,port(*AR1); DMA_CFI
;Prime DXR by writing first element
MOV #2C03h,AR0;
MOV #8000h,port(*AR0+);
;Enable channel_0
MOV #0C01h,AR1;
MOV #10C6h,port(*AR1);
;Start Sample Rate Generator and Enable Frame Sync Logic
MOV #03C1h,port(*AR0); SPCR2_0
;Allow Sample Rate Generator to Stablize
MOV #35h, BRC0;
RPTBLOCAL endofloop1-1
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
endofloop1
;Check all the data have been transmitted by DMA channel_0
;by reading channel status register
MOV #0C03h,AR1;
LOOP1 MOV PORT(*AR1),T0;
BTST @#3h,T0,TC1;
NOP;
NOP;
NOP;
BCC LOOP1,!TC1
;***************************************************************
;This section configures MCBSP2 for 32-bit frames consisting of a
;16-bit word for each of the left and right channels.
;The AIC23 is in master mode, DSP format and generates clocks
;and frame syncs externally.
; ======== mcbspCfg2 ========
; Create a mcbsp configuration object use for the mcbsp2 talking
; to the aic23 codec.
; AR0 -> McBSP2 registers.
;************************************************************
AMOV #3004h,XAR0;
MOV #0100h,port(*AR0+);SPCR2_2
MOV #0000h,port(*AR0+);SPCR1_2
MOV #0000h,port(*AR0+);RCR2_2
MOV #0140h,port(*AR0+);RCR1_2
MOV #0000h,port(*AR0+);XCR2_2
MOV #0140h,port(*AR0+);XCR1_2
MOV #0000h,port(*AR0+);SRGR2_2
MOV #0000h,port(*AR0+);SRGR1_2
ADD #6h,AR0;
MOV #0003h,port(*AR0);PCR_2
SUB #6h,AR0;
;Start McBSP by setting Trasmitter and Receiver bit to 1
MOV #3004h,AR0; SPCR2_2
MOV #0101h,port(*AR0+);XRST_ = 1
MOV #0001h,port(*AR0);RRST_ = 1
;Prime DRR by reading first element
MOV #3001h,AR0;
MOV PORT(*AR0),AC0;
;Prime DXR by writing first element
MOV #3003h,AR0;
MOV AC0,PORT(*AR0);
;Start Sample Rate Generator and Enable Frame Sync Logic
MOV #3004h,AR0;
MOV #03C1h,port(*AR0);
;Allow Sample Rate Generator to Stablize
MOV #35h,BRC0;
RPTBLOCAL endofloop2-1
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
endofloop2
;*****************************
; Read a data sample and wirte it to codec
;******************************
MOV #3003h,AR0;
MOV #3001h,AR2;
LOOP_13 MOV #3005h,AR7;
MOV port(*AR7),T1;
; poll whether the word can be ready to receive
BTST @#1,T1,TC1;rrdy
BCC LOOP_13,!TC1;
;Read the data
MOV port(*AR2),T2;
MOV T2,AC2
MOV T2,*CDP+
MOV *CDP, AC1
SFTL AC1, #-1
ADD AC1, AC2
SFTL AC2, #-1
MOV AC2,T2
LOOP_131 MOV #3004h,AR6;
MOV port(*AR6),T0;
; poll whether the word is ready ot transmit
BTST @#1,T0,TC1;xrdy
BTST @#2,T0,TC2;xempty
BCC LOOP_131,!TC1 | TC2;
; set the register with value in AC1
MOV T2,port(*AR0);
B LOOP_13;
;*****************************
; close the codec
;******************************
MOV #2C03h,AR0;
MOV #6h,AC0;
MOV #00ffh,AC1;
OR AC0
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