Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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ESE 570 DYNAMIC LOGIC GATES AND CELLS
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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DYNAMIC LOGIC GATES: valid logic level are not steady-state op points and depend on temporary storage of charge on parasitic node capacitances. Outputs are generated in response to input voltage levels and a clock. Requires periodic updating or refresh.
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Comparison of Static and Dynamic Logic Implementations
Y
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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1
11
VDD
VDD V
DD
VDD
VDD
more robust
Comparison of Static and Dynamic Logic Implementations
Y
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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NOTE: No cross-coupled inverters)
Flip-Flop
Latch circuit:
Latch
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Vy = V
T0n = 1V
+V x−7.45V ,+V x−2.55V ,
(VGD
> VT0p
)
Vy ≤ V
T0,M3 = 1.0 V;
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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+V x−7.45V ,+V x−2.55V ,
i.e. Vx can drop from V
x-max = V
DD – V
TMP to V
x-min = 2.55 V due to charge
leakage before VQ is effected (i.e. the output changes state).
V x=V x−min=2.55V
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Cext
Cext
Cext
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Cgb
= Cgbn
+ Cgbp
for M1, M2Cext
Cx = C
ext + C
j
Cx = C
ext + C
j
C x=C ext)AC j0
*1)V x
.0
)PC j0sw
*1)V x
.0sw
Vx-max
to Vx-min
due to leakage.
min + thold ,=- t=C x−min
I leakage−max-V x=
C x−min
I leakage−max+V x−max−V x−min,
Cx-min
= Cext
+ Cj-min where C
j-min = C
j (V
x = V
x-max)
Vx-max
= VDD
– VTn,MP
and Vx-min
= 2.55 V
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Vx-max
. Assume
VDD
leakage-max
(min) hold time if
V x−max=V DD−V TMP V x−min=2.55V
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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4.80 fF24 µm 5.20 fF
VT0 = 1.0 VGAMMA = 0.4 V1/2
PHI = -0.6 VPB = 0.88 VPBsw = 0.95 VXJ = 0.2 µmI
leakage,max = 0.85 pA
Cox
= 0.06 fF/µm2
C'metal
= 0.036 fF/µm2
C'poly
= 0.055 fF/µm2
Cj0 = CJ = 0.095 fF/µm2
Cj0sw
= CJSW = 0.200 fF/µm
Cn+p
= CJ An+p
= 0.095 fF/µm2 (36 µm2 + 12 µm2 + 0.8 µm2) = 4.56 fFC
n+p+ = CJSW P
n+p+ = 0.200 fF/µm (18 µm + 6 µm + 2 µm) = 5.20 fF
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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4.80 fF 4.18 fF
4.18 fF 8.19 fF
8.19 11.3ms
8.02 fF
8.02 11.04 ms
C j−min=Cn) p
*1)V x
.0
)C n) p)¿
*1)V x
.0sw
= 4.56 fF
*1)3.680.88
) 5.20 fF
*1)3.680.95
=4.36 fF
4.36 fF 8.20 fF
min + thold ,=C x−min
I leakage−max+V x−max−V x−min,=
8.20 x10−15 F0.85 x10−12 A
+3.68V−2.55V ,=10.9ms
Need Vx,max
to determine Cj,min
V x−max=V DD−V T ,MP=V DD−VT0−GAMMA+*∣−PHI)V SB∣−*∣−PHI∣,.=5.0V−1.0V−0.4V 1/2+*∣0.6V)V x−max∣−*∣0.6V∣,
Solving for Vx-max
: Vx-max
= 3.68 V
Cj-min
V x−max−4.3V=−0.4V 1/2+*∣0.6V)V x−max∣,
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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A
CB
GH
DEF
X
Y
Z
ABC
XG
HZ E
D
F
X
Z
YY
COMB LOG1
Synchronous CASCADED Dynamic Logic
COMB LOG2 COMB
LOG3
Asynchronous Combinational Static LogicCONVERTING STATIC LOGIC TO DYNAMIC LOGIC
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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for Cink Coutk to charge to new value for k = 1,2,3.
When Vout(i)
= 0V (or 5V) and Vin(i+1)
= 5V (or 0V) for i = 1,2 (stage)
“Charge Sharing” is an issue when φ1, φ
2 close.
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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“Rule of Thumb” make Cout1
= 10 Cin2
Vb >> V
a
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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If Vb = 0 and V
a = V
DD => V R≈
C in2V DD
Cout1)C in2
V R≈C in2Cout1
V DD≪V DD if Cout1
>> Cin2
“Rule of Thumb” make Cout1
= 10 Cin2
Va >> V
b
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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F1
F1
F2
F2
F1=+A)B,⋅C
F2=F1⋅D
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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F1F2
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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m
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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VDD
A
CK
Mp
Me
Z
DYNAMIC CMOS PRECHARGE – EVALUATE LOGIC
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Z
Z
of C is complete
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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CK = 0 => Z = ?CK = 1 => Z = ?
EXAMPLE
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Z = “0” when CK = “1” AND D AND E = “1” OR A AND B = “1” OR A AND C = “1”
Z = “1” when CK = “0”independent of inputs
“1”
EXAMPLE
Z=A⋅+B)C ,)D⋅E
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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ADVANTAGES AND DISADVANTAGES VS. STATIC LOGIC
ADVANTAGES ?
DISADVANTAGES ?
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Cascaded Domino CMOS Logic Gates
propagating
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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0 → 1
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Weak pull-up (small kp, i.e. small (W/L)
p) pMOS transistor used to maintain a
pre-charged high if the clock were to stop. Suitably weakened so that it does not interfere with pull-down during evaluation when the clock is operational.
“weak keeper”
(W/L)p-keeper
< (W/L)n-min
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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ZZ
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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= G2 + P2*C1= G3 + P3*C2
= G4 + P4*C3
Since all nodes are pre-charged there is no charge-sharing.
C4
C3
C2
C1
Z4
Z3
Z2
Z1
P0
Z1 = G1 + P1 * P0Z2 = G2 + P2 * G1 + P2 * P1 * P0 = G2 + P2 * Z1Z3 = G3 + P3 * G2 + P3 * P2 * G1 + P3 * P2 * P1 * P0 = G3 + P3 * Z2Z4 = G4 + P4 * G3 + P4 * P3 * G2 + P4 * P3 * P2 * G1 + P4 * P3 *P1 * P0 = G4 + P4 * Z3
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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CK and CK - sensitive to clock skew
NP DOMINO CMOS (NORA OR ZIPPER DOMINO) GATES
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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ADVANTAGES NORA VS. DOMINO CMOSDOMINO
1. No Inverters, i.e. save two transistors per stage.
DISADVANTAGES NORA VS. DOMINO CMOS1. Selective pull-up pMOS net is slow, e.g. pMOS
transistors require scaling.2. Floating dynamic outputs are susceptible to noise, i.e.
no inverters to drive succeeding stages.
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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T
To Next nMOS block
1 → 0or 1
0 → 1or
1 → 0
0 → 1or0 1 → 0
or 0 → 1
(N-BLOCK Inv. active)
Vo1
V02
Vo2 evaluates by selective pull up to VDD(P-BLOCK Inv. Tristate)
Vo1 evaluates by selective pull down to 0V
(N-BLOCK Inv. Tristate)(P-BLOCK Inv. active)
1 → 0
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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CK = 1
0
1 or 0
HIGH - ZINV
Vout1
Vout2
0 → 1or 0
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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CK = 0
1
HIGH - Z
1 or 0
INV
Vo1
Vo2
1 0→or 1
0 1→or 0
Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
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3.
gates.
thorough
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