Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
ELEC-E3550Integrated RF circuits
Spring 2018
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Topics of the previous lecture
Concepts related to mixers”mixing” = multiplication in time-domain = frequency shift in frequency domainConversion gain, SSB / DSB NF, IIP2 / IIP3, ICP, isolation
Active mixersCascode amplifier
Active mixerSingle-balanced mixer
Double-balanced mixerGilbert cell mixer
Passive mixersVoltage-mode passive mixer
Current-mode passive mixer
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Frequency Synthesizers (SX)
• System level & concepts• SX principles
• Phase-locked loop• ”theory” / CP-PLL / ADPLL
• Oscillators• Ring & LC
• Frequency dividers• Quadrature generation
Exercises & Homework
0 90°
A D
A D
Pre-select
Channel select
LO
I
Q
90o
DAI
DAQ Break
Break
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
SX Requirements
LO
fLO
phase noise
spurious tones
harmonics
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
SX Requirements
• Frequency span --- cover the required bandwidth + margin for PVT• Channel spacing & settling time• Phase noise• IQ-generation --- Amplitude and phase imbalance (IRR)
LO
fLO
phase noise
spurious tones
harmonics
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Impact of Phase Noise
LOInterferer
signal
Down-Conversion
Q
I
Phase noise impactsIQ-constellationReciprocal mixing
In TX, phase noise causes out-of-band spurious emission.
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Impact of Phase Noise
Phase noise requirement depends on:• Channel spacing• Modulation method (eg. compare QAM-16 vs. QAM-256)• Required sensitivity and selectivity• Specified environment (”hostile” / ”friendly”)• TX: emission mask
LOInterferer
signal
Down-Conversion
Q
I
Phase noise impactsIQ-constellationReciprocal mixing
In TX, phase noise causes out-of-band spurious emission.
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Phase Noise Specifications
System Band[MHz]
Ch. spacing[kHz]
N/C[dBc/Hz]@kHz
norm-N/C*[dBc/Hz]
IS54 824-849 30 -115@60 -132
GSM 880-915 200 -141@3000 -125
DECT 1880-1900 1728 -97@1800 -91
WCDMA 1920-1980 5000 -129@8000 -111
WLAN (b) 2400-2483.5 22000 -103@1000 -105
BlueTooth 2400-2483.5 1000 -109@1000 -111
GPS 1575.42 - -95@1000 -93
DOCSIS** 47-862 6000 -82@10 -100
DVB-S 10700-12750 fixed LO1 -95@100 -131
* Normalized to 2GHz and 1MHz, N/C~(fo/fm)2 **data over cable-TV
Phase noise specification for SX given either by• N/C at certain offset, e.g N/C@1 MHz < -120 dBc/Hz• Integrated N/C profileà can be then converted to jitter spec
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
IQ Imbalance
LNA
LO_I
LO_Q
LNA
LO_I
LO_Q
A D
A D
Hartley Receiver DCR
• LO signals (I) and (Q): equal amplitude (A) and 90-degree phase shift (f)• DA and Df results in imperfect image rejection or reduced SNR for DRC• Every signal path element contribute to IRR, but usually LO imperfections dominate• Image-Reject Ratio (IRR) is a measure of LO signal imbalance
2
21 2 cos1 2 cos
bal bal
bal bal
A AIRR
A Aqq
+ D +=
- D +
• Typically DCRs need IRR > 30 dBà Abal < 0.5 dB and ∆θ < 4°• LO chain often includes limiting amplifiersà phase error remains a challenge
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Frequency Synthesis Methods
1. Direct analog synthesis
2. Direct digital synthesis
3. Indirect digital synthesis
4. Indirect analog synthesis
”DDS”
”PLL”
”DAS”
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Direct Analog Synthesis (DAS)
Main problem for RF IC implementation: good filters can not be integrated.
DAS is in use e.g. in measurement instruments – High perf, high price
…switch
switch
switch
• Filters are filter banks and/or tunable filters• Amplifiers not drawn• Chain may include dividers as well
f1
f2f3f4
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Direct Analog SynthesisAt RF IC context we may use simplified versions of DAS.
”Manipulate a frequency tone with basic mathematical operators”- addition à mixer- substraction à mixer- division à frequency divider- multiplication à frequency doubler / tripler
Band 1
VCOFractional-N PLL
Band 2
Band 3
Band 4
Band 5
/ N1
/ N2
/ N3 N4
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Direct Digital Synthesis (DDS)
Problems:needs a high-speed D/Aneeds fclock > 3* fout
DDS is used in base stations and LF radios (e.g. military)Enables very complex modulations (military)
PhaseAccumulator
clock
data ROM D/A
time-sampledphase
time-sampledamplitude
analogsignal
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Indirect FS -- Phase-Locked Loop
Basic idea is to lock the oscillator into the incoming signal using a feedback loop.Compare to: feedback amplifier analysis in electronics
feedback systems in control theory and automation
VCO PDfRef fout
VCO PDfRef fout
1/N
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Some Books on PLL’s
• Many basic text books on RF/analog IC electronics include a chapter on PLLs– Razavi: RF Microelectronics,– Lee: The Design of CMOS RF IC,– Grebene: Bipolar and MOS Analog IC Desing, etc.
• U. Rohde: many books on PLL’s, not RF IC oriented• F. Gardner: Phaselock Techniques• R. Best: Phase-Locked Loops: design, simulation and applications• J. Crawford: Frequency Synthesizer Design Handbook• D. Wolaver: Phase-Locked Loop Circuit Design• C. Vaucher: Architectures for RF Frequency Synthesizers• D. Banerjee: PLL Performance, Simulation and Design (wireless.national.com)• ... and many more J
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
PLL
VCOspur
C/N
log w
PLL performs a high-pass filtering for the phase-errorà flat in-band noise
phasenoise
Typical Results of Linear Analysis
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Integer-N PLL:• reference frequency = channel spacing• if N is very large
• stability requires loop-BW < fref/10 à loop-BW smallà long settling time & poor phase noise reduction at high offset
• ref. source & PD noise is multiplied by N• Recall: GSM1800 ch. spacing=200 kHz, N~10000
Fractional-N Concept
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Integer-N PLL:• reference frequency = channel spacing• if N is very large
• stability requires loop-BW < fref/10 à loop-BW smallà long settling time & poor phase noise reduction at high offset
• ref. source & PD noise is multiplied by N• Recall: GSM1800 ch. spacing=200 kHz, N~10000
Basic integer-N PLL is not good for small channel-spaced systemsÞ Improvments on PLL architecture (mixers in loop, dual-loop, frac-N PLL)
Dual-modulus divider
)1(
111
1
+×+
+×
+==
=+
×+
+×+
NT
TTNT
TTNff
fN
fTT
TNf
TTT
B
BA
A
BAeffin
out
outin
BA
Bin
BA
A
/N/(N+1)fin fout
TA TB
Fractional-N Concept
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
• With the aid of dual-modulus divider division ratio can be set to N...N+1Example: TA/(TA+TB)=90%, TB/(TA+TB)=10% and N=100 => Neff » 100.1
à Frac-N PLL provides small channel step and still large loop-BW.
• Main problem : ”fractional spurs”àCan be partly compensated by randomizing the timing
and using SD noise shaping.(for details, Razavi presents an easy-to-read presentation in RF Microelectronics)
• Frac-N PLL requires more hardware and suffers from high spurios contentand increased noise level compared to int-N PLL.à use only when integer-N is not feasible.
Fractional-N Concept
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Charge-Pump PLL
PFD
1/N1
fOUT
VCO
1/N2
Loop FilterPhase-Frequency
Detector
Charge Pump
fREF
UP
DW
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
1) Analog multiplier (mixer)
KD depends on input signal level, not good !
If mixer inputs are overdriven, outputs saturates into ”0” or ”1”This is equivalent to drive a XOR gate with squarewaves.
2) Digital comparator (XOR gate)- performs essentially the same function as analog multiplier
These circuits do not provide frequency information: PD can not distiguishwhether win>wout or win<wout : this is called ”self acquisition”A small DC component in the error signal guides the loop.Therefore, it takes a relatively long time for the loop to settle.à we need a phase-frequency detector
[ ])2sin()sin(
)cos()()sin()(
2121
2121
2211
fwf
fww
-+=
-==
tVVVVKV
tVtvandtVtv
mD
Phase Detector
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
• also called ”tri-state phase detector”• two D-flipflops and AND-gate• Delay element is used to avoid
”dead-zone” problem.
+ edge-trigged circuità duty-cycles of the inputs ¹ 50% OK
+ Frequency steering
Phase - Frequency Detector
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Up/Dn control pulses from PFD are driving a buffer stage.• Three basic configurations• Key challenges:
• Linear response ( time – charge )• Matching of IUP / IDW
UP
DN
Charge Pump
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
CP creates an additional pole into transfer functionà loop becomes potentially unstable
à R has to be added for stability, and another C for attenuating ripple.
Active filter+ Can provide DC gain: additional design freedom+ (partial) remedy for charge leakage+ Not resiprocicalà suppress VCO feedthrough- Higher noise, higher component count & power
Loop Filter
Oscillator and divider will be discussed in detail later.
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Impact of Technology EvolutionRecall our earlier paradigm changes, e.g.• GaAs MESFETà Si Bipolarà CMOS• Superheterodyne receiverà DCR• Monolithic capacitors: vertical fieldà lateral field• Gilbert cell mixerà current-mode passive mixer
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Impact of Technology Evolution
“Simple PD” (mixer)PLL
Charge-pumpPLL
All-digitalPLL
1990 2000 2010
Recall our earlier paradigm changes, e.g.• GaAs MESFETà Si Bipolarà CMOS• Superheterodyne receiverà DCR• Monolithic capacitors: vertical fieldà lateral field• Gilbert cell mixerà current-mode passive mixer
“In a highly-scaled CMOS technology, time-domain resolution of a digitalsignal edge transition is superior to voltage resolution of analog signals”
R. Bogdan StaszewskiManager of
TI’s DRP group
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
All-Digital PLL
TDC
1/N
fOUT
DCOLoopFilter Dither
fREF
FCW ∑ Tune
• Frequency control word (FCW) defines the target frequency• Time-to-Digital converter (TDC) describes the output frequency with a digital word• Error signal (digital) is filtered in the digital loop filter• Digital-controlled oscillator (DCO) is tuned accordingly• Dithering (compare to frac-N principle) is used to achieve fine frequency step• Prescaler used to lower fout (only if needed!) (65-nm CMOS: TDC fmax~1.7 GHz)
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
10 minutes break
à Oscillatorsà Dividersà IQ generation
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Oscillators
Oscillator is an autonomous device which generates a waveformà It converts power from DC to ”AC”
Variable frequency oscillator converts a control signal into frequencyà information is converted from one mode to another• VCO – voltage-controlled oscillator• ICO – current-controlled oscillator• DCO – digitally controlled oscillator
Oscillator waveform can be• Sinusoidal : low level of higher harmonics• Square : high level of higher harmonics, ”clock signal”
• ramp or triangular is used at LF control circuits
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Oscillator Classification
oscillation mode oscillator structure
• Stable (no oscillation)• Harmonic (sinusoidal)• Relaxation• Chaotic
• Phase shift (RC)• Gm-C• Crystal• Multivibrator
• Ring• LC
No correlation !!
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Oscillator Terms and Figures of Merit• Tuning Range : ratio of maximum and minimum oscillation frequency• VCO gain (KVCO) and its deviation (linearity)• Output power (preferably constant)• supply voltage / current consumption / power efficiency• Distortion in ”sinusoidal” oscillators• Temperature stability (Dfreq/DT)• Pushing (PSRR) (Dfreq/Dsupply)• Pulling (load) : Frequency shift caused by load impedace variation• Pulling (injection) : Frequency shift caused by external disturbance• Phase Noise / Jitter• Die Area (IC implementation) / Component count (discreate circuits)
nconsumptioPowerNoisePhaseRangeTuningFOM
*µ
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Ring Oscillator
0 1 0 11 0 1 00 1 0 1
Nfosc t2
1=
NCIf
IC
loadosc
load µÞµt
t t t
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Ring Oscillator
0 1 0 11 0 1 00 1 0 1 Real implementation is differential and
simple cross-coupling creates proper fb.
+ can be transistor-only circuità small area
+ Easy to tune, large tuning range
M power cons. is relative to freq.(although follows technology-nodes)Mmoderate (poor) phase noise
Nfosc t2
1=
NCIf
IC
loadosc
load µÞµt
t t t t t tt
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
LC Oscillator
Is negative resistor a plausible device at all?
Gloss Gneg0
1
£-
=
negloss
osc
GGLC
w
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
LC Oscillator
Is negative resistor a plausible device at all?
Transconductor in unity feedback Gunn diode
Gloss Gneg0
1
£-
=
negloss
osc
GGLC
w
i=gm×vinvin
vout
-vout
I
V
)( outm
outin vg
vR-×
=
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Negative Conductance : Unity Feedback(most of modern RFIC VCOs use these)
• Cross-coupled pair (CCP) : NMOS / PMOS / CMOS• Biasing : top / bottom / none• Advanced techniques like noise filteringà Really many different topologies exist
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
NMOS CCP Biasing
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
CMOS Cross-Coupled Pair
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Negative conductance : reactive feedbackZin
Vbias
C
C
222
1C
min jC
gZww
+-=
nmos = gm and Vbias–node is signal ground
Zin
Vbias
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Negative conductance : reactive feedbackZin
Vbias
C
C
222
1C
min jC
gZww
+-=
nmos = gm and Vbias–node is signal ground
Zin
Vbias ( )LjRcoil w++
Add a coilà oscillator
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Negative conductance : reactive feedbackZin
Vbias
C
C
222
1C
min jC
gZww
+-=
nmos = gm and Vbias–node is signal ground
Some Classical Oscillators
Zin
Vbias
bias
bias
bias bias
MEISSNER ARMSTRONG HARTLEY COLPITTS
CLAPP MILLER
bias
bias
( )LjRcoil w++
Add a coilà oscillator
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Linear Analysis Methods
B(s)
A(s)
ZG ZL0)()(
0)()(
00
00
=+=
£+=
wwww
LG
LG
XXXRRR
1) Loop-Gain
2) Negative-Resistance
3) Nodal EquationSee details:L. Larson : RF and microwave circuitdesign for wireless communications
°=Ð
³
180)()(1)()(
oscosc
oscosc
jBjAjBjAww
ww
[ ] [ ] { }{ } 0
000
=
=Þ=Þ=×
YIM
YREYVY
in each case you get two equationsone for fosc and second for -gm
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Example: Common-Drain Colpitts
RC1
C2L
Yin
gm(V1-V2)Yo
V2V1
GL
01)(
1
211
11=
+++++---
--+++
moinmin
inLin
gYR
YCCjgCjY
CjYGCjYLj
ww
www
( ) ( )in
moL
in
in CCC
ggR
G
CCCCCCL +
+++
+++
=12
21
12
)1(1w ÷÷
ø
öççè
æ+
++
++++
>in
inLo
inm CC
CC
CCGgRC
CCg1
2
2
1
2
1 2)1(
Vb
C1
C2
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Oscillator Simulations1) Small-signal analysis : loop-gain or neg-res method (AC or S-par analysis)
à rough estimation for fosc and adequate gain- NOT ACCURATE due to various large-signal phenomena
2) Time-domain analysis (TRAN) à Oscillation frequency and amplitude• You need a time-varying element for oscillation build-up
(eg. exp. incr. supply, init current in coil)• Use constant time-step• Use high precision settings
- Sweeps toilsome in some simulators- No noise analysis / analysis really heavy
3) Harmonic Balance (SST, ”steady-state” sim.)à gives oscillation frequency and amplitudeà Phase noise analysis+ Results readily in frequency domain+ Easy to sweep parameters and analyze results- Not available in all softwares, may include flaws- Not a general simulation, you can not simulate everything with SST
.option HMIN=2p HMAX=2p eps=0.1u reltol=1u
Vprobe drain1 drain2 probe
.sst oscil nharm=10 fund_osc=3G
.extract fsst label=taajuus fund_osc
.extract fsst label=Voscpp yval(vm(drain1), fund_osc)
.sstnoise v(drain1) harm (1) dec 10 1k 10e6*.plot sstnoise db(phnoise).extract sstnoise label=N/C@10k yval(db(phnoise), 1e4).extract sstnoise label=N/C@1M yval(db(phnoise), 1e6)
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Remainder: Monolithic Coils
i i
H
Very important for RF ICsà Self-learning assignment
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Remainder: Varactors
N-wellP-type substrate
N-wellP-type substrate
G
Inversion-mode PMOS
N-type accumulation-MOS
P-type substrate
G
Inversion-mode NMOS
N-isoP-type substrate
G
P-type accumulation-MOS
P-well
G
• Four types are available, inversion-mode are “ordinary” MOSFETs• Quality factor and tuning range (Cmax/Cmin) are competing properties• Typ. Q~50 at 2 GHz and TR~3• Process variation tracks to MOSFET variation
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Coarse tuning with SC-network• Large VCO tuning range (à high Kvco) is needed to compensate PVT variations.• High Kvco means that oscillator is noisy, and it also causes problems in PLL design.• How to implement large tuning range with small Kvco ?
à switched-capacitor network for coarse tuning
tune
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 16
6.5
7
7.5
8
8.5
9
9.5
10
Tuning voltage [V]
Freq[GHz]
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Oscillator Phase NoiseIntuitive approach : ”noise mixing”• Oscillator is a nonlinear circuit• oscillation swing is ”internal LO”• noise (int. & ext.) is mixed into carrier• fb-loop performs filtering
Intuitive approach II : ”Frequency modulation”• Oscillator is a VCO & ICO• noise is modulating the oscillator frequency
noise w
n
"LO"
VCO ICO
wn- wn
[ ]ttKVAtAtv mmm
VCOmosc )cos()cos(
2cos)( 000 wwww
ww --+
××+»
Low phase noiseà Minimize nonlinearityà Minimize KVCO and other sensitivities
Narrowband FMapproximation
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Oscillator Phase NoiseConsider ideal parallel LCR-type oscillator with noiseless Gneg.
There are losses in the resonator and corresponding noise source is
Impedance of the LC-tank
Tank quality factor
We have
Noise voltage is
This is both amplitude and phase noise. Oscillator performs amplitudeclippingà no amplitude noise. Thus, divide above by two. Also recall
Noise-to-carrier ratio is
kTGf
in 42
=D
0
00
2)(
ww
www
D-»D+
LjZ
QGL
LGQ
00
11ww
=Þ=
ww
ww
ww
wwD
=D
»D+ 0
00
00 2
1
2)(
QGQGZ
20222
214 ÷÷
ø
öççè
æD
=×D
=D w
wQ
kTRZf
if
v nn
RPv sigsig ×=2
20
212/ ÷÷
ø
öççè
æD
=w
wQP
kTCNsig
Low phase noiseà Maximize Psig and Q
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Leeson’s Phase Noise Model
( )ïþ
ïýü
ïî
ïíì
÷ø
öçè
æD
+×÷÷ø
öççè
æD
+×
×=Dww
ww c
sig
fQP
FkT 1)21(12log10 20L
Heurestical model (based on experiments)• fc is 1/f-noise cornerà close-in noise• constant term ”1” is included to
describe the noise floor• F is for additional noise due to –gm
10 100 1000 10000-140
-130
-120
-110
-100
-90
-80
-70
C/N[dBc/Hz]
Frequency [kHz]
-30 dB/dec
-20 dB/dec
noise floor
M fc is not the same as device’s 1/f-cornerM F is difficult to estimate a prioriM Based on linear time-invariant model
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Frequency Dividers
à There is a frequency limit, set by the limited speed of dynamic logic or increased powerconsumption, where static logic becomes superior.With 65-nm CMOS this limit is in range of 2-3 GHz, in 28-nm at 5-7 GHz.
CVfP ddDC ××= 2
Static logic (SCL = source-coupled logic)• devices have constant bias (no saturation)• no speed limitation (as with dyn. logic)• power – frequency dependency weaker• differential signals (dyn. logic single-ended)à Better immunity to noise, glitches etc.
Dynamic logic:• transistors operate as switches• many logic families• on/off switchingà limited speed• power consumption is related to speed :
• speed scales with the technology.• power consumption scales with the technology
From RF designer’s point of view there are two types of logic: dynamic & static
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
SCL D-flipflop divider
• D-flipflop in unity feedback is a divide-by-two circuit• D-flipflop consists of two D-latches
D-latchD Q
DX QX CLK
D-latchD Q
DX QX CLK
DFFfin
fout
Q
CLK
D
• resistor• PMOS• inductor
TRACK HOLD
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Divider Chains
DFF DFF
in
out
modulus ctrl
DFF DFF
in
modulus ctrl
Div-2/3 Div-3/4
Asynchronous chainDivide by 2N
Johnson counterDivide by 2N
Dual-modulusdividers
D Q
DFF
QXD Q
DFF
QXD Q
DFF
QX
D Q
DFF
QXD Q
DFF
QXD Q
DFF
QXD Q
DFF
QX
• Power consumptionlower after each division
• Higher noise (jitter)
• Each DFF runs at finàhigher power cons.• smaller noise (jitter)
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
IQ Generation
0 90°
A D
A D
Pre-select
Channel select
LO
I
Q
Four LO signals needed:0° / 90° / 180° / 270°
IQ amplitude and phasebalance (IRR) very important.
1. RC phase shiftersà polyphase RC filter2. Divide-by-two circuit3. Quadrature oscillators
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
RC Phase Shiftersvin
vinI QQp ( 90 deg)
Im ( 180 deg)
Qm ( 270 deg)
Ip ( 0 deg)
constant IQ phase balance constant IQ amplitude balance
• Narrow bandwidth• Sensitive to process spread• Post-tuning possible• Clipping amplifier helps
RC-CR network
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
RC Phase Shiftersvin
vinI QQp ( 90 deg)
Im ( 180 deg)
Qm ( 270 deg)
Ip ( 0 deg)
constant IQ phase balance constant IQ amplitude balance
• Narrow bandwidth• Sensitive to process spread• Post-tuning possible• Clipping amplifier helps
RC-CR network
vin Qp
Ip
Im
Qm
0
10
20
30
40
50
60
70
80
90
100
110
3-stage
2-stage
IRR
[dB
]
Frequency
Polyphase RC filter
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Divide-by-two IQ Generation
D-latchD Q
DX QX CLK
D-latchD Q
DX QX CLK
DFFIN
I Q
• Wide bandwidth• Compact size, easy to design well• IRR limited by latch matching• Requires double-freq signal• Non-perfect input signal:
• Amplitude error => phase error• Phase error attenuates a bit
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Divide-by-two IQ Generation
D-latchD Q
DX QX CLK
D-latchD Q
DX QX CLK
DFFIN
I Q
• Wide bandwidth• Compact size, easy to design well• IRR limited by latch matching• Requires double-freq signal• Non-perfect input signal:
• Amplitude error => phase error• Phase error attenuates a bit
IN
BIAS &POWER CTRL
I
IX
Q
QX
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Quadrature Oscillators
t t tt0° 90° 180° 270° 0°
Oscillator 2Oscillator 1 0 90 180
270 0 180
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Quadrature Oscillators
t t tt0° 90° 180° 270° 0°
Oscillator 2Oscillator 1 0 90 180
270 0 180
• Quadrature coupling resultsin increased phase noise
• Large die area
Department of Electronics and NanoengineeringStadius, Ul Haq, Khonsari
Integrated RF circuitsSpring 2018
Summary
• SX requirements, impact of phase noise, IQ imbalance (IRR)• DAS / DDS / PLL• CP-PLL• ADPLL
• Oscillators: Ring & LC• LC-oscillators: unity feedback / reactive feedback• Phase noise
• Frequency Dividers: dynamic ”CMOS” / static ”SCL”• IQ signal generation: RC polyphase / Div-2 / quadrature osc.
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