EE 5900 Advanced EE 5900 Advanced Algorithms for Robust Algorithms for Robust VLSI CAD, Spring 2009VLSI CAD, Spring 2009
Sequential CircuitsSequential Circuits
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Sequential CircuitsSequential Circuits
Combinational Logic:Combinational Logic: Output depends only on current inputOutput depends only on current input Able to perform useful operations Able to perform useful operations
(add/subtract/multiply/…)(add/subtract/multiply/…) Has no memoryHas no memory
2023.04.21 PJF - 3Sequential Circuits
Sequential Circuits (cont.)Sequential Circuits (cont.)
Sequential Logic:Sequential Logic: Output depends not only on current Output depends not only on current
input but also on past input values, e.g., input but also on past input values, e.g., design a counterdesign a counter
Need some type of memory to Need some type of memory to remember the past input valuesremember the past input values
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Sequential Circuits (cont.)Sequential Circuits (cont.)
Circuits that wehave learnedso far
Information StoringCircuits
Timed “States”
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Sequential Logic: ConceptSequential Logic: Concept
Sequential Logic circuits remember Sequential Logic circuits remember past inputs and past circuit state.past inputs and past circuit state.
Outputs from the system areOutputs from the system are“fed back” as new inputs“fed back” as new inputs With gate delay and wire delayWith gate delay and wire delay
The storage elements are circuits The storage elements are circuits that are capable of storing binary that are capable of storing binary information: memory.information: memory.
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Synchronous Synchronous vsvs. Asynchronous. Asynchronous
There are two types of sequential circuits:There are two types of sequential circuits: SynchronousSynchronous sequential circuit: circuit sequential circuit: circuit
output changes only at some discrete output changes only at some discrete instants of time. This type of circuits instants of time. This type of circuits achieves synchronization by using a timing achieves synchronization by using a timing signal called the signal called the clockclock..
AsynchronousAsynchronous sequential circuit: circuit sequential circuit: circuit output can change at output can change at anyany time (clockless). time (clockless).
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Clock SignalClock Signal
Different duty cycles
Clock generator: Periodic train of clock pulses
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Synchronous Sequential Synchronous Sequential Circuits:Circuits:
Flip flops as state memoryFlip flops as state memory
The flip-flops receive their inputs from the The flip-flops receive their inputs from the combinational circuit and also from a clock combinational circuit and also from a clock signal with pulses that occur at fixed intervals signal with pulses that occur at fixed intervals of time, as shown in the timing diagram.of time, as shown in the timing diagram.
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SR Latch (NAND version)SR Latch (NAND version)
S’
R’
Q
Q’
0 00 11 01 1
S’ R’ Q Q’0
1
1
01 0 Set
0 0 1 0 1 1 1 0 1 1 1 0
X Y NAND
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SR Latch (NAND version)SR Latch (NAND version)
S’
R’
Q
Q’
0 00 11 01 1
S’ R’ Q Q’1
1
1
0 1 0 Hold
0 0 1 0 1 1 1 0 1 1 1 0
X Y NAND
1 0 Set
2023.04.21 PJF - 11Sequential Circuits
SR Latch (NAND version)SR Latch (NAND version)
S’
R’
Q
Q’
0 00 11 01 1
S’ R’ Q Q’1
0
0
1
0 0 1 0 1 1 1 0 1 1 1 0
X Y NAND
1 0 Hold
1 0 Set0 1 Reset
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SR Latch (NAND version)SR Latch (NAND version)
S’
R’
Q
Q’
0 00 11 01 1
S’ R’ Q Q’1
1
0
1
0 0 1 0 1 1 1 0 1 1 1 0
X Y NAND
0 1 Hold
1 0 Set0 1 Reset1 0 Hold
2023.04.21 PJF - 13Sequential Circuits
SR Latch (NAND version)SR Latch (NAND version)
S’
R’
Q
Q’
0 00 11 01 1
S’ R’ Q Q’0
0
1
1
0 0 1 0 1 1 1 0 1 1 1 0
X Y NAND
0 1 Hold
1 0 Set0 1 Reset1 0 Hold
1 1 Disallowed
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SR Latch with Clock signalSR Latch with Clock signal
Latch is sensitive to input changes ONLY when C=1Latch is sensitive to input changes ONLY when C=1
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D LatchD Latch One way to eliminate the undesirable One way to eliminate the undesirable
indeterminate state in the RS flip flop is to indeterminate state in the RS flip flop is to ensure that inputs S and R are never 1 ensure that inputs S and R are never 1 simultaneously. This is done in the simultaneously. This is done in the D latch:D latch:
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Flip-FlopsFlip-Flops
Latches are “transparent” (= any Latches are “transparent” (= any change on the inputs is seen at the change on the inputs is seen at the outputs immediately).outputs immediately).
This causes synchronization problems.This causes synchronization problems. Solution: use latches to create flip-flops Solution: use latches to create flip-flops
that can respond (update) only on that can respond (update) only on specific times (instead of any time).specific times (instead of any time).
Types: RS flip-flop and D flip-flopTypes: RS flip-flop and D flip-flop
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Master-Slave FF configuration Master-Slave FF configuration using SR latchesusing SR latches
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S R CLK Q Q’
0 0 1 Q0 Q0’ Store 0 1 1 0 1 Reset1 0 1 1 0 Set1 1 1 1 1 DisallowedX X 0 Q0 Q0’ Store
Master-Slave FF configuration Master-Slave FF configuration using SR latches (cont.)using SR latches (cont.)
•When C=1, master is enabled and stores new data, slave stores old data.•When C=0, master’s state passes to enabled slave, master not sensitive to new data (disabled).
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Edge-triggered Flip-FlopsEdge-triggered Flip-Flops
D-Type Positive Edge-Triggered Flip-Flop:
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Characteristic TablesCharacteristic Tables
Defines the Defines the logicallogical properties of a flip- properties of a flip-flop (such as a truth table does for a flop (such as a truth table does for a logic gate).logic gate).
Q(t) – present state at time tQ(t) – present state at time t Q(t+1) – next state at time t+1Q(t+1) – next state at time t+1
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Characteristic Tables Characteristic Tables (cont.)(cont.)SR Flip-FlopSR Flip-Flop
SS RR Q(t+1)Q(t+1) OperationOperation
00 00 Q(t)Q(t) No change/HoldNo change/Hold
00 11 00 ResetReset
11 00 11 SetSet
11 11 ?? Undefined/InvalidUndefined/Invalid
2023.04.21 PJF - 22Sequential Circuits
Characteristic Tables Characteristic Tables (cont.)(cont.)
D Flip-FlopD Flip-Flop
DD Q(t+1)Q(t+1) OperationOperation
00 00 SetSet
11 11 ResetReset
Characteristic Equation: Q(t+1) = D(t)
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D Flip-Flop Timing D Flip-Flop Timing ParametersParameters
Setup time
Hold time
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Sequential Circuit AnalysisSequential Circuit Analysis AnalysisAnalysis: Consists of obtaining a : Consists of obtaining a suitablesuitable
description that demonstrates the description that demonstrates the time sequencetime sequence of inputs, outputs, and states.of inputs, outputs, and states.
Logic diagram: Boolean gates, flip-flops (of any Logic diagram: Boolean gates, flip-flops (of any kind), and appropriate interconnections.kind), and appropriate interconnections.
The logic diagram is derived from any of the The logic diagram is derived from any of the following:following: Boolean Equations (FF-Inputs, Outputs)Boolean Equations (FF-Inputs, Outputs) State TableState Table State DiagramState Diagram
2023.04.21 PJF - 25Sequential Circuits
Example 1Example 1
InputInput: : x(t) x(t) Output:Output: y(t) y(t) State:State: (A(t), B(t)) (A(t), B(t)) What is the What is the Output Output
FunctionFunction??
What is the What is the Next State Next State FunctionFunction??
AC
D Q
Q
C
D Q
Q
y
x A
B
CP
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Example 1 (continued)Example 1 (continued) Boolean equations Boolean equations
for the functions: for the functions: A(t+1) = A(t)x(t) A(t+1) = A(t)x(t)
+ B(t)x(t) + B(t)x(t) B(t+1) = B(t+1) = A’A’(t)x(t)(t)x(t) y(t) = x’(t)(B(t) + A(t))y(t) = x’(t)(B(t) + A(t))
C
D Q
Q
C
D Q
Q'
y
xA
A’
B
CP
Next State
Output
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State Table CharacteristicsState Table Characteristics State tableState table – a multiple variable table with the – a multiple variable table with the
following four sections:following four sections: Present StatePresent State – the values of the state variables for – the values of the state variables for
each allowed state.each allowed state. InputInput – the input combinations allowed. – the input combinations allowed. Next-stateNext-state – the value of the state at time (t+1) – the value of the state at time (t+1)
based on the based on the present statepresent state and the and the inputinput.. OutputOutput – the value of the output as a function of the – the value of the output as a function of the
present statepresent state and (sometimes) the and (sometimes) the inputinput.. From the viewpoint of a truth table:From the viewpoint of a truth table:
the inputs are Input, Present Statethe inputs are Input, Present State and the outputs are Output, Next Stateand the outputs are Output, Next State
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Example 1: State TableExample 1: State Table The state table can be filled in using the next state and The state table can be filled in using the next state and
output equations:output equations: A(t+1) = A(t)x(t) + B(t)x(t)A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =B(t+1) =A (t)x(t);A (t)x(t); y(t) =y(t) =x (t)(B(t) + A(t))x (t)(B(t) + A(t))
Present State Input Next State Output A(t) B(t) x(t) A(t+1) B(t+1) y(t)
0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0
2023.04.21 PJF - 29Sequential Circuits
State DiagramsState Diagrams The sequential circuit function can be The sequential circuit function can be
represented in graphical form as a represented in graphical form as a state diagramstate diagram with the following components:with the following components: A A circlecircle with the state name in it for each state with the state name in it for each state A A directed arcdirected arc from the from the Present StatePresent State to the to the Next StateNext State
for each for each state transitionstate transition A label on each A label on each directed arcdirected arc with the with the InputInput values which values which
causes the causes the state transitionstate transition, and, and A label: A label:
On each On each circlecircle with the with the outputoutput value produced, or value produced, or On each On each directed arcdirected arc with the with the outputoutput value produced. value produced.
2023.04.21 PJF - 30Sequential Circuits
Example 1: State DiagramExample 1: State Diagram
Which type?Which type? Diagram getsDiagram gets
confusing forconfusing forlarge circuitslarge circuits
For small circuits,For small circuits,usually easier tousually easier tounderstand thanunderstand thanthe state tablethe state table
A B0 0
0 1 1 1
1 0
x=0/y=1 x=1/y=0
x=1/y=0x=1/y=0
x=0/y=1
x=0/y=1
x=1/y=0
x=0/y=0
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