EE141
1© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 1
Digital Integrated Digital Integrated
CircuitsCircuitsA Design PerspectiveA Design Perspective
Arithmetic CircuitsArithmetic CircuitsReference: Digital Integrated Circuits, 2nd edition, Jan M. Rabaey, AnanthaChandrakasan and Borivoje Nikolic
Disclaimer: slides adapted for INE5442/EEL7312 by José L. Güntzelfrom the book´s companion slides madeavailable by the authors.
EE141
2© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 2
A Generic Digital ProcessorA Generic Digital Processor
MEM ORY
DATAPATH
CONTROL
INP
UT
-OU
TP
UT
EE141
3© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 3
Building Blocks for Digital ArchitecturesBuilding Blocks for Digital Architectures
Arithmetic unit
- Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
EE141
4© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 4
An Intel MicroprocessorAn Intel Microprocessor
9-1
Mu
x9
-1 M
ux
5-1
Mu
x2
-1 M
ux
ck1
CARRYGEN
SUMGEN
+ LU
1000um
b
s0
s1
g64
sum sumb
LU : Logical
Unit
SU
MS
EL
a
to Cache
node1
RE
G
Itanium has 6 integer execution units like this
EE141
5© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 5
BitBit--Sliced DesignSliced Design
Bit 3
Bit 2
Bit 1
Bit 0
Regis
ter
Ad
der
Sh
ifte
r
Mu
ltip
lexer
ControlD
ata
-In
Data
-Ou
t
Tile identical processing elements
EE141
6© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 6
BitBit--Sliced Sliced DatapathDatapath
Adder stage 1
Wiring
Adder stage 2
Wiring
Adder stage 3
Bit s
lice 0
Bit s
lice 2
Bit s
lice 1
Bit s
lice
63
Sum Select
Shifter
Multiplexers
Loopback B
us
From register files / Cache / Bypass
To register files / Cache
Loopback B
us
Loopback B
us
EE141
7© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 7
Itanium Integer Itanium Integer DatapathDatapath
Fetzer, Orton, ISSCC’02
EE141
8© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 8
AddersAdders
EE141
9© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 9
FullFull--AdderAdderA B
Cout
Sum
Cin Fulladder
EE141
10© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 10
The Binary AdderThe Binary Adder
S A B Ci
⊕ ⊕⊕ ⊕⊕ ⊕⊕ ⊕=
A= BCi ABCi ABCi
ABCi
+ + +
Co
AB BCi
ACi
+ +=
A B
Cout
Sum
Cin Fulladder
EE141
11© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 11
Express Sum and Carry as a function of P, G, DExpress Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) = AB
Propagate (P) = A ⊕ B
Delete = A B
Can also derive expressions for S and Co based on D and P
Propagate (P) = A ++++ B
Note that we will be sometimes using an alternate definition for
EE141
12© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 12
The RippleThe Ripple--Carry AdderCarry Adder
Worst case delay linear with the number of bits
Goal: Make the fastest possible carry path circuit
FA FA FA FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
A3 B3
S3
Ci,0 Co,0
(= Ci,1)
Co,1 Co,2 Co,3
td = O(N)
tadder = (N-1)tcarry + tsum
EE141
13© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 13
Complimentary Static CMOS Full AdderComplimentary Static CMOS Full Adder
28 Transistors
A B
B
A
Ci
Ci A
X
VDD
VDD
A B
Ci BA
B VDD
A
B
Ci
Ci
A
B
A CiB
Co
VDD
S
EE141
14© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 14
Inversion PropertyInversion Property
A B
S
CoCi FA
A B
S
CoCi FA
EE141
15© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 15
Minimize Critical Path by Reducing Inverting StagesMinimize Critical Path by Reducing Inverting Stages
Exploit Inversion Property
A3
FA FA FA
Even cell Odd cell
FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
B3
S3
Ci,0 Co,0 Co,1 Co,3Co,2
EE141
16© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 16
A Better Structure: The Mirror AdderA Better Structure: The Mirror Adder
VDD
Ci
A
BBA
B
A
A B
Kill
Generate"1"-Propagate
"0"-Propagate
VDD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
VDD
SCo
24 transistors
EE141
17© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 17
Mirror AdderMirror Adder
Stick Diagram
Ci
A B
VDD
GND
B
Co
A Ci
Co
Ci
A B
S
EE141
18© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 18
The Mirror AdderThe Mirror Adder
•The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry-generation circuitry.
•When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion
capacitances is particularly important.
•The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .
•The transistors connected to Ci are placed closest to the output.
•Only the transistors in the carry stage have to be optimized foroptimal speed. All transistors in the sum stage can be minimal size.
EE141
19© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 19
Transmission Gate Full AdderTransmission Gate Full Adder
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
EE141
20© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 20
Manchester Carry ChainManchester Carry Chain
CoC
i
Gi
Di
Pi
Pi
VDD
CoC
i
Gi
Pi
VDD
φφφφ
φφφφ
EE141
21© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 21
Manchester Carry ChainManchester Carry Chain
G2
φφφφ
C3
G3
Ci,0
P0
G1
VDD
φφφφ
G0
P1
P2
P3
C3
C2
C1
C0
EE141
22© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 22
Manchester Carry ChainManchester Carry Chain
Pi + 1
Gi + 1
φ
Ci
Inverter/Sum Row
Propagate/Generate Row
Pi
Gi
φ
Ci - 1
Ci + 1
VDD
GND
Stick Diagram
EE141
23© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 23
CarryCarry--Bypass AdderBypass Adder
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,3Co,2Co,1Co,0Ci ,0
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,2Co,1Co,0Ci,0
Co,3
Mu
ltip
lexer
BP=PoP1P2P3
Idea: If (P0 and P1 and P2 and P3 = 1)
then Co3 = C0, else “kill” or “generate”.
Also called
Carry-Skip
EE141
24© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 24
CarryCarry--Bypass Adder (cont.)Bypass Adder (cont.)
Carrypropagation
Setup
Bit 0–3
Sum
M bits
tsetup
tsum
Carrypropagation
Setup
Bit 4–7
Sum
tbypass
Carrypropagation
Setup
Bit 8–11
Sum
Carrypropagation
Setup
Bit 12–15
Sum
tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum
EE141
25© Digital Integrated Circuits2nd
Arithmetic CircuitsSlide 25
Carry Ripple versus Carry BypassCarry Ripple versus Carry Bypass
N
tp
ripple adder
bypass adder
4..8
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