8/10/2019 Design and Fabrication of a 2-bit Comparator
1/23
Concept and Design and Fabrication of a 2 BitComparator
(A design report for ECEN 5375)
By
Kendra Krueger
May 4th200
8/10/2019 Design and Fabrication of a 2-bit Comparator
2/23
Outline
Con!ept and "esign and #a$ri!ation of a 2 Bit Co%parator &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
'utine &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&2
&ntrodu!tion &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& 3
2&Cir!uit des!ription &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&33&Cir!uit si%uation &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&7
4&*orst !ase anaysis &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& 0
5&Cir!uit +ayout &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& 2,&-esting .ro!edure &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&3
7&Cir!uit #a$ri!ation &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& 4
/&"ei!e -esting &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&51&Cir!uit -esting &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& 20
0&.ossi$e i%proe%ents &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&23
&Con!usion &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&242ina Con!usion &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&24
2
8/10/2019 Design and Fabrication of a 2-bit Comparator
3/23
1.Introduction
-he !on!ept of this design is to produ!e a 2 $it !o%parator using pM' transistors& A
!o%parator !onsists of to ' gates hi!h !o%$ine in a N' to deter%ine if the
inputs are e6ua or not the ogi! is des!ri$ed in e6uation && -ransient and "C
si%uations ere !ondu!ted on the !ir!uit to deter%ine proper idth to ength ratios andorse !ase s!enarios& -he ayout as then !reated using a sti!8 diagra% hi!h as then
!onerted into a fina design ayout using Ce*in&
(A0 O B0)+(A1 O B1)=DEquation 1.1: Comparator Logic Equation
2.Circuit description
A !o%parator !an $e si%pified into NAN" and N' gates hi!h %a8e it easier toi%pe%ent ith pM' te!hnoogy& #igure 2& and 2&2 sho the !onersion fro% '
to NAN"& #ro% this point using these diagra%s and the pM' i%pe%entation of a
NAN" and N' a fu !ir!uit !an $e designed as dispayed in figure 2&3& -a$e 2& isthe truth ta$e for the !o%parator ogi!
Figure 2.1: Comparator Logic Gates
Figure 2.2: Comparator Logic with NAND gates
3
A0
B0
C0
74HC386D
A1
B1
C1
74HC386D
C0
C1
D
74HC36D
1
2
3
74HC03D
1
2
3
74HC03D
1
2
3
74HC03D
1
2
C0
74HC03D
1
2
3
74HC03D
1
2
3
74HC03D
1
2
3
74HC03D
1
2
C1
74HC03D
C0
C1
D
74HC36D
A0
B0
A1
B1
8/10/2019 Design and Fabrication of a 2-bit Comparator
4/23
A0 A B0 B C0 C "
0 0 0 0 0 0 1
0 0 0 0 0
0 0 0 0 0
0 0 0
0 0 0 0 0
0 1 0 1 0 0 1
0 0 0
0 0 0
0 0 0 0 0
0 0 0
1 0 1 0 0 0 1
0 0 0
0 0 0
0 0 0
0 0 0
1 1 1 1 0 0 1
Ta!e 2.1: De"ice Logic
4
8/10/2019 Design and Fabrication of a 2-bit Comparator
5/23
-he first design as i%pe%ented using NM' te!hnoogy as iustrated in figure 2&3&
9oeer sin!e the %aterias and pro!esses used in fa$ri!ation are $ased on pM'te!hnoogy the !ir!uit as i%pe%ented using pM' te!hnoogy as isuai:ed in figure
2&4& -he ony pro$e%s fa!ed hen !onerting the ogi! as !onfusion $eteen high and
o ogi! ees& #or nM' ogi! positie aues are high and 0 is o& #or pM'negatie aues are high and 0 is o&
Figure 2.#: Comparator Circuit with C$%& transistors
5
8/10/2019 Design and Fabrication of a 2-bit Comparator
6/23
Figure 2.': Comparator Circuit with p$%& transistors
nitiay the $asi! proided %ode for the pM' transistor as used dispayed in
e6uation 2& ith ; ratios of 2;20 for oad transistors and 20;2 for driers&
,
8/10/2019 Design and Fabrication of a 2-bit Comparator
7/23
&M'"E+ .M' .M' (+E0 to 0 ots& -he
signa as then o$sered on the C'C and " outputs& #igure 3& are the resuts fro% the
first "C anaysis transistors ith threshod otages of >3< and gate otages of >0< to a high of >,, C"'=3&7E>0 C'=3&7E>0 9=,, -'=0E>
/ ?'=23, ?E.=&25 ?C-=/&3E4 AMMA=&5 N#=3&23E M@=&41
M@*=&1,E>3 .B=&7)
7
8/10/2019 Design and Fabrication of a 2-bit Comparator
8/23
Equation #.1: )mpro"e* p$%& mo*e!
Figure #.2:)mpro"e* DC Ana!(sis
-he net step as to run a transient anaysis hi!h aos for a of the states of the
dei!e to $e o$sered& .uses of 40 and /0us ere used on the inputs to drie the states&
#igure 3&3 dispays the $ehaior of the syste% ith !hanging inputs&
Figure #.#: Transient Ana!(sis
By !o%paring the states to the ogi! diagra% it !an $e seen that the si%uated dei!e is
indeed fun!tioning as a !o%parator& Nota$e in figure 3&3 are pea8s and dips hi!h
/
8/10/2019 Design and Fabrication of a 2-bit Comparator
9/23
appear %id state& -hese are !aused $y !onditions hen $oth inputs !hange
si%utaneousy on the puse edge& -he fooing ist dispays the nodes of the si%uation* C:\Users\Kendra K\Documents\micro lab\8-16and40-8wl-goodsim.asc1 !"#dd 0 -1$% !"#&0 0 'U()+-1$ 0 40us 1us 1us 40us 80u, 0 0 'U()+-1$ 0 80u 1u 1u 80u 160u,
/1 !"#DD !"#DD 00 0 23et l16u w8u/$ !"#dd !"#dd 00% 0 23et l16u w8u/5 014 0 0 0 23et l8u w40u/1% !"#dd !"#dd !"#C0 0 23et l16u w8u/% 010 00 014 0 23et l8u w40u/ !"#dd !"#dd 010 0 23et l16u w8u/4 004 00 0 0 23et l8u w40u/6 00% !"#&0 004 0 23et l8u w40u/ 01% 0 0 0 23et l8u w40u/8 00 !"#&0 01% 0 23et l8u w40u/10 008 010 0 0 23et l8u w40u/11 !"#C0 00% 008 0 23et l8u w40u/%$ D !"#C0 0 0 23et l8u w40u/%6 D !"#C1 0 0 23et l8u w40u/% !"#dd !"#dd D 0 23et l16u w8u$ !"#&1 0 'U()+-1$ 0 %00us 1us 1us 40us 80u,6 1 0 'U()+-1$ 0 %80u 1u 1u 80u 160u,/1 !"#DD !"#DD 00$ 0 23et l16u w8u/14 !"#dd !"#dd 001 0 23et l16u w8u/1$ 01 1 0 0 23et l8u w40u/16 !"#dd !"#dd !"#C1 0 23et l16u w8u/1 005 00$ 01 0 23et l8u w40u/18 !"#dd !"#dd 005 0 23et l16u w8u/15 00 00$ 0 0 23et l8u w40u/%0 001 !"#&1 00 0 23et l8u w40u/%1 011 1 0 0 23et l8u w40u/%% 00$ !"#&1 011 0 23et l8u w40u
/% 006 005 0 0 23et l8u w40u/%4 !"#C1 001 006 0 23et l8u w40u.model /) /).model '/) '/).lib C:\'7"7&1\(9C\(9)'C1\lib\cm;\standard.mos./D( '/) '/) +((% (%0u 5< instead of &,0 the dei!e oud
not propery perfor% as dispayed in figure 4&&
1
8/10/2019 Design and Fabrication of a 2-bit Comparator
10/23
Figure '.1: )nsu++icient Gate ,o!tage at -, ,th
9ere it !an $e seen that the C' output is not $eing propery a!tiated ith the A0 input&
*hen the input otage and 5 ots the outputs are then properyinitiai:ed as seen in figure 4&2
Figure '.2:)ncrease* Gate ,o!tage at -, ,th
0
8/10/2019 Design and Fabrication of a 2-bit Comparator
11/23
9oeer een after in!reasing the gate otage the sing $eteen positie high and
o aues as not arge enough on the " output so the idth and ength ratios ere
in!reased to $etter !ontrast high and o& Co%paring the fina !ir!uit at >5< threshodotage (figure 4&3) to the transient at &,< threshod (figure 3&3) the high to o sing is
%u!h %ore signifi!ant&
Figure '.#: Fina! Transient with -1, Gate ,o!tage/ - Thresho!* ,o!tage
5.Circuit Layout
-he first step of !onfiguring the ayout as to dra a sti!8 diagra%& -he sti!8 diagra%
portrays the o!ation of the different ayers and their !onne!tions to one another& -he
sti!8 diagra% in figure 5& portrays %eta in $ue gate oide in red fied oide in greenand ia hoes ith $a!8 !ir!es&
8/10/2019 Design and Fabrication of a 2-bit Comparator
12/23
Figure .1: &tic Diagram
#ro% the sti!8 diagra% an appropriate ayer diagra% !oud $e !reated using Ce*inoftare& #igure 5&2 $eo shos the fina ayout design& A fe features needed to $e
atered fro% the sti!8 diagra% in order to fit a the !o%ponents in& 'ne nota$e !hange
is the re%oa of 4 !enter testing pads on the eft and right sides& e6uire%ents for the
ayout in!uded %ini%u% feature si:e of /% and %ini%u% ayer oerap of 4%&
Figure .2: Fina! La(out Design
6.Testing Procedure
After the dei!e has !o%peted fa$ri!ation %utipe tests %ust $e run to !onfir% its
fun!tionaity& -he first steps i $e to test the C0 output hi!h is the output of one
2
8/10/2019 Design and Fabrication of a 2-bit Comparator
13/23
' gate !o%ing fro% A' and B' inputs& By arying the input signas high and o
at aues si%iar to si%uation (high >0 o 0 5) the outputs shoud %i%i! those
in the si%uation& Net the sa%e shoud $e done ith C A and B& #inay the totaoutput " shoud $e tested arying the inputs A0 B0 A and B& -he aues shoud
foo the truth ta$e for the !o%parator& f the resuts do not %at!h $oth 's and the
N' gates !an $e tested indiiduay sin!e testing pads ere !onne!ted to input;outputines C and C0&
.Circuit !a"rication
-he !ir!uit as fa$ri!ated using %utipe ithography steps& -he pro!ess started ith a n>
type 0 !% 4 %i thi!8 (00) sii!on afer hi!h as oidi:ed in a stea%at%osphere at 00DC for 0 %in& -he fooing steps ere ta8en to fa$ri!ate the afer
Ta!e .1: Farication &teps
-he fooing i%ages here ta8en after fa$ri!ation had $een !o%peted&
Figure .1: Fina! $icrograph o+ Circuit
-his is the fina grand !ir!uit fuy designed and fa$ri!ated& -he fa$ri!ation
pro!ess did hae a fe $u%ps aong the ay $ut did not hae a signifi!ant effe!t on the
3
8/10/2019 Design and Fabrication of a 2-bit Comparator
14/23
end resut& o%e issues o$sered during fa$ri!ation in!uded the $u$$es for%ed during
the gate oide step of the pro!ess& Aso the gate oide et!h %ay hae oer et!hed and
redu!ed idth of the gate hi!h !oud resut in different otage output& #urther%ore
Aign%ents ere not perfe!t hi!h !oud ead to so%e non fun!tiona !ir!uits due to
aign%ent rotation& 9oeer it did see% that there ere a signifi!ant a%ount of propery
aigned !ir!uits hi!h are suita$e for testing&
Figure .2: Circuit throughout +arication +rom top !e+t c!ocwise3 Fie!* o4i*e/ Gate %4i*e/
,ia ho!es/ A!uminum.
#.$e%ice Testing
-esting as perfor%ed on the arious dei!es and stru!tures on the afer& -he
fooing data as o$tained through these tests in order to !o%pare 6uaity and
fun!tionaity ith other afers fa$ri!ated in the !ass&
/&a .roide the data %easured on the trans%ission ine stru!ture $y potting the%easured resistan!e %utipied ith the idth (20 %i!ron) as a fun!tion of the
!onta!t spa!ing (0 20 40 and /0) %i!ron& Etra!t the sheet resistan!eRs (= the
sope) and the !onta!t resistan!eRc (haf the >ais inter!ept in units of 'h%>
!%)& Ca!uate the !onta!t resistiity c fro% csc RR =
4
8/10/2019 Design and Fabrication of a 2-bit Comparator
15/23
Figure 5.1: Transmission Line 6esistance
/&$ *hat is the thi!8ness of the gate FdiffusionF and fied oide as %easured ith the
eipso%eterG *hat are the thi!8nesses of the gate oide and FdiffusionF oide aso$tained fro% the C>V%easure%entsG *hat aues are the %ost a!!urate and hyG
Figure 5.2: Capacitance
'ide -hi!8ness
5
8/10/2019 Design and Fabrication of a 2-bit Comparator
16/23
Measure%ents using interfero%etry and eipso%etry ere not used&
7&! *hat is the doping !on!entration the threshod otage and the fat$and otage aso$tained fro% the C>V%easure%entG Carefuy s!rutini:e the %ini%u% !apa!itan!e
the C>Vsyste% used to !a!uate the doping !on!entration and adHust the aue if
ne!essary& As additiona infor%ation 8eep in %ind that the sheet resistan!e (as
%easured ith the M>gage) of the starting afers as 00 > 200 'h% per s6uare&-he afers are 4 %is thi!8& *hat doping !on!entration oud you epe!t fro%
this M>gage %easure%entG
#at Band
8/10/2019 Design and Fabrication of a 2-bit Comparator
17/23
-heoreti!a #at Band otage and Capa!itan!e
/&d +ist the %easured aues of the output !ondu!tan!e the threshod otage and the
sope on the ersus VG!ure of the arger drier transistor& Ca!uate the surfa!e
%o$iity $ased on your %easure%ents& *hat aue did you use for the W/Lratio of
the transistorG 9o does your !a!uated aue !o%pare to the $u8 %o$iityepe!ted fro% the su$strate doping !on!entrationG Ca!uate the trans!ondu!tan!e
for the gate and drain otage at hi!h the output !ondu!tan!e as %easured (ta8e
the drain otage to $e hafay $eteen the to aues used to dra the straightine)& Ca!uate the ratio $eteen the trans!ondu!tan!e and output !ondu!tan!e at
that $ias point&
Figure 5.#: %utput Con*uctance
'utput Condu!tan!eI
-hreshod
8/10/2019 Design and Fabrication of a 2-bit Comparator
18/23
8/10/2019 Design and Fabrication of a 2-bit Comparator
19/23
Figure 5.
-he data etra!ted fro% the dei!es is su%%ari:ed in the ta$e $eoI
7arameter e4pecte* actua! ,a!ue otaine*
+rom
-hreshod otage >5 < >7 < -ransfer !ure
9oe %o$iity 00 !%2;s 1, !%2;s Ca!uated fro%K
and Coxate !apa!itan!e 37n# /&5n# C>< %easure%ent
"oping density 2 05!%>3 &43 05!%>3 C>< %easure%ent
Ta!e 5.1: Capture* De"ice 7arameters.
&.Circuit Testing
Cir!uit testing $egan ith itte resuts $ut this as pro$a$y !aused $y poor!onne!tions or a testing on a $ad !ir!uit& -he first test in!uded %easuring the !urrentea8age fro% poer to ground& -here did not see% to $e signifi!ant ea8age so testing
!ontinued on !hosen !ir!uit& Net the output as %easured hie arying the to inputs&
.oer as set to >302020
8/10/2019 Design and Fabrication of a 2-bit Comparator
20/23
Figure 8.1: First %utput $easurement
A se!ond dei!e as then tested for repeata$iity&
Figure 8.2: &econ* %utput $easurement
#ro% these to graphs it is apparent that the $ehaior is fun!tiona and so%ehatrepeata$e& n the first the otage starts to go high at around >0< input and has a haf
%ai%u% at >2
8/10/2019 Design and Fabrication of a 2-bit Comparator
21/23
otage starts to turn on& "ei!e 2 shos si%iar resuts $ut ith a higher turn on otage
at around >5305< and not >77
8/10/2019 Design and Fabrication of a 2-bit Comparator
22/23
-his resuted in to sy%%etri! $it !o%parators that ere testa$e $ut not the fina
output of the !o%$ined 2 $it !o%parator&
1'.Possi"le impro%ements
-he !ir!uit !oud hae $een i%proed ith further error proofing of the origina design&
#urther%ore so%e of the *;+ ratios !oud hae $een !hanged to in!rease poerpropagation through out the !ir!uit& f %ore spa!e ere aaia$e idea *;+ ratios oud
$e /;,4& #igure 7& $eo shos responses ith puses of 4s instead of the preiousy
used 40s& *hen idth to ength ratio is de!reased for oads to /;,4 fro% /;, figure
7&2 shos $etter response ti%e&
Figure .1: 51; wi*th to !ength ratio response to '
s pu!se
Figure .2: 5;'
8/10/2019 Design and Fabrication of a 2-bit Comparator
23/23
#urther%ore during testing it oud hae $een usefu to hae %ore pads
!onne!ted to !ertain outputs su!h as spe!ifi! NAN" gates ithin the !ir!uit to test for
indiidua fun!tionaity&
11.Conclusion
-he design and fa$ri!ation of the !o%parator as in genera a su!!ess& -hereere a fe 8in8s aong the ay $ut the pro!ess proed to $e reia$e and si%uated
fun!tionaity as o$tained during testing& -he 2>$it !o%parator had to $e redu!ed to a >
$it !o%parator due to design error $ut $oth $it !o%parators ere fun!tiona& -he poersuppy otage ne!essary as >30730< and a threshod of >,< shos ery si%iar resuts&
After fa$ri!ation there ere approi%atey 20 or8ing !ir!uits & 9af ere osthen the afer !ra!8ed and the rest ere isuay defe!tie due to s!rat!hes or $u$$es
!aused during et!hing& -he fina !oor as sier on the dei!e region and a
purpe;green around the edges depending on the ange the !hip as hed& My afer as!hosen for testing $e!ause fun!tionaity of the transistors and other dei!es ere
!onsistent&
12.!inal Conclusion
At first 27 transistors see%ed as i8e an inti%idating nu%$er $ut after the fa$ri!ation
yieded a or8ing dei!e J% ess s8epti!a& -he resuts see% to !o%e don to haing
enough pads in order to test different regions of the !ir!uit and arious outputs in !ase a%ista8e as %ade further don the ine& f the hoe !ass ere to or8 on a %ore
!o%pe !ir!uit it shoud hae su$ fun!tionaity ithin in it that !an easiy $e tested&
in!e an aerage of 30 transistors see%ed a !haenging enough tas8 to design ithout
fa it see%s that oud $e a good nu%$er to hae per student& 9oeer $uiding a%ore !o%pe !ir!uit oud re6uire so%ething to $e !hosen ahead of ti%e and so%e of
the !reatie !haenge oud $e ost to the indiidua& thin8 a reay in!redi$e part of
this !ass as the start to finish design and i%pe%entation of so%ething e ere a$e tode!ide upon oursees and ithin that !o%es the tas8 of deter%ining hat is doa$e
ithin the ti%e and resour!e i%its& A of those fa!tors ead to the !ourse $eing a hands
on earning adenture that reay enHoyed&
Top Related