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Lecture32
WhirlwindReviewofCS37
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CharlesBabbageandHisEnginesofComputing
BornDecember26,1791inTeignmouth,DevonshireUK.Died1871,London.Knowntosomeasthe"FatherofComputing"
forhiscontributionstothebasicdesignofthecomputerthroughhis
AnalyticalEngine.
TheDifferenceEngineI:25,000precisionmechanicalparts;neverquite
completed.
TheDifferenceEngineII:Improveddesign;notcompletedforlackof
funding.
TheAnalyticalEngine:Itwouldhavebeenprogrammable
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CharlesBabbageandHisEnginesofComputing
BornDecember26,1791inTeignmouth,DevonshireUK.Died1871,London.Knowntosomeasthe"FatherofComputing"
forhiscontributionstothebasicdesignofthecomputerthroughhis
AnalyticalEngine.
TheDifferenceEngineI:25,000precisionmechanicalparts;neverquite
completed.
TheDifferenceEngineII:Improveddesign;notcompletedforlackof
funding.
TheAnalyticalEngine:Itwouldhavebeenprogrammable
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AlanTuring,FounderofComputerScience
1912(23June):Birth,Paddington,London
1931-34:UndergraduateatKing'sCollege,CambridgeUniversity
1932-35:Studiesquantummechanics,probability,logic1936:TheTuringmachine:OnComputableNumbers... submitted
1936-38:AtPrincetonUniversity.Ph.D.Papersinlogic,algebra,numbertheory
1938-39:ReturntoCambridge.IntroducedtoGermanEnigmacipherproblem
1939-40DevisestheBombe,machineforEnigmadecryption1939-42:BreakingofU-boatEnigmacipher,savingbattleoftheAtlantic
1943-45:ChiefAnglo-Americanconsultant.Introducedtoelectronics1946:Computerdesign,leadingtheworld,formallyaccepted
1947-48:Papersonprogramming,neuralnets,andprospectsforartificialintelligence
1949:Workonprogrammingandworld'sfirstserioususeofacomputer
1950:Philosophicalpaperonmachineintelligence:theTuringTest1952:Arrestedandtriedasahomosexual,lossofsecurityclearance
1954(7June):Deathbycyanidepoisoning,Wilmslow,Cheshire.
Turing
Machine
data
program
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JohnvonNeumman,ComputerArchitect
Writesamemoin1944(laterturnedintoa
paperin1946),thatgivesbirthtothecomputerarchitecturethatweknowtoday.
OppenheimerandVonNeumann
(ontheright)
EDVAC
Thegeneral-purposecomputingmachinecontainingfourmainorgans:arithmetic,
memory,control,andconnectionwiththehumanoperator.
Washethefirstonetocomeupwiththisconcept?
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LayersofAbstraction
FunctionalComponents
LogicGates
DiscreteElectronicComponents
bitstrings
bits
electriccurrents
DiscreteSpintronic Components electronsspins
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TransistorLogic
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LogicGates
Agraphicalalphabettodescribelogicfunctions.
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SynthesisofLogicFunctions
2.Constructitstruthtable.
1111
1011
1101
0001
1110
0010
0100
0000
MCBA
1.Understandthefunctiondescription.(3-bitmajority).
3.Lookattheentriesthatproducea1ontheoutputandconstruct
minterms.
Ex.When(A=0,B=1,C=1), we
producea1resultwith: BCA
4.Adduptheminterms withan
OR:ABCCABCBABCAM +++=
ThisiscalledSumofProducts
(SOP)form,orsumofminterms.
Thisgives1ifany oftheinputcombos
thatproduce1ispresented.
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LogicReduction:Karnaugh Maps
1110
0100
ABC 00 01 11 10
0
1
1.Countthenumberofinputsandcreatethemap.
2.Transportdatafromthetruthtable
intothemap.
3.Lookforadjacent1sinrectangles
withnumbersofcellsthatarepowers
of2:1,2,4,8,etc.
4.Findthelargestgroupsthatcoverall
1satleastonce.
ABAB
CCABCABABC
=
=+=+
)1(
)(
ABACBCM ++=ABCCABCBABCAM +++=
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SequentialLogic
CombinationalLogic:Nomemory.
Circuitsgainthecapabilityofremembering
statesandofreactingdifferentlytodifferentinputs
atdifferenttimes.
Memory
CombinationalLogicClock
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IntegerNumberRepresentationsinBinary
8
76
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
Biased
B=7
-10-715111115
-2-1-614111014-3-2-513110113
-4-3-412110012
-5-4-311101111
-6-5-210101010
-7-6-1910019
-8-7-0810008
77+7701117
66+6601106
55+5501015
44+4401004
33+3300113
22+2200102
11+1100011
00+0000000
2s
complement
1s
complement
Signed
Magnitude
Unsigned
integer
BinaryDecimal
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OperationsonBinaryValues
b
0
2
Result
Operation
a
1
CarryIn
CarryOut
1-bitversion
Notehowitdoesall
threeoperationsin
parallel,whetherit
isrequiredornot.
ALU:ArithmeticLogicUnit
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ComplexArithmeticOperations
Definealgorithmsforthemultiplicationand
divisionofbinarynumbers.
Designhardwarecapableofcarryingout
theseoperations.
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FloatingPointNumberRepresentation
SE(exponent)M(mantissa)single=
SE(exponent)M(mantissa)double=
1bit 8bits 23bits
11bits 52bits
TheExponentisrepresentedinExcessB=127forsingleandB=1023fordoubleprecision.
1bit
ES
MX 2)1()1( +=
TheIEEE754Standard(1985)
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AssemblyProgramming
$0,
$t0..$t9,$s0,$s7,
$at,$k0,$k1,
$a0..$a3,$v0,$v1,
$ra,
$fp,$sp,
$gp
CPU
32FPregistersor
16FPregisters:
$f0,$f2,$f4,$f6,
(doubleprecision)
$f1,$f3,$f5,
(singleprecision)
FPU
BadVaddr,Status,
Cause,
EPC
coprocessor
systembus
TheMIPS2000Architecture
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TechniquesinAssemblyProgramming
high
low
$sp
Argument6
Argument5
SavedRegisters
$fp Procedurecallingconventions
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PiecingTogetheranExecutable
fromSeparatelyCompiledUnits
Object file
Instructions
Relocation
records
main:
jal ???
jal ???
call, sub
call, printf
Executable file
main:
jal printf
jal sub
printf:
sub:
Object file
sub:
C library
print:
Linker
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Performance
Howdowecountthenumberof
instructionsexecutedinaprogram?
IstheCPIindependentoftheprogramwe
use?HowdowefigureouttheCPI?
Identifythei differentclassesofinstructionsusedin
theprogramandcountCi ,thenumberof
instructionsfromeachclassintheprogram.Each
classgroupsinstructionswiththesameclockcount
CPIi (integerarithmetic,memoryaccess,etc).
=
=
n
i
ii CCPIcyclesclock1
)(
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ASingle-CycleDatapath
Shiftleft 2
PC
Instructionmemory
Readaddress
Instruction[310]
Datamemory
Readdata
Writedata
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Instruction [1511]
Instruction [2016]
Instruction [2521]
Add
ALUresult
Zero
Instruction [50]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
Branch
JumpRegDst
ALUSrc
Instruction [3126]
4
Mux
Instruction [250] Jump a ddress [310]
PC+4 [3128]
Signextend
16 32Instruction [150]
1
Mux
1
0
Mux
0
1
Mux
0
1
ALUcontrol
Control
AddALU
result
Mux
0
1 0
ALU
Shift
left 226 28
Address
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AMulticycle Datapath
Shiftleft 2
PC
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Instruction
Mux
0
1
Mux
0
1
4
Instruction
Signextend
3216
Instruction
Instruction
Instruction
Instructionregister
ALUcontrol
ALUresult
ALU
Zero
Memorydata
register
A
B
IorD
MemRead
MemWrite
MemtoReg
PCWriteCond
PCWrite
IRWrite
ALUOp
ALUSrcB
ALUSrcA
RegDst
PCSource
RegWrite
Control
Outputs
Op
Instruction[31-26]
! " #
Mux
0
2
Jumpaddress [31-0]
$ ! " #
$
26 28Shiftleft 2
PC [31-28]
1
1 Mux
0
3
2
Mux
0
1ALUOut
Memory
MemData
Writedata
Address
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Microprogram counter
Address select logic
Adder
1
Input
Datapath
control
outputs
Microcodestorage
Inputs from instruction
register opcode field
Outputs
Sequencing
control
SequencingPCWriteControl
MemoryRegisterControl
ALUSRC2
ALUSRC1
ALUControl
MicroinstructionFormat
WhatisdoneOperandsources RorW
SourceforW
RorWSourceforW
Whento
writeWhatcomes
next
ControlUnitDesign:
1) FSM2) Microprogramming
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PC
Instructionmemory
Instruction
Add
Instruction
MemtoReg
ALUOp
Branch
RegDst
ALUSrc
4
16 32Instruction
0
0
Mux
0
1
AddAdd
result
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Signextend
Mux
1
ALUresult
Zero
Writedata
Readdata
Mux
1
ALUcontrol
Shiftleft 2
RegWrite
MemRead
Control
ALU
Instruction
6
EX
M
WB
M
WB
WBIF/ID
PCSrc
ID/EX
EX/MEM
MEM/WB
Mux
0
1
MemWrite
Address
Datamemory
Address
Pipelining:IncreasingThroughput
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PC
Instructionmemory
4
Registers
Signextend
Mux
Mux
Mux
Control
ALU
EX
M
WB
M
WB
WB
ID/EX
EX/MEM
MEM/WB
M
ux
Datamemory
Mux
Hazarddetection
unit
Forwardingunit
IF.Flush
IF/ID
Mux
ExceptPC
40000040
0
Mux
0
Mux
0
Mux
ID.Flush EX.Flush
Cause
Shiftleft 2
Writedata
Readdata
Address
Readdata
Address Writeregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
ALUcontrol
3216
Instruction
RegWrite
ALUOp
ALUSrc
RegDst
MemWrite
MemRead
MemtoReg
Branch
=
HazardsandForwarding
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Weneedsometechniquethatallowsustogetthebestofamemory
systemwhilewepaylowcost(constructionandperformance).
CP U
Level n
Level 2
Level 1
Levels in th e
memory hierarchy
Increasing distan ce
from the CPU in
access time
Size of the m emory at each level
TheMemoryHierarchy
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Directmapped
Fully
Associative2-waySet
Associative
4-waySet
Associative
8-waySet
Associative
Spectrumofdesignoptionsforcachememory
missratedecreases
hittimeincreases
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Valid
1
1
1
1
0
11
0
1
1
0
1
Page table
Physical page
addressValid
TLB
1
1
1
1
0
1
Ta g
Virtual page
number
Physical page
or disk address
Physical memory
Disk storage
TLB
VirtualMemory
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Valid Tag Data
Page offset
Page offset
Virtual page number
Virtual address
Physical page numberValid
1220
20
16 14
Cache index
32
Cache
DataCache hit
2
Byteoffset
Dirty Ta g
TLB hit
Physical page number
Physical address t ag
TLB
Physical address
31 30 29 15 14 13 12 11 10 9 8 3 2 1 0
Virtualaddress
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Disk
Platter
Track
Platters
Sectors
Tracks
Eachplatterisamagnetic
surface.Foreachplatter,
theremustanassociatedread/writehead.
Aplatterisdividedinto
tracks andtracksaredivided
intosectors.
Tracksontheoutsideofa
plattermay havemore
sectorsthanthosefurther
inside.(Abandisagroupofadjacenttracksallwiththe
samenumberofsectors.)
Takingthesametrackacrossallsurfaces,youhavewhatiscalleda
cylinder.
Adiskisablock device.
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ConnectingCPU,I/OandMemory
Main
memory
I/O
controller
I/O
controller
I/O
controller
Disk Graphics
output
Network
Processor
Cache
Interrupts
Disk
Memory-I/OBUS
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ComputerNetworks
bus star
ring
mesh
hypercube
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ProcessingModels
SISD:
Singleinstructionstream
Singledatastream
MIMD:
Multipleinstructionstreams
Multipledatastreams
MISD:
Multipleinstructionstreams
Singledatastream
SIMD:
Singleinstructionstream
Multipledatastreams
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processor
cache
singlebus
processor
cache
processor
cache
Main
Memory
I/O
SharedMemoryMultiprocessors
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processor
cache
interconnectionnetwork
processor
cache
processor
cache
memory memory memory
DistributedMemoryArchitectures
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