1
COMP541
Datapath &Single-Cycle MIPS
Montek Singh
Oct 27, 2014
Topics Complete the datapath Add control to it Create a full single-cycle MIPS!
ReadingChapter 7Review MIPS assembly language
Chapter 6 of course textbookOr, Patterson Hennessy (inside front flap)
A MIPS CPU
3
MIPS CPUInstr
MemoryData
Memory
pc
instr
memwrite
dataadr
readdata
writedata
clk clkreset
Top-Level: MIPS CPU + memories
4
MIPS CPUInstr
MemoryData
Memory
pc
instr
memwrite
dataadr
readdata
writedata
clk clkreset
clkreset
We will add I/O devices (display, keyboard, etc.) later
Top-level module
Top-Level MIPS: Verilogmodule top(input clk, reset, output … ); // add signals here for debugging
// we will add I/O later
wire [31:0] pc, instr, readdata, writedata, dataadr; wire memwrite;
mips mips(clk, reset, pc, instr, memwrite, dataadr, writedata, readdata); // processor
imem imem(pc[31:0], instr);// instr memory// send full PC to imem
dmem dmem(clk, memwrite, dataadr, writedata, readdata); // data memory
endmodule
One level down: Inside MIPS Datapath: components that store or process data
registers, ALU, multiplexors, sign-extension, etc. we will regard memories as outside the CPU, so not part of the core
datapath
Control: components that tell datapath what to do and when control logic (FSMs or combinational look-up tables)
MIPS CPU
Control
ALUFN,regwrite,regdst…
opcode,func, flagZ …
MIPS Datapath
InstrMemory
DataMemory
pc
instr
memwrite
dataadr
readdata
writedata
clk
reset
clk
One level down: Inside MIPSmodule mips(input clk, reset, output [31:0] pc, input [31:0] instr, output memwrite, output [31:0] dataaddr, writedata, input [31:0] readdata);
wire memtoreg, branch, pcsrc, alusrc, regdst, regwrite, jump; wire [4:0] ALUFN; wire flagZ;
controller c(instr[31:26], instr[5:0], flagZ, memtoreg, memwrite, pcsrc, alusrc, regdst, regwrite, jump, ALUFN); datapath dp(clk, reset, memtoreg, pcsrc, alusrc, regdst, regwrite, jump, ALUFN, flagZ, pc, instr, dataddr, writedata, readdata);endmodule
NOTE: This is may need changes before you use it for your lab assignment
Review: MIPS instruction types
Three instruction formats:R-Type: register operands I-Type: immediate operand J-Type: for jumps
8
R-Type instructions Register-type
3 register operands:rs, rt: source registersrd: destination register
Other fields:op: the operation code or opcode (0 for R-type
instructions)funct: the function
– together, op and funct tell the computer which operation to perform
shamt: the shift amount for shift instructions, otherwise it is 0
op rs rt rd shamt funct6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-Type
R-Type Examples
add $s0, $s1, $s2
sub $t0, $t3, $t5
Assembly Code
0 17 18 16 0 32
Field Values
0 11 13 8 0 34
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
000000 10001 10010 10000 00000 100000
op rs rt rd shamt funct
000000 01011 01101 01000 00000 100010
Machine Code
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
(0x02328020)
(0x016D4022)
Note the order of registers in the assembly code:
add rd, rs, rt
I-Type instructions Immediate-type
3 operands:op: the opcoders, rt: register operands imm: 16-bit two’s complement immediate
op rs rt imm6 bits 5 bits 5 bits 16 bits
I-Type
I-Type Examples
Assembly Code
8 17 16 5
Field Valuesop rs rt imm
6 bits 5 bits 5 bits 16 bits
addi $s0, $s1, 5
addi $t0, $s3, -12
lw $t2, 32($0)
sw $s1, 4($t1)
8 19 8 -12
35 0 10 32
43 9 17 4
(0x22300005)
(0x2268FFF4)
(0x8C0A0020)
(0xAD310004)
001000 10001 10000 0000 0000 0000 0101
op rs rt imm
Machine Code
6 bits 5 bits 5 bits 16 bits
001000 10011 01000 1111 1111 1111 0100
100011 00000 01010 0000 0000 0010 0000
101011 01001 10001 0000 0000 0000 0100
Note the differing order of registers in the assembly and machine codes:
addi rt, rs, imm
lw rt, imm(rs)
sw rt, imm(rs)
J-Type instructions Jump-type
26-bit address operand (addr)Used for jump instructions (j)
op addr6 bits 26 bits
J-Type
Review: Instruction Formats
op rs rt rd shamt funct6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-Type
op rs rt imm6 bits 5 bits 5 bits 16 bits
I-Type
op addr6 bits 26 bits
J-Type
MIPS State Elements
15
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RD
DataMemory
WD
WEPCPC'
CLK
32 3232 32
32
32
32 32
32
32
5
5
5
We will fill out the datapath and control logic for basic single cycle MIPS• first the datapath• then the control logic
Single-Cycle Datapath: lw Let’s start by implementing lw instruction
How does lw work? STEP 1: Fetch instruction
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RD
DataMemory
WD
WEPCPC'
Instr
CLK
Single-Cycle Datapath: lw STEP 2: Read source operands from register
file
Instr
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RD
DataMemory
WD
WEPCPC'
25:21
CLK
Single-Cycle Datapath: lw STEP 3: Sign-extend the immediate
SignImm
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
CLK
NOTE: Sign Extension is done conditionally in our MIPS there are signed and unsigned instructions (e.g., ADD vs. XOR)
Single-Cycle Datapath: lw STEP 4: Compute the memory address
SignImm
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
SrcB
ALUResult
SrcA Zero
CLK
ALUControl2:0
ALU
010
Note ALUControl: ours will be different
Single-Cycle Datapath: lw STEP 5: Read data from memory and write it
back to register file
A1
A3
WD3
RD2
RD1WE3
A2
SignImm
CLK
A RD
InstructionMemory
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
SrcB20:16
ALUResult ReadData
SrcA
RegWrite
Zero
CLK
ALUControl2:0
ALU
0101
Single-Cycle Datapath: lw STEP 6: Determine the address of the next
instruction
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
SrcB20:16
ALUResult ReadData
SrcA
PCPlus4
Result
RegWrite
Zero
CLK
ALUControl2:0
ALU
0101
Let’s be Clear: CPU is Single-Cycle! Although the slides said “STEP” …
… all those operations are performed in one cycle!!!
Let’s look at sw next … … and then R-type instructions
Single-Cycle Datapath: sw Write data in rt to memory
nothing is written back into the register file
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
20:16
15:0
SrcB20:16
ALUResult ReadData
WriteData
SrcA
PCPlus4
Result
MemWriteRegWrite
Zero
CLK
ALUControl2:0
ALU
10100
Single-Cycle Datapath: R-type instr R-Type instructions:
Read from rs and rtWrite ALUResult to register fileWrite to rd (instead of rt)
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PCPC' Instr25:21
20:16
15:0
SrcB
20:16
15:11
ALUResult ReadData
WriteData
SrcA
PCPlus4WriteReg4:0
Result
RegDst MemWrite MemtoRegALUSrcRegWrite
Zero
CLK
ALUControl2:0
ALU
0varies1 001
Single-Cycle Datapath: beq Determine whether values in rs and rt are equal Calculate branch target address: BTA = (sign-extended immediate << 2) + (PC+4)
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1
PC' Instr25:21
20:16
15:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
RegDst Branch MemWrite MemtoRegALUSrcRegWrite
Zero
PCSrc
CLK
ALUControl2:0
ALU
01100 x0x 1
Complete Single-Cycle Processor (w/control)
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
26
Control Unit Generally as shown below
but some differences because our ALU is more sophisticated
RegDst
Branch
MemWrite
MemtoReg
ALUSrcOpcode5:0
ControlUnit
ALUControl2:0Funct5:0
MainDecoder
ALUOp1:0
ALUDecoder
RegWriteflagZ
PCSrc
Note: This will be 5 bits for our full-feature ALU!
Note: This will be different for our full-feature ALU!
Note: Zero flag is input to control, and PCSrc is generated here!
Review: Lightweight ALU from book
ALU
N N
N
3
A B
Y
F
F2:0 Function
000 A & B
001 A | B
010 A + B
011 not used
100 A & ~B
101 A | ~B
110 A - B
111 SLT
28
Review: Lightweight ALU from book
+
2 01
A B
Cout
Y
3
01
F2
F1:0
[N-1] S
NN
N
N
N NNN
N
2
Ze
roE
xtend
F2:0 Function
000 A & B
001 A | B
010 A + B
011 not used
100 A & ~B
101 A | ~B
110 A - B
111 SLT
29
Review: Our “full feature” ALU Our ALU from Lab 3 (with support for
comparisons)
Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B 1 X0 1 1 A LT B 1 X1 1 1 A LTU B X 00 1 0 B<<A X 10 1 0 B>>A X 11 1 0 B>>>A X 00 0 0 A & B X 01 0 0 A | B X 10 0 0 A ^ B X 11 0 0 A | B
5-bit ALUFN
A B
Result
BidirectionalShifter
BooleanAdd/SubSub
Bool
Shft
Math
1 0
1 0
ZFlag
FlagsN,V,C
Bool0
0 1
<?
30
Review: R-Type instructions Register-type
3 register operands:rs, rt: source registersrd: destination register
Other fields:op: the operation code or opcode (0 for R-type
instructions)funct: the function
– together, op and funct tell the computer which operation to perform
shamt: the shift amount for shift instructions, otherwise it is 0
op rs rt rd shamt funct6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-Type
Controller (2 modules)module controller(input [5:0] op, funct, input flagZ, output memtoreg, memwrite, output pcsrc, alusrc, output regdst, regwrite, output jump, output [2:0] alucontrol);
// 5 bit ALUFN for our ALU!!
wire [1:0] aluop; // This will be different for our ALU wire branch; // See NOTE on next slide
maindec md(op, memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop); aludec ad(funct, aluop, alucontrol);
assign pcsrc = branch & (op == beq ? flagZ : ~flagZ); // handle both beq and bneendmodule
RegDst
Branch
MemWrite
MemtoReg
ALUSrcOpcode5:0
ControlUnit
ALUControl2:0Funct5:0
MainDecoder
ALUOp1:0
ALUDecoder
RegWriteflagsZ
PCSrc
Note on Controller Implementation For Lab: we will merge the functionality of the
main decoder and ALU decoder into oneso, okay not to partition into two submodules
Main Decodermodule maindec(input [5:0] op, output memtoreg, memwrite, branch, alusrc, output regdst, regwrite, jump, output [1:0] aluop); // different for our ALU
reg [8:0] controls;
assign {regwrite, regdst, alusrc, branch, memwrite, memtoreg, jump, aluop} = controls;
always @(*) case(op) 6'b000000: controls <= 9'b110000010; //Rtype 6'b100011: controls <= 9'b101001000; //LW 6'b101011: controls <= 9'b001010000; //SW 6'b000100: controls <= 9'b000100001; //BEQ 6'b001000: controls <= 9'b101000000; //ADDI 6'b000010: controls <= 9'b000000100; //J default: controls <= 9'bxxxxxxxxx; //TIP: put controls for NOP here! endcaseendmodule
Why do this?
This entire coding may
be different in our design
ALU Decodermodule aludec(input [5:0] funct, input [1:0] aluop, output reg [2:0] alucontrol); // 5 bits for our ALU!!
always @(*) case(aluop) 2'b00: alucontrol <= 3'b010; // add 2'b01: alucontrol <= 3'b110; // sub default: case(funct) // RTYPE 6'b100000: alucontrol <= 3'b010; // ADD 6'b100010: alucontrol <= 3'b110; // SUB 6'b100100: alucontrol <= 3'b000; // AND 6'b100101: alucontrol <= 3'b001; // OR 6'b101010: alucontrol <= 3'b111; // SLT default: alucontrol <= 3'bxxx; // ??? endcase endcaseendmodule
This entire coding will be
different in our design
Control Unit: ALU Decoder
ALUOp1:0 Meaning
00 Add
01 Subtract
10 Look at Funct
11 Not Used ALUOp1:0 Funct ALUControl2:000 X 010 (Add)
X1 X 110 (Subtract)
1X 100000 (add) 010 (Add)
1X 100010 (sub) 110 (Subtract)
1X 100100 (and) 000 (And)
1X 100101 (or) 001 (Or)
1X 101010 (slt) 111 (SLT)
This entire coding will be
different in our design
36
Control Unit: Main DecoderInstruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0
R-type 000000 1 1 0 0 0 0 …lw 100011 1 0 1 0 0 1 …sw 101011 0 X 1 0 1 X …beq 000100 0 X 0 1 0 X …
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
37
Note on controller The actual number and names of control
signals may be somewhat different in our/your designcompared to the one given in the bookbecause we are implementing more
features/instructions
SO BE VERY CAREFUL WHEN YOU DESIGN YOUR CPU!
Single-Cycle Datapath Example: or
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
0010
01
0
0
1
0
39
Extended Functionality: addi No change to datapath
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
Control Unit: addiInstruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0
R-type 000000 1 1 0 0 0 0 …lw 100011 1 0 1 0 0 1 …sw 101011 0 X 1 0 1 X …beq 000100 0 X 0 1 0 X …addi 001000 1 0 1 0 0 0 …
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
41
Adding Jumps: j
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC'
Instr25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
0
1
25:0 <<2
27:0 31:28
PCJump
Jump
42
Control Unit: Main DecoderInstruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0 Jump
R-type 000000 1 1 0 0 0 0 …lw 100011 1 0 1 0 0 1 …sw 101011 0 X 1 0 1 X …beq 000100 0 X 0 1 0 X …
j 000100 0 X X X 0 X XX 1
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC'
Instr25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
0
1
25:0 <<2
27:0 31:28
PCJump
Jump
43
Summary We learned about a complete MIPS CPU NOTE: Many details are different…
… from what you will implement in the labour lab MIPS has more featuresevery single line of Verilog you take from these slides
must be carefully vetted!
Next class:We will look at performance of single-cycle MIPSWe will look at multi-cycle MIPS to improve
performance
Next lab: Implement single-cycle CPU!
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