CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING
LECTURE 24, FALL 2012
TOPICS TODAY
• Finite State Machines
• Example: Mod-4 Counter
• Example: Vending Machine
FINITE STATE MACHINES
EXAMPLE: MOD 4 COUNTER
Appendix A: Digital LogicA-59
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Example: Modulo-4 Counter• Counter has a clock input (CLK) and a RESET input.• Counter has two output lines, which take on values of 00, 01, 10,
and 11 on subsequent clock cycles.
3-bit Synchronous
Counter
0 0 0 0 1 0 1 1 0 0RESET q0
4 3 2 1 04 3 2 1 0 Time (t)Time (t)
0 1 0 1 0
D
Q
Q
CLK
s0
s1
D
Q
Q
q1
s0
s1
Appendix A: Digital LogicA-60
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
StateTransition
Diagram forMod-4
Counter
A B1/00
0/01
1/00
Output 00state
Output 01state
RESET
q1
C D
Output 10state
Output 11state
q0
0/101/00
0/00
0/11
1/00
Appendix A: Digital LogicA-61
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
State Table for Mod-4 Counter
Present state
Input RESET0 1
A B/01 A/00B C/10 A/00
Next state Output
C D/11 A/00D A/00 A/00
Appendix A: Digital LogicA-62
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
State Assignment for Mod-4 Counter
Presentstate (St)
Input RESET0 1
A:00 01/01 00/00B:01 10/10 00/00C:10 11/11 00/00D:11 00/00 00/00
Appendix A: Digital LogicA-63
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Truth Table for Mod-4 Counter
00110011
01010101
s1(t) s0(t)
00001111
RESET r(t)
0110110000000000
s1s0(t+1)
0110110000000000
q1q0(t+1)
s1(t+1) = r(t)s1(t)s0(t) + r(t)s1(t)s0(t)
s0(t+1) = r(t)s1(t)s0(t) + r(t)s1(t)s0(t)
q1(t+1) = r(t)s1(t)s0(t) + r(t)s1(t)s0(t)
q0(t+1) = r(t)s1(t)s0(t) + r(t)s1(t)s0(t)
Mod 4 Counter Timing
Clock
Reset
s1
s0
q1
q0
Outputs 00 only when reset is high
UMBC, CMSC313, Richard Chang <[email protected]>
Mealy vs Moore Finite State Machines
• Mealy: output depends on input and state bits
CombinationalLogic
FlipFlops
input output
• Moore: output depends only on state bits
CombinationalLogic
FlipFlops
input output
CombinationalLogic
UMBC, CMSC313, Richard Chang <[email protected]>
EXAMPLE: VENDING MACHINE
Appendix A: Digital LogicA-70
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Example: A Vending MachineController
• Example: Design a finite state machine for a vending machinecontroller that accepts nickels (5 cents each), dimes (10 centseach), and quarters (25 cents each). When the value of the moneyinserted equals or exceeds twenty cents, the machine vends theitem and returns change if any, and waits for next transaction.
• Implement with PLA and D flip-flops.
Appendix A: Digital LogicA-71
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Vending Machine State TransitionDiagram
A B D
C
0 ¢ 5 ¢ 15 ¢
10 ¢
N/000
Q/101
Q/110
N = NickelD = DimeQ = Quarter
N/100 D/110
Q/111
D/000
N/000
D/100Q/111
D/000 N/000
A dime is inserted
1/0 = Dispense/Do not dispense merchandise
1/0 = Return/Do not return a nickel in change
1/0 = Return/Do not return a dime in change
Appendix A: Digital LogicA-72
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Vending Machine State Table andState Assignment
N00 01
A B/000 C/000
P.S.
Input
BCD
C/000 D/000D/000 A/100A/100 A/110
(a)
D10
A/110A/101A/111B/111
Q N
00 01
A:00 01/000 10/000
P.S.
Input
10/000 11/00011/000 00/10000/100 00/110
(b)
D
10
00/11000/10100/11101/111
Q
B:01C:10D:11
s1s0
x1x0 x1x0 x1x0
z2z1z0s1s0 /
Appendix A: Digital LogicA-73
Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
PLA Vending Machine Controllers1 s0 x1 x0
s1 s0 z2 z1 z0
0
1
2
4
5
6
8
9
10
12
13
14
(c)
5 × 5 PLA
z1z0
x1x0
(a)
DQs0
DQs1
CLK
0000000011111111
0000111100001111
0011001100110011
0101010101010101
100d010d100d001d
001d001d011d111d
001d000d001d011d
000d001d001d001d
0123456789
101112131415
s1 s0 x1 x0
Present state C oin
010d110d100d000d
s1 s0 z2 z1 z0
N ext state
D ispenseR eturn nickel
Base 10 equivalent
(b)
R eturn dim e
z2
NEXT TIME
• Finite State Machine Simplification
• 2-bit CPU
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