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CS 230: Computer CS 230: Computer Organization and Organization and
Assembly LanguageAssembly Language
Aviral Shrivastava
04/11/231
Department of Computer Science and Engineering
School of Computing and InformaticsArizona State University
Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB
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AnnouncementsAnnouncements
04/11/232
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More AnnouncementsMore Announcements
04/11/233
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The Instruction Set The Instruction Set Architecture (ISA)Architecture (ISA)
04/11/234
instruction set architecture
software
hardware
ISA - The interface description separating the software and hardware.
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Below the Below the ProgramProgram
04/11/235
High-level language program (in C) swap (int v[], int k) . . .
Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31
Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000
C - Compiler
Assembler
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Higher-Level Higher-Level LanguagesLanguages
• Higher-level languages– Allow the programmer to think in a more natural language
• Customized for their intended use, e.g., – Fortran for scientific computation– Cobol for business programming– Lisp for symbol manipulation
– Improve programmer productivity and maintainability• more understandable code that is easier to debug and validate
– Independent of• Computer on which it applications are developed• Computer on which it applications will execute
• Enabler– Optimizing Compiler Technology
• Very little programming at the assembler level
04/11/236
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MIPS R3000 Instruction Set MIPS R3000 Instruction Set ArchitectureArchitecture
• Instruction Categories– Arithmetic – Load/Store– Jump and Branch– Floating Point
•coprocessor
– Memory Management– Special
04/11/237
R0 - R31
PCHI
LO
OP
OP
OP
rs rt rd sa funct
rs rt immediate
jump target
3 Instruction Formats: all 32 bits wide
Registers
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RISC Vs. CISCRISC Vs. CISC
• MIPS ISA is a RISC ISA• RISC – Reduced Instruction Set Computer• CISC – Complex Instruction Set Computer
• Many differences– Will learn over the lectures
• One main difference– In MIPS (a RISC architecture), all instructions are 32-bits– In IA32 (a CISC architecture), instructions can be of
variable widths
04/11/238
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MIPS ISA: Arithmetic MIPS ISA: Arithmetic InstructionsInstructions
• MIPS assembly language arithmetic statementadd $t0, $s1, $s2sub $t0, $s1, $s2
• Each arithmetic instruction performs only one operation
• Each arithmetic instruction specifies exactly three operands
destination source1 op source2
• All operands are contained in the Register File– $t0, $s1,$s2 are in Register File
• Operand order is fixed04/11/239
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Compiling More Complex Compiling More Complex StatementsStatements
• What is the assembler equivalent ofh = (b - c) + d
• Assume– Variable b is stored in register $s1– Variable c is stored in $s2– Variable d is stored in $s3 – Result is to be left in $s0
04/11/2310
sub $t0, $s1, $s2
add $s0, $t0, $s3
## $t0 = b - c
## $s0 = $t0 + d
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MIPS Register FileMIPS Register File
• All source operands of arithmetic instructions must be from the Register File
• All the destination operands of arithmetic instructions must be written into the Register File
• Register File– Holds thirty-two 32-bit registers– Two read ports and– One write port
• Registers are– Faster than main memory– Easier for a compiler to use
• e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack
– Can hold variables so that• code density improves (since register are named with fewer
bits than a memory location) • Register addresses are indicated by using $
04/11/2311
Register File
src1 addr
src2 addr
dst addr
write data
32 bits
src1data
src2data
32locations
325
32
5
5
32
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Register Naming Register Naming ConventionConvention
04/11/2312
16 $s0 callee saves
. . . (caller can clobber)
23 $s7
24 $t8 temporary (cont’d)
25 $t9
26 $k0 reserved for OS kernel
27 $k1
28 $gp pointer to global area
29 $sp stack pointer
30 $fp frame pointer
31 $ra return address (Hardware)
0 $zero constant 0 (Hardware)
1 $at reserved for assembler
2 $v0 expression evaluation &
3 $v1 function results
4 $a0 arguments
5 $a1
6 $a2
7 $a3
8 $t0 temporary: caller saves
. . . (callee can clobber)
15 $t7
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MIPS ALUMIPS ALU
• 32-bit ALU– 2 32-bit sources– 1 32-bit result
• Operations– Arithmetic
• ADD, SUB, ...
– Logical• AND, OR, NOR, XOR, …
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ALU
32-bit
32-bit
32-bit
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How does it How does it work?work?
sub $t0, $s1, $s2
04/11/2314
Register File
src1 reg no
src2 reg no
src1 data
src2 data
$t0 R8 $s1 R17 $s2 R18
R0R1
R8
25R17R18
17
18 1025
10
-
dst addr
write data
15
8
15
15
R31
25 10
• Arithmetic instructions can only change the contents of the Register File– In CISC processors, arithmetic instructions
are much more powerful – they can read and change the contents of the memory
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MIPS R3000 Instruction Set MIPS R3000 Instruction Set ArchitectureArchitecture
• Instruction Categories– Arithmetic – Load/Store– Jump and Branch– Floating Point
• coprocessor
– Memory Management– Special
04/11/2315
R0 - R31
PCHI
LO
OP
OP
OP
rs rt rd sa funct
rs rt immediate
jump target
3 Instruction Formats: all 32 bits wide
Registers
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MemoryMemory
• Arithmetic instructions operands must be registers– How do we get data into and out of memory?
• Remember, program and data reside in memory (Not in registers)
– What about programs with a lot of variables?
04/11/2316
Processor
Control
Datapath
Memory
Devices
Input
Output
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Accessing Accessing MemoryMemory
• MIPS has two basic data transfer instructions for accessing memorylw $t0, 4($s3) #load word from memory
sw $t0, 8($s3) #store word to memory
(assume $s3 holds 2410)
• The data transfer instruction must specify– Memory address
• where in memory to read from (load) or write to (store)
– Register destination (source) • where in the register file to write to (load) or read from (store)
• The memory address is formed by – summing the constant portion of the instruction and the
contents of the second register04/11/2317
28
32
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Memory OrganizationMemory Organization• How wide is the memory• What is each unit
• Each unit is a bit– 0, 1
• 8-bits = 1 byte– In MIPS memory is byte
addressable– 232 locations of 1 byte
• Software likes to operate on “words”– 1 word = 4 bytes = 32
bits– 230 locations of 1 word
04/11/2319
Memory
Memory
232 Locations
8-bit
32-bit
230 Locations
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MIPS Memory MIPS Memory AddressingAddressing
• The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) registerlw $t0, 4($s3) #what? is loaded into $t0
sw $t0, 8($s3) #$t0 is stored where?
04/11/2320
Memory
. . . 0 1 0 0Data Word Address
0
4
8
12
16
20
24
. . . 1 0 0 0
. . . 0 0 1 0
. . . 0 0 0 1
. . . 1 1 0 0
. . . 0 1 0 1
. . . 0 1 1 0$s3 holds 8
in location 16
. . . 0001
. . . 0001
. . . 0 0 0 1
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Compiling with Loads Compiling with Loads and Storesand Stores
• Assume– Variable b is stored in $s2 – Base address of array A is in $s3
• What is the MIPS assembly code forA[8] = A[2] - b
04/11/2321
$s3
$s3+4
$s3+8
$s3+12
. . .
A[2]
A[3]
. . .
A[1]
A[0]
lw $t0, 8($s3)
sub $t0, $t0, $s2
sw $t0, 32($s3)
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Compiling with a Variable Compiling with a Variable Array IndexArray Index
• Assume– A is an array of 50 elements– Base of A is in register $s4– Variables b, c, and i are in $s1, $s2, and $s3
• What is the MIPS assembly code for c = A[i] - b
04/11/2322
add $t1, $s3, $s3 #array index i is in $s3
add $t1, $t1, $t1 #temp reg $t1 holds 4*i
add $t1, $t1, $s4 #addr of A[i]
lw $t0, 0($t1)
sub $s2, $t0, $s1
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Assembly Generation: Arithmetic Assembly Generation: Arithmetic InstructionsInstructions
• Instructions, like registers and words of data, are also 32 bits long– Example: add $t0, $s1, $s2– registers have numbers $t0=$8, $s1=$17, $s2=$18
• Instruction Format:
04/11/2323
op rs rt rd shamt funct
000000 10001 10010 01000 00000 100000
What do the field names stand for?
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MIPS Instruction FieldsMIPS Instruction Fields
• op• rs• rt• rd• shamt• funct
04/11/2324
op rs rt rd shamt funct6 bits 5 bits 5 bits 5
bits5 bits
6 bits
= 32 bits
opcode indicating operation to be performed
address of the first register source operand
address of the second register source operand
the register destination address
shift amount (for shift instructions)
function code that selects the specific variant of the operation specified in the opcode field
R Format
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Assembly Generation: Load Assembly Generation: Load InstructionInstruction
• Consider the load-word and store-word instructions,– What would the regularity principle have us do?– New principle: Good design demands a compromise
• Introduce a new type of instruction format– I-type for data transfer instructions– previous format was R-type for register
• Example: lw $t0, 24($s2)
04/11/2325
op rs rt 16 bit number
100011 10010 01000 0000000000011000
35 18 8 24
I Format
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Assembly Generation: Store Assembly Generation: Store InstructionInstruction
sw $t0, 24($s2)
04/11/2326
op rs rt 16 bit number
43 18 8 24
101011 10010 01000 0000000000011000
• A 16-bit address means access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register $s2
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Assembling CodeAssembling Code
• Example: A[8] = A[2] – b
lw $t0, 8($s3) #load A[2] into $t0
sub $t0, $t0, $s2#subtract b from A[2]
sw $t0, 32($s3) #store result in A[8]
• Assemble the MIPS code for these three instructions
04/11/2327
35lw 19 8 8
43sw 19 8 32
0sub 8 18 8 0 34
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MIPS Data TypesMIPS Data Types
04/11/2328
Bit: 0, 1
Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word
Character: ASCII 7 bit code
Integers: Unsigned Integers Signed Integers - 2's complement
Floating Point
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Decimal, Hexadecimal, and Decimal, Hexadecimal, and BinaryBinary
04/11/2329
00 0 000001 1 000102 2 001003 3 001104 4 010005 5 010106 6 011007 7 011108 8 100009 9 100110 A 101011 B 101112 C 110013 D 110114 E 111015 F 1111
1010 1100 0011 (binary)= 0xAC3
10111 (binary)= 0001 0111 (binary)= 0x17
0x3F9= 11 1111 1001 (binary) MEMORIZE!
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Unsigned Binary Unsigned Binary RepresentationRepresentation
Hex Binary Decimal
0x00000000 0…0000 0
0x00000001 0…0001 1
0x00000002 0…0010 2
0x00000003 0…0011 3
0x00000004 0…0100 4
0x00000005 0…0101 5
0x00000006 0…0110 6
0x00000007 0…0111 7
0x00000008 0…1000 8
0x00000009 0…1001 9
…
0xFFFFFFFC 1…1100 232-4
0xFFFFFFFD 1…1101 232-3
0xFFFFFFFE 1…1110 232-2
0xFFFFFFFF 1…1111 232-1
04/11/2330
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Signed Binary Signed Binary Representation : Representation :
2’s C binary decimal
1000 -8
1001 -7
1010 -6
1011 -5
1100 -4
1101 -3
1110 -2
1111 -1
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
04/11/2331
23 - 1 =
-(23 - 1) =-23 =
1010
complement all the bits
1011
and add a 1
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Memory Address Memory Address LocationLocation
lw $t0, 24($s2)2410 + $s2 =
04/11/2332
Memory
data word address (hex)
0x000000000x000000040x000000080x0000000c
0xf f f f f f f f
$s2 0x12004094
0x00000002
Note that the offset can be positive or negative
. . . 1001 0100+ . . . 0001 1000 . . . 1010 1100 = 0x120040ac
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MIPS Instructions, so MIPS Instructions, so farfar
Category Instr Op Code Example Meaning
Arithmetic(R format)
add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s3
subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3
Datatransfer(I format)
load word 35 lw $s1, 100($s2) $s1 = Memory($s2+100)
store word 43 sw $s1, 100($s2) Memory($s2+100) = $s1
04/11/2333
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Review: MIPS R3000 Review: MIPS R3000 ISAISA
• Instruction Categories– Arithmetic – Load/Store– Jump and Branch– Floating Point
• coprocessor
– Memory Management– Special
04/11/2334
R0 - R31
PC
HI
LO
OP
OP
OP
rs rt rd sa funct
rs rt immediate
jump target
Registers
R Format
I Format
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
• 3 Instruction Formats: all 32 bits wide
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
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Review: MIPS Review: MIPS Organization so farOrganization so far
• Arithmetic instructions – to/from the register file• Load/store instructions - to/from memory
04/11/2335
32registers
($zero - $ra)read data
32
5
32
5
5src1 addr
src2 addr
dst addr
write data
32 bits
32
32
3232
32
ProcessorMemory
32 bits
230 words
read/write addr
write data
word address(binary)
0…00000…01000…10000…1100
1…1100
Register File
src1data
src2data
32
32
ALU
0 1 2 37654
byte address(big Endian)
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Review: Naming Convention for Review: Naming Convention for RegistersRegisters
04/11/2336
16 $s0 callee saves
. . . (caller can clobber)
23 $s7
24 $t8 temporary (cont’d)
25 $t9
26 $k0 reserved for OS kernel
27 $k1
28 $gp pointer to global area
29 $sp stack pointer
30 $fp frame pointer
31 $ra return address (Hardware)
0 $zero constant 0 (Hardware)
1 $at reserved for assembler
2 $v0 expression evaluation &
3 $v1 function results
4 $a0 arguments
5 $a1
6 $a2
7 $a3
8 $t0 temporary: caller saves
. . . (callee can clobber)
15 $t7
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MIPS Data MIPS Data TypesTypes
04/11/2337
Bit: 0, 1
Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word
Character: ASCII 7 bit code
Integers: Unsigned Integers Signed Integers - 2's complement
Floating Point
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Yoda says…Yoda says…
• Named must your fear be before banish it you can
04/11/2338
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