Choosing the Right Processor for your Application
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AgendaChoosing the right processor for your applicationHardware design flowSoftware design flowVarious design phasesRecap of product life cycle
Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.
Choosing the right Processor
Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.
Microprocessor, by-itself, completely useless – must have external peripherals toInteract with outside world
CPU
CONTROL
ADDRESS
DATA
BOOTROM
Used at startup
Instruction(program)
ROMTransducers
KeyboardScreenUARTParallelinterface
etc
DataRAM
Microprocessor Basic
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CPU
Micro controller
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CPU121416
Memory(Data) 8
Memory (Program)
CPUMemory
(Program&Data)
Von Neumann Harvard
Von Neumann VS Harvard
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Why do we need DSP Processor?
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CPLD Vs FPGA
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CPLDs have the advantage of virtually “instant-on” functionality
CPLDs can be lower cost than FPGAs, especially if a configuration source is required for the FPGA*
CPLDs typically use the same manufacturer tool suite as FPGA components*
CPLDs tend to have simpler architectures / structures and fewer I/O and registers than FPGAs*
In some applications CPLDs can have superior performance to FPGAs* (ex: timing and I/O levels)
CPLD Vs FPGA
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Logic blocks I/O blocksClock routingRouting matrix
CPLD Architecture
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I/O blocksClock routingRouting matrixMemoryMultipliers /DSP blocksProcessor core
Logic blocks
FPGA Architecture
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FPGA Technologies
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No need for logic optimization using Karnaugh map.
Design is portable from one vendor application to the another.
Technology Independent.
Design cycle time reduces dramatically.
Provides concise representation of the design in contrast to logic diagrams
Why HDL?
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VHDLAda-like –Highly structuredNo case sensitivityEncapsulation –Architecture –Entity
Verilog Vs VHDL
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DSP Vs FPGA
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Higher PerformanceParallel algorithm implementation
Customizable DesignOptimize for speed and cost
System IntegrationLess board real estateLess chips could mean less system cost
When to use DSP in FPGA
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Power SupplyCLKCLK
CLKcustomIF-logic
SDRAM SDRAMSRAM SRAMSRAM
Memory Controller
UART LC
DisplayController
InterruptController Timer
AudioCodec
CPU(uP / DSP) Co-
Proc.
GP I/O
AddressDecode
Unit
EthernetMAC
Traditional embedded system design using DSP
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Next Step...Next Step...
FPGACLKCLK
CLKcustomIF-logic
SDRAM SDRAMSRAM SRAMSRAM
Memory Controller
UART
DisplayController
Timer
Power Supply
LC
AudioCodec
CPU(uP / DSP) Co-
Proc.
GP I/O
AddressDecode
Unit
EthernetMAC
InterruptController
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Power Supply
SDRAM SDRAMSRAM SRAMSRAM
LC
AudioCodec EPROM
Configurable system on Chip-CSoC
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2 or More Independent Processors in 1 Package
Symmetric Multiprocessing Number of Identical Processors Common Shared Memory One Operating System
Asymmetric Multiprocessing Different Processors, Instruction Sets Different Operating Systems Possibly Without Shared Memory
Multicore Processor
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•Identical Cores•Identical access to all System Resources•Memory, Disk, UARTs, Communication Controllers,•Examples: Analog Devices Blackfin 561
SMP-BF561
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Processors Need Not be IdenticalProcessor Specialization May Increase Performance.T.I.’s OMAP•General Purpose Processor+Digital Signal Processor(“DSP”)
AMP-TI OMAP
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AgendaProcessor selection CriteriaChoosing the right processor for your applicationHardware design flowSoftware design flowVarious design phasesRecap of product life cycle
Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.
QFP
SOLDERINGIRON
SOLDERING
STATION
OVEN
Selection of packages
DIP SOIC
BGAPLCC
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Hardware Design Flow
SCHEMATIC DESIGN LAYOUT DESIGN
ASSEMBLY & TESTING
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AgendaChoosing the right processor for your applicationHardware design flowSoftware design flowVarious design phasesRecap of product life cycle
Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.
Software Design Flow
Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.
GenerateNetlist
ISE
Platform Ext.Proj.Nav. / VHDL
*.mhs
*.elf
*.c *.asm
Compile &Link
UpdateBitstream
*.bit
*.h
Gen.Libs
Platform Definition(peripherals, configuration, connectivity, address space)
EDK: Embedded Development Kit XPS: Xilinx Platform Studio ISE: Integrated Software Environment MHS: Microprocessor Hardware Specification
*.bit
XPS
GenerateBitstream
*.ucf
Hardware Software
*.bmm
Software Design Flow -FPGA
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Data2MEM
Download Combined Image to FPGA
Compiled ELF Compiled BIT
RTOS, Board Support Package
EmbeddedDevelopment Kit
Integrated HW/SW/FPGA Flows
Instantiate the ‘System Netlist’ and Implement
the FPGA
?
HDL Entry
Simulation/Synthesis
Implementation
Download BitstreamInto FPGA
Chipscope
Standard FPGAHW Development Flow
VHDL or Verilog
System NetlistInclude the BSPand Compile theSoftware Image
?
Code Entry
C/C++ Cross Compiler
Linker
Load SoftwareInto FLASH
Debugger
Standard EmbeddedSW Development Flow
C Code
Board SupportPackage
12 3 Compiled BITCompiled ELF
Xilinx Platform Studio SDK
Xilinx Platform Studio
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FPGA Design Flow
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Design Compilation Simulation Verification
Graphical Entry
HDL Entry
Compiler
Timing Diagram
Timing Analysis
Program CPLD
Development Board
FPGA Design Flow
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Unified Tool Releases, All Tools Available for Evaluations
Verilog VHDL C/C++ MATLAB Simulink 3rd Party
Unified Design Environment The Ultimate System Integration Design Tools
New !New !
HW D
esign
ers
SW D
evelo
pers
Archite
cts
Verific
ation
Team Syst
em
Integ
rator
s. . . .
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Programmable
technologyGate countNumber of
I/O’S
Manufacturer
Family
Device
Power Consumption
Speed,voltage
Packaging
Design Decision in Choosing an FPGA
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Processor selection Criteria
Development tools Performance Cost Operating systems Hardware tools Peripherals Power consumption Supplier reputation
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SW DEVELOPMENT
HW DEVELOPMENT
SW SELECTION
HW SELECTION
INTEGRATION TESTING & TUNING DEPLOYMENT
Compiler RTOSs
Networking Protocols Java
SupportGraphics Support Project
& Code Mgmt.
RTOS
Simulation
Rapid Prototyping
Real-time Data
Visualization
Memory Leak
Detection CPUProfiling
Post-mortem Debug
Semiconductor Co-funded
Development Hardware Coverage
Board Bring-Up
Board Diagnostics & Manufacturing
Test
Source-level
Debugging
Real-time System
Analysis & Triggering
Execution Tracing Code
Coverage Analysis
In-field Debugging
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Embedded Development using FPGA
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AgendaChoosing the right processor for your applicationHardware design flowSoftware design flowVarious design phasesRecap of product life cycle
Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.
Simulation Evaluation
Emulation
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AgendaChoosing the right processor for your applicationHardware design flowSoftware design flowVarious design phasesRecap of product life cycle
Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.
Recap of Designing an Embedded System
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http://nptel.iitm.ac.in/videocourselist.phphttp://youtube.com/iit
Website and Resources
Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt Ltd.
http://www.esacademy.com/8051
(Philips Flash ISP software)
http://www.keil.com/demo/ Evaluation version for 8051 and ARM
http://www.microchip.comPIC
FPGAhttp://www.xilinx.com/support/download/index.htm
https://www.altera.com/support/software/download/sof-download_center.html
http://www.analog.com/en/embedded-processing-dsp/content/blackfin_bold_training/fca.html
DSP
www.ti.com/
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Questions ?
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