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Analog input subsystem
inputtransducer
signalconditioning
sample& hold
analog todigital conv.
Property being
measured
Digital valueto CPU
convert property toelectrical voltage/current
produce convenient voltage/currentlevels over range of interest
hold value during conversion
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Analog output subsystem
digital toanalog conv
signalconditioning
outputtransducer/
actuator
Property beingcontrolled
Digital valuefrom CPU
convert binary code to ananalog voltage/current
produce convenient voltage/currentlevels over range of interest
convert electrical signal to
mechanical or other property
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Multichannel analog input subsystem
inputtransducer
signalconditioning
sample& hold
Analog toDigital Conv.
Property1
Digital value
mux
inputtransducer
signalconditioning
Property2
inputtransducer
signalconditioning
PropertyN
Selectchannel
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Analog subsystem properties
Accuracy: degree to which measured value differsfrom true value
Resolution/precision: degree to which two conditionscan be distinguished
Related to #bits in digital value Range: minimum to maximum useful value
Linearity: y = Ax + B (correction reqd if not linear) piecewise linear approximation over different ranges
Repeatability: same measurement for a given value affected by hysteresis or other phenomena
Stability: value changes other than due to theproperty being measured (eg. T affecting P)
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Analog to digital conversion errors
May need to correct in software
Offset error
Gain error
Nonlinearity error -Unequal distancesbetween transition points
Quantization error:Difference between digital
& analog valuesUsually want LSB
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Transducers
Convert physical quantity to electrical signal Self-generating generates voltage/current signal
Non-self-generating other property change (ex. R)
Examples:
Force/stress (strain gage) Temperature (thermocouple, thermistor, semicond.) Pressure Humidity (gypsum block) Smoke Light (phototransistor, photoconductive cell) Acceleration (accelerometer) Flow Position (potentiometer, displacement)
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Temperature sensors
Thermocouple Seeback EMF produced byheating junction of dissimilar metals (V)
Thermistor mix of materials in ceramic
Metal conductor:
)](1[ 00 TTRRt +=
+ V -
[ ]ToTt eRR
/1/1
0
=
Negative temperature coefficient: R^ with TvLinear over small range
Positive temp. coefficient: R^ with T^
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-+
Vcc
VBE
VBE
VBE
Semiconductor temperature sensor
=IsIc
qkTVBE ln
Base-emitter voltage approximately proportional to T
TVBE
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Analog Devices AD590 Temperature
Transducer
IC generates current proportional totemperature
Generated current IT is linear: 1 a/oK
Example:
Design a temperature monitor withoutput in the range [0v..4v] overtemperature range [-20oC .. +60oC]
(Use summing amplifier)
IT
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Strain Gage
Measure stress by measuring change orresistance of a conductor due to change of itslength/area
Compression: L decreases, A increases
Elongation: L increases, A decreases
Gage factor (sensitivity):
A
L
=AoLoR
LL
RRS
/
/
=
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Wheatsone bridge
Measure small resistance changes
+
=
+
+=
RsR
RsV
RsR
RsV
RR
RVVo
ref
refref
2
1
Some pressure sensors use bridge with all 4 Rs variable
Balanced: Vo = 0 when R=Rs
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Signal conditioning
Produce noise-free signal over workinginput range
Amplify voltage/current levels
Bias (move levels to desired range)
Filter to remove noise
Isolation/protection (optical/transformer)
Common mode rejection for differential signals Convert current source to voltage
Conditioning often done with op amp circuits
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Operational amplifiers
Amplifier types:
Inverting amplifier
Non-inverting amplifier
Summing amplifier Differential amplifier
Instrumentation amplifier
Tradeoffs
Inverting/noninverting High input impedance
Defined gain
Comon mode rejection
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Basic op amp configurations
2
21/
21
2
R
RRViVo
RR
RVoVi
+=
+=
Inverting amplifier Noninverting amplifier
Noninverting version has high input impedance
1
221
R
R
Vi
Vo R
Vo
R
Vi
=
=
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Differential amplifier
21
1201
211
RR
VRVRVx
RVoVx
RVxV
+
+=
=
21
22
212
RR
RVVx
RVx
RVxV
+=
=
)12(1
2VV
R
RVo =
Choose R1 to set input impedance; R2 to set gain
Eliminates common modevoltage (noise, etc.)
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Instrumentation amplifier
+=
34
1221)12(
RR
RRVVVo
High input impedance, common mode rejectionCan match R2, R3, R4 on chip and use external R1 to set gain
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Sample-and-hold
Required if A/D conversion slow relative tofrequency of signal: Close switch to sample Vin (charge C to Vin)
Aperture (sampling) time = duration of switch closure
Open switch to hold Vin
converterVin
C
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Analog to digital conversion
Given: continuous-time electrical signal
v(t), t >=0
Desired: sequence of discrete numeric values thatrepresent the signal at selected sampling times :
v(0), v(T), v(2T),v(nT)
T = sampling time: v(t) sampled every T seconds
n = sample number
v(nT) = value of v(t) measured at the nth sample time andquantized to one of 2k discrete levels
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A/D conversion process
v(t)
t T 2T 3T 4T 5T 6T 7T
1 2 3 4 5 6 7
v(t*)
t*
k
v(kT)
Input signal Sampled signal
(3/4)Vref
Sampled & quantized
Sampled data sequence:
10, 10, 10, 10, 11, 11, 11
Binary values of n, whereV(kT) = (n/4)Vref
(2/4)Vref
(1/4)Vref
(0/4)Vref
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A/D conversion parameters
Sampling rate, F (sampling interval T = 1/F) Nyquist rate 2 x (highest frequency in the signal) to
reproduce sampled signals Examples:
CD-quality music sampled at 44.1KHz
(ear can hear up to about 20-22KHz) Voice in digital telephone sampled at 8KHz
Precision (# bits in sample value) k = # of bits used to represent samples precision: each step represents (1/2k)*Vrange accuracy: degree to which converter discerns proper level
(error when rounding to nearest level)
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Digital to analog conversion
R-2R Ladder Network
=
=
N
k
kkbVrVout
1 2
1
(Reference)
Equivalentresistance = R I/2n+1
Equivalentresistance = R
Current tovoltage
number = bn*2n + bn-1*2
n-1 + . + b1*21 + b0*2
0
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Digital to analog conversion
bits of digital word
referencevoltage
Vr/2Vr/4Vr/8Vr/2n-1Vr/2n
contribution toVout when switchconnected to Vr
Bit k => Vr/2k
=
=
N
kkk
bVrVout
1 2
1
Source: http://www.irctt.com/pdf_files/LADDERNETWORKS.pdf
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DAC 0831 8-bit D/A converter
Input latches can be made transparent
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Flash A/D conversion
N-bit result requires 2n comparators and resistors:
encoder
Vin
...
Vref
n-bitoutput
Identify bit at whichcomparator outputschange from 1->0.
Comparator output = 1 if Vin > Vref*(N/2n)(N = 1, 2, . 2n-1)
= R
RVrefV n
n
2
)12(
*Comparators
Thermometer code bottom k bits = 1, upper 2n-1-k bits = 0
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Dual-slope conversion Use counter to measure time required to
charge/discharge capacitor (relatively low speed).
Charging, then discharging eliminates non-linearities(high accuracy).
Relatively low cost
Vin
control
counter
-Vref
clock
n-bit output
-
+
comparator
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1. SW1 connects Vin for fixed time T
C charges with current = Vin(t)/R
Dual-slope conversion steps
Vin
RC
TdttVin
RC
dtti
C
tVo
TT
c === 00
)(1
)(1
)(
-Vo(t)
Constant slopeSlope Vin
T t1
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2. SW1 connects Vref until Vo discharges to 0.
C discharges with constant current = -Vref/R
When Vo(T+t1) = 0:
Dual-slope conversion steps
+
+=+1
1)(
1)(
0
1
tT
T
ref
T
dtVRC
dttVinRC
tTVo
-Vo(t)
Constant slopeSlope Vin
T t1
VrefT
tVin
dtVRC
dttVinRC
tT
T
ref
T
=
= +
1
0
1
1)(1
Use a counterto measure t1.
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Successive approximation A/D converter
Vin
SuccessiveApproximationRegister (SAR)
D/A Converter(R/2R ladder)
clock
Digital
Output
7654
3210
+ -Comparator
Vout
1. Clear all bits of SAR
2. Set SAR bit 7 = 13. If Vout < Vin, keep 1
If Vout > Vin, reset to 04. Repeat steps 2-3 for
bits 6-0.
5. SAR bits 7-0 = convertedvalue
Vref
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National Semiconductor ADC0804
Analog-to-Digital Converter
Successive approximation A/D converter
8-bit data: precision = (1/256)Vrange
Accuracy: 1 LSB Conversion time: 100s
Input voltage range: 0 to 5v
Built-in reference (Vcc/2) Can also use external reference: Vref/2
Microprocessor bus compatible
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Input
Address
IOR*
IOW*
Address
Reference(if used)
ClockComponents
Data bus
SARD/A
Dataready
ADC0804 functional diagramSource: National Semiconductor Data Sheet
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ADC0804 pin diagramDB7-0: data bus interface
CS*: chip select (address)RD*: read enable (IOR*)
- CS* & RD* active puts data onDB7-0.
- Otherwise, DB7-0 tri-stated
WR*: write enable (IOW*)- CS* & WR* active triggers newconversion
INTR*: interrupt- Set to 1 at start of conversion- Set to 0 when conversion finished- Set to 1 when data rea
VIN(+),VIN(-) analog input voltageCLK IN, CLK R clock componentsVref/2 reference voltage (1/2 Vcc if open)
Source: National SemiconductorData Sheet
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HCS12 analog-to-digital converter
PORTAD pins
(Cady, Figure 17-2)
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Freescale MAC7100
Successive-Approximation ADC
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LPC 22xx Analog to Digital Converter
10-bit successive approximation A/D converter 2.44s conversion for 10 bits (410 Ksamples/sec)
Programmable precision: 3 to 10 bits
Conversion time = #bits + 1 clock cycles 0 to 3 volt measurement range
Ref. voltage pins: V3A (3v), VSSA (gnd)
Analog multiplexer for inputs Ain0-Ain7 4-input (LPC21xx or LPC22xx in 64-pin pkg)
8-input (LPC22xx in >64-pin pkg)
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LPC 22xx A/D control register (ADCR)
Edge Start Test PDN CLKS Burst CLKDIV Sel
27 26 25 24 23 22 21 20 19 18 17 16 15 . 8 7 0
Edge = select rise/fall edge of trigger signalStart = trigger source to start conversion
000 = halt001 = start now (software control)010-111 : Hardware-controlled: convert channels in Sel from 0-7
010/011 = P0-16/P0-22 pin triggers conversion100-111 = MAT0-1, MAT0-3, MAT1-0, MAT 1-1
match event triggers conversion
Burst = 0 for software control, 1 for hardware controlCLKS = # clocks (4 to 11) => resolution 3 to 10 bitsSel = Pin(s) to be sampled (one bit per pin)CLKDIV = pclk divider (divide to 4.5MHz or lower)PDN = 1 to enable the converter, o/w power down
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LPC 22xx A/D data register (ADDR)
Done Overrun CHN V/V3A
31 30 29 28 27 26 25 24 23 . 16 15 . 6 5 .0
Converted sample(represents V / Vref)
Channel #of convertedsample
Conversion done(sample valid)--------------------------Clears on data read
New sample has overwrittenprevious (unread) sample
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S/W-controlled example
VPBDIV = 0x02; // pclk = 30MHz
IO1DIR = 0x00FF0000; //P1.16-23 outputs
ADCR = 0x00270601; //10 bits @ 3 MHzADCR |= 0x01000000; // set START bit
while (1) {
val = ADDR; // read data reg
check DONE & repeat until 1
}
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H/W-controlled example
VPBDIV = 0x02; // pclk = 30MHz
IO1DIR = 0x00FF0000; //P1.16-23 outputs
ADCR = 0x00270607; //10 bits @ 3 MHz
ADCR |= 0x01000000; // enable conversionVICVectCnt10 = 0x32;
VICVectAddr0 = (unsigned) AD_ISR;
VICVectEnable = 0x00040000;while (1) {}
ISR on next page
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HW-controlled example (continued)
void AD_ISR (void) __irq {
unsigned val, chan;
static unsigned result[4];
` val = ADDR; // read data reg
val = ((val>>6) & 0x03FF); // result
chan = ((ADCR>>0x18) & 0x07); //channel
result[chan] = val; // save
}
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Sigma Delta ADC
High resolution (16 or more bits) High integration
Reasonable cost
Often used to sample CD-quality audio 16-bit resolution @ 44.1Ksamples/sec
Oversampling used to spread noise over
wider frequency range Digital filtering eliminates the noise
Gives good dynamic range with simple ADC
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Sigma-Delta ADC
High rate bitstream
Density of 1s at
modulator outputproportional to theinput signal.
Filtering extractsInfo from serialdata stream.(lower rate)
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Sigma-Delta A/D Converter
Comparator
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Modulator operation
Slope of integrator output depends onmagnitude of Vin
sigma => summing/integration
Compare integrator output to 0v, producing1 if positive and 0 if negative (1-bit ADC)
delta = difference
Density of 1s in the bitstream proportional tomagnitude of input voltage Vin
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Example
Filtering determines average voltage (density of 1s) in bitstream
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Maxim MAX1402 Sigma-Delta ADC
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ADC converter characteristicsType Need
SHA?
Cycles/
conversion
Advant-
ages
Disadvant-
ages
Example
Flash No 1 Fastest Expensive,power
6-bit @400MHz
Successive
Approx-imation
Yes >= 2 Fast,
cheap
Slower
than flash
8-bit @
20 MHz
Integrating Yes Varies Precise Slow 22-bit @20Hz
Sigma-Delta
No Many Mostlydigital,linear,highresolution
Complexdigitalcircuit
16-bit @100 KHz
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ADC converter comparison
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