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Challenges in CMOSMiniaturization
Muhammad Amin Qureshi
GSSE
PAF-KIET
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Why Scaling?
Increase chip packing density
Better performance (speed)
Response to switching signals
Reduced cost per transistor
Low-power consumption
Light-weight products Increase current drive (transconductance)
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Moores Law
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How to Scale?
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How to Scale?
DennardsScaling TheoryConstant Electric Field
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Problems in Scaling
The basic need was to reduce channel length Short-Channel Effects
Voltage scaling
Doping scaling
Constant Electric Fieldvoltage per unit dimension
Scaling could not follow Dennardstheory
precisely, but came along nicely Reaching physical limits
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Problems in Scaling
Short-Channel Effects Threshold voltage lowering
Depletion regions bulge
Electrostatic charge sharing between gate anddrain/source
Requires lesser gate charge
to start inversion
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Problems in Scaling
Drain-Induced Barrier Lowering (DIBL) Unintended charge sharing between drain and
source
Increase in VDSpulls the drain conduction banddown
Drain-to-channel depletion width expands
The potential barrier at source is lowered Significant leakage current (Ioff)
VTis lowered
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Problems in Scaling
DIBL
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Problems in Scaling
Channel-length modulation In saturation, IDSis independent of VDS.
The depletion region of p-n junction at drain
expands because excess Vdsat drops across thedrain junction depletion region.
Effective channel length decreased
Current increases with VDS
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Problems in Scaling
Gate Oxide Thickness issue
Toxmust be reduced to avoid short-channel effects
Inherits some more problems
Only a few atomic layers thick Quantum-mechanical activity occurs
Exponentially increasing gate leakage currents
Direct Tunneling of electrons beyond gate in to the channel
Use of High-K Oxide or Metal Gate
Metal gates are backbecause no depletion Implementation challenges at sub-100nm regime
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Problems in Scaling
Gate Oxide Issues The gate might damage due to the flowing
currents
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Problems in Scaling
Subthreshold Leakage Current in channel does not abruptly becomes
zero below threshold
Or.. the more thermally energetic electronsovercome the potential barrier to enter thechannel while the VGS< VTH
Subthreshold conduction
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Problems in Scaling
Heavy doping to reduce DIBL and SCE
Results in:
Increased Lateral Electric Field GIDL
BTBT
Low mobility of electrons due to impurity
scattering Larger capacitance in high depletion-charge
channel; reduced on current
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Problems in Scaling
Band-to-Band Tunneling Heavy doping causes higher electric fields
BTBT happen near drain and make a bendbending
of 1-2V for 100 distance
Gate-Induced Drain Leakage Gate overlaps the drain
Gate at negative voltage; drain at high voltage
High doping = Narrow depletion region
Tunneling of electrons from the channel to drain
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Problems in Scaling
Mobility Degradation Due to high doping and thus high electric fields
Carriers are pushed towards the Si-SiO2interface Surafce scattering
Imputrity scattering the dopants
Random Dopant Distribution Doping in channel is highly random
Only a few hundred dopants in sub-100nmdevices
Random dopants in a retrograde channel doping
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Trends
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Trigate Transistor22nm (Intel)
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Trigate Benefits
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Power
Power was not discussed A bottle-neck for higher performance
Static power governed by subthreshold leakage
and gate leakage Dynamic power governed by switching
Though Dennardstheory maintained powerdensity per chip, it increased in implementation
Millions/billions of transistors per chip Though only a few percent switch at a time
Still a lot of power
Limit the operation frequency
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Conclusion
Moores law and Dennardstheory are going toend, for the current CMOS technology at least
New technologies required to cope up with the
performance requirements and packing morelogic into the chips
Intels trigate transistor is a revolutionary
invention Silicon and CMOS will stay a bit longer
Early introduction of 22nm in 2012
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