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TM
March 1997
CDP1802AC/3 High-Reliability CMOS 8-Bit Microprocessor
Features For Use In Aerospace, Military, and Critical IndustrialEquipment
• Minimum Instruction Fetch -Execute Time of 4.5 µs (Maximum Clock Frequency of 3.6MHz) at V DD =5V, T A = +25 oC
• Operation Over the Full MilitaryTemperature Range . . . . . . . . . . . . . . . -55 o C to +125 oC
• Any Combination of Standard RAM and ROM Up to65,536 Bytes
• 8–Bit Parallel Organization With Bidirectional DataBus and Multiplexed Address Bus
• 16 x 16 Matrix of Registers for Use as Multiple Pro-gram Counters, Data Pointers, or Data Registers
• On-Chip DMA, Interrupt, and Flag Inputs
• High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of V DD
Description The CDP1802A/3 High -Reliability LSI CMOS 8 -bit registeroriented Central -Processing Unit (CPU) is designed for useas a general purpose computing or control element in a widerange of stored -program systems or products.
The CDP1802A/3 includes all of the circuits required forfetching, interpreting, and executing instructions which havebeen stored in standard types of memories. Extensiveinput/output (I/O) control features are also provided to facili-tate system design.
The 1800 Series Architecture is designed with emphasis onthe total microcomputer system as an integral entity so thatsystems having maximum flexibility and minimum cost can be
realized. The 1800 Series CPU also provides a synchronousinterface to memories and external controllers for I/O devices,and minimizes the cost of interface controllers. Further, the I/Ointerface is capable of supporting devices operating in polled,interrupt -driven, or direct memory -access modes.
The CDP1802AC/3 is functionally identical to its predeces-sor, the CDP1802. The “A” version includes some perfor-mance enhancements and can be used as a directreplacement in systems using the CDP1802.
This type is supplied in 40 lead dual -in-line sidebrazedceramic packages (D suffix).
Pinout CDP1802AC/3 (SBDIP)
TOP VIEW
Ordering Information
PACKAGETEMP. RANGE
(oC) 5V - 3.2MHzPKGNO.
SBDIP -55 to 125 CDP1802ACD3 D40.6
13
1
2
3
4
5
6
7
8
9
1011
12
14
15
16
17
18
19
20
CLOCK
WAIT
CLEAR
Q
SC1
SC0
MRD
BUS 7
BUS 6
BUS 5BUS 4
BUS 3
BUS 2
BUS 1
BUS 0
VCCN2
N1
N0
VSS
28
40
39
38
37
36
35
34
33
32
3130
29
27
26
25
24
23
22
21
VDDXTAL
DMA IN
DMA OUT
INTERRUPT
MWR
TPA
TPB
MA7
MA6MA5
MA4
MA3
MA2
MA1
MA0
EF1
EF2
EF3
EF4
File Number 1441.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143
|Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
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CDP1852INPUT PORT
DATA CS1CS2CDP1852
OUTPUTPORT
CLOCK
CS1CS2 MA0–7N0
MRD
MWR
N1
TPB DATA TPA
CDP18028–BIT CPU
MRD
MA0–4
MWR
CS
CDP182432 BYTE RAM
MA0–7
DATA
CEO
TPA
MRD
8–BIT DATA BUS
ADDRESS BUS
CDP18331K–ROM
DATA
FIGURE 1. TYPICAL CDP1802A/3 SMALL MICROPROCESSOR SYSTEM
CDP1802AC/3
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Absolute Maximum Ratings Thermal InformationDC Supply Voltage Range, (V DD)
(All Voltages Referenced to V SS Terminal)CDP1802AC/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V DD +0.5VDC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . . ± 10mA
Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)SBDIP Package . . . . . . . . . . . . . . . . . . . 55 15Device Dissipation Per Output TransistorTA = Full Package Temperature Range . . . . . . . . . . . . . . . . 100mWOperating Temperature Range (T A)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . .-55 oC to +125 oCStorage Temperature Range (T STG ). . . . . . . . . . . .-65 oC to +150 oC
Lead Temperature (During Soldering)At distance 1/16 ± 1/32 In. (1.59 ±0.79mm)from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions TA = Full Package Temperature Range. For maximum reliability, operating conditionsshould be selected so that operation is always within the following ranges
PARAMETER MIN MAX UNITS
DC Operating Voltage Range 4 6.5 V
Input Voltage Range V SS VDD V
Maximum Clock Input Rise or Fall Time - 1 µs
Performance Specifications
PARAMETER V DD (V) -55 oC TO +25 oC +125 oC UNITS
Minimum Instruction Time (Note 1) 5 4.5 5.9 µs
Maximum DMA Transfer Rate 5 450 340 Kbytes/s
Maximum Clock Input Frequency,Load Capacitance (C L) = 50pF, f CL
5 DC-3.6 DC-2.7 MHz
NOTE:
1. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3machine cycles - one Fetch and two Execute operations.
Static Electrical Specifications All Limits are 100% Tested
PARAMETER
CONDITIONS -55 oC, +25 o C +125 oC
UNITSVOUT
(V) VIN, (V) VCC, VDD (V) MIN MAX MIN MAX
Quiescent Device Current, I DD - - 5 - 100 - 250 µA
Output Low Drive (Sink) Current(Except XTAL), I OL
0.4 0, 5 5 1.20 - 0.90 - mA
XTAL 0.4 5 5 185 - 140 - µA
Output High Drive (Source)Current (Except XTAL), I OH 4.6 0, 5 5 - -0.30 - -0.20 mA
XTAL 4.6 0 5 - -135 - -100 µA
Output Voltage Low-Level, V OL - 0, 5 5 - 0.1 - 0.2 V
Output Voltage High-Level, V OH - 0, 5 5 4.9 - 4.8 - V
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Input Low Voltage, V IL 0.5, 4.5 - 5 - 1.5 - 1.5 V
Input High Voltage, V IH 0.5, 4.5 - 5 3.5 - 3.5 - V
Input Leakage Current, I IN AnyInput
0, 5 5 - ±1 - ±5 µA
Three-State Output LeakageCurrent, I OUT
0, 5 0, 5 5 - ±1 - ±5 µA
NOTE:
2. 5V level characteristics apply to Part No. CDP1802AC/3, and 5V and 10V level characteristics apply to part No. CDP1802A/3.
Timing Specifications As a Function of T (T = 1/fCLOCK), C L = 50 pF
PARAMETER V DD (V)
LIMITS (NOTE 3)
-55 o C, +25 o C +125 oC UNITS
High-Order Memory-Address Byte Setup to TPA Time, t SU 5 2T-450 2T-580 ns
High-Order Memory-Address Byte Hold After TPA Time, t H 5 T/2 +0 T/2 +0 ns
Low-Order Memory-Address Byte Hold After WR Time, t H 5 T-30 T-40 ns
CPU Data to Bus Hold After WR Time, t H 5 T-170 T-250 ns
Required Memory Access Time Address to Data, t ACC 5 5T-300 5T-400 ns
NOTE:
3. These limits are not directly tested.
Implicit Specifications (Note 4) T A = -55 oC to +25 oC
PARAMETER SYMBOL V DD (V)TYPICALVALUES UNITS
Typical Total Power DissipationIdle “00” at M(0000), C L = 50pF
f = 2MHz - 5 4 mW
Effective Input Capacitance any Input - C IN - 5 pF
Effective Three-State Terminal Capacitance Data Bus - - 7.5 pF
Minimum Data Retention Voltage - V DR - 2.4 V
Data Retention Current - IDR
2.4 10 µA
NOTE:
4. These specifications are not tested. Typical values are provided for guidance only.
Static Electrical Specifications All Limits are 100% Tested (Continued)
PARAMETER
CONDITIONS -55 oC, +25 o C +125 oC
UNITSVOUT
(V) VIN, (V) VCC, VDD (V) MIN MAX MIN MAX
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Dynamic Electrical Specifications CL = 50pF, Timing Measurement at 0.5 V DD Point
PARAMETERS V DD (V)
-55 oC TO +25 o C +125 oC
UNITSMIN MAX MIN MAX
Progagation Delay Times, t PLH , tPHL
Clock to TPA, TPB 5 - 275 - 370 ns
Clock-to-Memory High Address Byte, t PLH , tPHL 5 - 725 - 950 ns
Clock-to-Memory Low Address Byte Valid, t PLH , tPHL 5 - 340 - 425 ns
Clock to MRD, t PLH , tPHL 5 - 340 - 425 ns
Clock to MWR, t PLH , tPHL 5 - 275 - 370 ns
Clock to (CPU DATA to BUS) Valid, t PLH, tPHL 5 - 430 - 550 ns
Clock to State Code, t PLH , tPHL 5 - 440 - 550 ns
Clock to Q, t PLH , tPHL 5 - 375 - 475 ns
Clock to N (0 - 2), tPLH
, tPHL
5 - 400 - 525 ns
Interface Timing Requirements (Note 5)
Data Bus Input Setup, t SU 5 10 - 10 - ns
Data Bus Input Hold, t H 5 175 - 230 - ns
DMA Setup, t SU 5 10 - 10 - ns
DMA Hold, t H 5 200 - 270 - ns
Interrupt Setup, t SU 5 10 - 10 - ns
Interrupt Hold, t H 5 175 - 230 - ns
WAIT Setup, t SU 5 30 - 30 - ns
EF1-4 Setup, t SU 5 20 - 20 - ns
EF1-4 Hold, t H 5 100 - 135 - ns
Required Pulse Width Times
CLEAR Pulse Width, t WL 5 150 - 200 - ns
CLOCK Pulse Width, t WL 5 140 - 185 - ns
NOTE:
5. Minimum input setup and hold times required by Part CDP1802AC/3.
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Performance Curves
FIGURE 2. TYPICAL MAXIMUM CLOCK FREQUENCY AS AFUNCTION OF TEMPERATURE
FIGURE 3. TYPICAL MAXIMUM CLOCK FREQUENCY AS AFUNCTION OF SUPPLY VOLTAGE
FIGURE 4. TYPICAL TRANSITION TIME vs LOADCAPACITANCE
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENTCHARACTERISTICS
FIGURE 6. MINIMUM OUTPUT LOW (SINK) CURRENTCHARACTERISTICS
NOTES:
6. Idle = “00” at M (0000)
7. Branch = “3707” at M (8107)
FIGURE 7. TYPICAL POWER DISSIPATION AS A FUNCTIONOF CLOCK FREQUENCY FOR BRANCHINSTRUCTION AND IDLE INSTRUCTION
5
4
3
2
1
0
6
7
8
35 45 55 65 75 85 95 105 11525 125 S Y S T E M M A X I M U M C L O C K F R E Q U E N C Y
( f C L ) (
M H z )
VDD = 5V
LOAD CAPACITANCE (C L) = 50pF
AMBIENT TEMPERATURE (T A) (o C)
3 4 5 6 7 8 9 10 122
SUPPLY VOLTAGE (V DD) (V)
11
5
4
3
2
1
0
6
7
S Y S T E M M A X I M U M C L O C K F R E Q U E N C Y
( f C L
) ( M H z )
8LOAD CAPACITANCE (C L) = 50pF
TA = 25 oC
TA = 125 oC
E X T R
A P O L
A T E D
50 75 100 125 150 175 20025
300
250
200
150
100
350
400
0
50 T R A N S I T I O N T I M E ( t T H L , t T L H
) ( n s ) AMBIENT TEMPERATURE (T A) = 25 o C
0LOAD CAPACITANCE (C L) (pF)
tTLH
tTHL
-9 -8 -7 -6 -5 -4 -3-10
2
3
4
5
6
1
0-2 -1
O U T P U T H I G H ( S O U R C E ) C U R R E N T
( I O H - m
A )
DRAIN TO SOURCE VOLTAGE (V DS ) (V)
GATE TO SOURCE VOLTAGE (V GS ) = -5V
AMBIENT TEMPERATURE = -40 TO +85 oC
0
25
20
15
10
5
30
35
1 2 3 4 5 6 70 8 9 10
GATE TO SOURCE VOLTAGE (V GS ) = 5V
AMBIENT TEMPERATURE = -40 oC TO +85 oC
O U T P U
T L O W
( S I N K ) C U R R E N T ( I O L
) ( m A )
0
DRAIN-TO-SOURCE VOLTAGE (V DS ) (V)
10
1
0.1
100
1000
0.01 0.1 1 10
AMBIENT TEMPERATURE (T A) = 25 o C
CLOCK INPUT FREQUENCY (f CL) (MHz)
T Y P I C A L P O W E R D I S S I P A T I O N
( P D
) ( m W )
V C C = V D D = + 5 V V C C
= V D D = 5 V
“ B R A N C H ”
“ I D L E ”
CDP1802AC/3
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All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Burn-In Circuit
NOTE: Any output except XTAL.
FIGURE 8. TYPICAL CHANGE IN PROPAGATION DELAY AS A FUNCTION OF A CHANGE IN LOAD CAPACITANCE
TYPE V DD TEMPERATURE TIME
CDP1802AC 7V +125 oC 160 Hours
FIGURE 9. BIAS/STATIC BURN-IN CIRCUIT
Performance Curves (Continued)
100
75
50
25
0
125
150
∆
P R O P A G A T I O N D E L A Y T I M E
( ∆ t P L H , ∆
t P H L
) ( n s )
50 100 150 2000∆ LOAD CAPACITANCE ( ∆ CL) (pF)
AMBIENT TEMPERATURE(TA) = 25 o C
V C C = V D D = 5 V
∆ t P H L
∆ t P L H
V C C = V D
D = 5 V
VDD
VDD
NC
NC
VDD
VDD
NC
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
ALL RESISTORS ARE 47k Ω ±20%
CDP1802AC/3