Preliminary Product Information This document conCirrus Logic reserv
Copyrig(P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581http://www.cirrus.com
CDB43122
Evaluation Board for CS43122/CS4397
FeatureslDemonstrates recommended layout and grounding arrangements
lCS8414 receives AES/EBU, S/PDIF, & EIAJ-340 Compatible Digital Audio
lSupports PCM Audio and SACD Audio lRequires only a digital signal source for a
complete Digital-to-Analog Converter systeml Included Wall Mount power supply
DescriptionThe CDB43122 evaluation board is an excellent meansfor quickly evaluating the CS43122 or CS4397 24bit-192 kHz D/A converters. The board accepts SPDIF andSACD inputs and, with an analog output interface, pre-sents line level signals via XLR connectors. Evaluationrequires an analog signal analyzer and a digital signalsource.
The CS8414 digital audio receiver I.C. provides the sys-tem timing and data signals necessary to operate theDigital-to-Analog converter and will accept AES/EBU,SPDIF and EIAJ compatible audio data. The evaluationboard may also be configured to accept external timingsignals for operation in a user application during systemdevelopment in PCM and DSD modes.
ORDERING INFORMATIONCDB43122 Evaluation Board
I
CS8414
EXT.PCM/DSD
INPUTSELECTOR
MODESELECTOR
CS43122
ANALOGFILTER
ANALOGFILTER
POWER SUPPLYREGULATION
tains information for a new product.es the right to modify this product without notice.
1
ht Cirrus Logic, Inc. 2001All Rights Reserved)
MAR ‘01DS526DB1
CDB43122
TABLE OF CONTENTS1. CDB43122 SYSTEM OVERVIEW ............................................................................................. 32. CS43122 DIGITAL TO ANALOG CONVERTER ....................................................................... 33. CS8414A DIGITAL AUDIO RECEIVER .................................................................................... 34. EXTERNAL DIGITAL AUDIO DATA AND DSD INPUT PORT .................................................. 35. MODE CONTROL ..................................................................................................................... 36. AUTOMATIC SWITCHING MODE............................................................................................. 37. OUTPUT FILTER ....................................................................................................................... 48. POWER SUPPLIES .................................................................................................................. 49. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................. 410. CS43122 MODE SETTINGS..................................................................................................... 611. SCHEMATICS ......................................................................................................................... 712. PCB ARTWORK .................................................................................................................... 10
LIST OF FIGURESFigure 1. Power Supply ................................................................................................................... 6Figure 2. Output Filter ..................................................................................................................... 7Figure 3. Input Reciever, DAC ........................................................................................................ 8Figure 4. Silkscreen Top ................................................................................................................. 9Figure 5. Top Layer ....................................................................................................................... 10Figure 6. Second Layer ................................................................................................................. 11Figure 7. Third Layer ..................................................................................................................... 12Figure 8. Bottom Layer.................................................................................................................. 13
LIST OF TABLESTable 1. Single Speed (16 to 50 kHz) Digital Interface Format Options.......................................... 5Table 2. Single Speed (16 to 50 kHz) De-Emphasis Options ......................................................... 5Table 3. Double Speed (50 to 100 kHz) Sample Rate Mode Options............................................. 5Table 4. Quad Speed(100 to 200 kHz) Sample Rate Mode Options .............................................. 5Table 5. 8x Interpolated Input Mode Options (CS43122 only) ........................................................ 5Table 6. Direct Stream Digital Options (CS43122 only) ................................................................. 5Table 7. SWITCH S2 MODE SETTINGS TABLE........................................................................... 6
Contacting Cirrus Logic SupportFor a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the informationcontained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty ofany kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information beingrelied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including thosepertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, includinguse of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is theproperty of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights,copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information containedherein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other partsof Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to othercopying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic,Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in somejurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2 DS526DB1
CDB43122
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1. CDB43122 SYSTEM OVERVIEW
The CDB43122 evaluation board is an excellentmeans of quickly evaluating the CS43122 orCS4397 24 bit - 192 kHz audio D/A converters.The evaluation board features a CS8414 digital au-dio input interface receiver, an analog output buff-er/filter, and on board power supply regulation tobe used with a supplied AC Wall Mount powersupply. The CS8414 provides an easy interface to32 kHz to 96 kHz digital audio signal sources. Theevaluation board also allows the user to supply ex-ternal PCM data and DSD data through a 10-pinheader for system development.
2. CS43122 DIGITAL TO ANALOG CONVERTER
Please refer to the CS43122 or CS4397 productdatasheets for a complete detailed description ofthese components.
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standardS/PDIF data format using a CS8414 Digital AudioReceiver, Figure 1. The outputs of the CS8414 in-clude a serial bit clock, serial data, left-right clock(FSYNC), de-emphasis control and a 256 Fs mas-ter clock. The operation of the CS8414 and a dis-cussion of the digital audio interface are included inthe CS8414 datasheet.
4. EXTERNAL DIGITAL AUDIO DATA AND DSD INPUT PORT
The evaluation board has been designed to allowinterfacing to external systems via the 10-pinheader, JP1. This header allows the evaluationboard to accept externally generated clocks and da-ta.
The port is activated by setting the “MODE” Con-trol Switch “S2” position 6 “INT/EXT” switch tothe closed position.
This port accepts PCM data, DSD (CS4397) dataor data from an external 8X interpolator such as an
HDCD PMD100 or PMD200. Notice that theboard has provisions for terminating this input pofor proper signal integrity using resistors R2through R24.
The board also features automatic mode switchbetween this port and the SPDIF port when uswith a SACD player. See Section 6- “AutomatMode Switching” for a complete description of thfeature.
5. MODE CONTROL
The board utilizes a Dip Switch, “S2” to allow thuser to select various operational modes of tCS43122 or CS4397. These modes include setion of the Digital Interface Format, De-emphasiSample Rate modes, Internal-External Digital Adio Data, PCM-DSD Automatic Switching, 64x 128x DSD Data, +3 V/+5 V Digital Supply voltageselection, and Mute control. See Tables 1 througfor a complete description of how the switch setings set the different operating modes of tCS43122.
6. AUTOMATIC MODE SWITCHING
The board features an automatic PCM or DSD put data switching mode for use with an externSACD player. When used with an external SACplayer that has both a SPDIF output connectedJ1 (U5) and DSD data output connected to the Jport, will allow the board to switch automaticallbetween the two.
Theory of operation - When an SACD playeswitches from playing a CD to a DSD disc, the SDIF output data is disabled, the internal circuit(U6, U2, U3, U4, U7) detects loss of an SPDsource and automatically switches the Digital DaInput path (U8) to the DSD input port JP1. Thfeature can also be controlled from an external cotrol signal by removing R60 and inputting a contrsignal into JP2. Logic low = PCM mode, Logihigh = DSD mode.
DS526DB1 3
CDB43122
7. OUTPUT FILTER
The output buffer/filter uses a balanced configura-tion. The balanced output filter consist of the 301ohm resistors and the 2200pf capacitor, and is de-signed to cancel out the opposing multibit step pat-tern in each analog output to create a very low outof band noise spectrum. The op-amps provide out-put buffering and are configured to provide a+4.5db boost when the board switches into DSDmode to compensate for the 4.5db gain loss of theCS4397 in DSD mode. The balanced outputs areAC coupled and are provided on board by XLRtype connectors.
8. POWER SUPPLIES
The CDB43122 comes supplied with an external14 VAC Wall Mount power supply for conve-nience in setup, and to make measurements easierby eliminating ground loop problems between labpower supplies and measurement equipment (Note:the provided wall mount supply only operates at110/120V and 50/60 Hz). The external 14 VACvoltage supplied at J11 is rectified, filtered and reg-ulated to produce +/-12 volts by regulators U13 andU14. Separate voltage regulation is used for thedigital control circuitry (CS8414) and for the digi-tal power section and analog section for theCS43122 - CS4397. The digital power for theCS43122 - CS4397 is user selectable by switch #9on dip switch S2. The open position sets the voltageregulator VREG2 to +5.0 volts, the closed positionsets the voltage regulator to +3.3 volts.
The CDB43122 evaluation board can also be pow-ered by an external lab power supply by connecting+12 vdc to the +12V (J8) binding post, -12 vdc to -12V (J10), and ground to GND (J9). Up to +/- 13volts is allowed before reverse voltage protection
diodes D3 and D4 will clamp the input voltage.With JP5 connected, the +5V, VD and VA supplieswill be regulated from the supplied +12V. To pro-vide VA and VD externally via the designatedbinding posts, remove JP5 and lift pin 3 (bottomright pin) on VREG1; +5V to the CS8414 will stillbe provided by the on board regulator.
WARNING: refer to the CS43122 datasheet formaximum allowable voltage levels. Operation out-side this range can cause permanent damage to thedevice.
9. GROUNDING AND POWER SUPPLY DECOUPLING
For the user to be able to realize the high perfor-mance capabilities of the CS43122 or CS4397, it isrecommended to pay careful attention to PC boardlayout, grounding, and placement of the power sup-ply and decoupling capacitors. It is recommendedwhen doing the PC board layout to use one groundplane underneath the part for both the analog anddigital sections. Please review the attached PCboard photo plots for an example of the suggestedgrounding method.
It is also recommended to pay careful attention tothe placement of the decoupling capacitors tied toVREF (pin 28). This pin requires a very low im-pedance path to ground at high frequencies as thispin draws high frequency current pulses at 6 MHz.It is important to place the .01 uf capacitor and100 uf capacitor right next to the pin. Keep the con-necting trace as short as possible. High perfor-mance capacitors such as NPO for the .01 uf and alow ESR electrolytic or tantalum for the 100 uf arerecommended. Low frequency distortion (0-40Hz)performance can also be improved by increasingthe FILT+ (pin 27) capacitance value up to 470uf.
4 DS526DB1
CDB43122
10. CS43122/CS4397 MODE SETTINGS (SW2)
1. Note: Switch #’s 1 to 4 must be open for audio mode to function properly.
Switch # Label Position Description 1 MO OPEN = 1 See CS43122 datasheet for details2 M1 OPEN = 1 See CS43122 datasheet for details3 M2 OPEN = 1 See CS43122 datasheet for details4 M3 OPEN = 1 See CS43122 datasheet for details5 M4 OPEN = 1 See CS43122 datasheet for details6 INT/EX1 OPEN = INT SETS THE INPUT MUX TO THE CS8414 (INT) OR TO JP1 (EX1)7 PCM/DSD OPEN = DISABLED Activates Auto Switching for PCM and DSD8 64/128X OPEN = 128X SETS THE CLOCK MODE FOR DSD9 +3V/5V OPEN = +5V SETS THE DIGITAL POWER SUPPLY TO +3.3 OR +5 VOLTS
10 /MUTE CTL OPEN = DISABLED ENABLES THE EXTERNAL MUTE CONTROL CIRCUITRYDEFAULT SWITCH 9 SET CLOSED, ALL OTHERS SET TO OPEN
SWITCH S2 MODE SETTINGS TABLE
DS526DB1 5
CD
B43122
6D
S526D
B1
+20V-12V
+12V
+12V
+5V
U13LM317T
31 2
VIN
ADJ
VOUT
90UFSP_3 528
6630ES_0 805%
R651101%
C6010UFCSP_3 528
R63953
1%
C6110UFCSP_3 528
R611101%C56
47UF25V
LT1117SO T223
VREG 3
1 2 34
ADJ
OUT
IN
TAB
C57
10UFCSP_3 528
C6210UFCSP_3 528
+3V/+5V
-12V+12V
-20V
+20V
-20V
+5VA VD+3/+5
+12V
+5.5VAVD+3/+5
C4647UF25V
C85100UF25V
C4910UFCSP_3 528
R58560RES_ 0805 5%
D2GREEN LEDPOWE R
J13
VD+3/+5
1
U14LM 337T
21 3
VIN
ADJ
VOUT
J8
+12VDC
1
R629531%
J9
GND
1
C5847UF25V
J10
-12VDC
1
R641101%
D4
P6KE13
12
C51C
D3
P6KE13
12
C84100UF25VC52
100UF25V
C53100UF25V
J11
POWERJAC K
23
1
J12
+5.5VA
1
JP5+12V INT/EXT
1 2
SHORTING-JUMPER
JMPHDR1
SHORTING-JUMPER
JMPHDR2
C55
4700UF25V
R3R1
R59365RES_ 08051%
D5
1N4003T
12
R55390
5%
D6
1N4003T1
2
LT1117SO T223
VREG 1
1 2 34
ADJ
OUT
IN
TAB
R56330
1%
R541101%
C544700UF25V
C5147UF25V
C4710UFCSP_ 3528
C4810UFCSP_3 528
LT1117SO T223
VREG 2
1 2 34
ADJ
OUT
IN
TAB
R571101%
C5010UFCSP_3 528
+3V/+5V
Figure 1. Power Supply
CD
B43122
DS
526DB
17
MALE
MALE
3
Q2SC3326
1
23
C408200PF
JP3CIRDIN_3-P
1 2
3
C728200PF
53326
1
23
C358200PF
%
1%
R79 301 PIH1%
JP2CIRDIN_3-P
1 2
3
43326
1
23
05
R78 432
%
33326
1
23
1%
C278200PF
MUT E
MUT E
MUT E
MUT E
DSD
DSD
DSD
DSD
+12V
-12V
+12V
-12V
+12V
-12V
-12V
+12V
+12VQ62SC3326
1
2
~
U21LT1028
3
26
74 1 8
R91
N.S. PIHRN551%
~
U15LT1028
3
26
74 1 8
C71
.1UF0805
2
C77 1UFCAP, 1UF, MF, 50V, 5%
C65.1UF
0805
R82 301 PIH
RN55
1%
R80 470
RES_0 805 5%
R7747KRES_0 8051%
C432200PF
R52 301 PIH
RN55
1%
C67.1UF
0805
R7647KRES_0 8051%
Q2SC
R81 432
RES_ 0805
1%
R53 51 PIH
RN55
1
C83 1UFCAP, 1UF, MF, 50V, 5%
R43 51 PIH
RN55
C63.1UF
0805
R7447KRES_0 8051%
R491KRES_0 8055%
R47 301 PIH
RN55
1%~
U17LT1028
3
26
74 1 8
RN55
R83 470
RES_0 805 5%
Q92SC3326
1
23
C64
.1UF0805
C78 10 UF 25VQ7
2SC3326
1
23
C79 1UFCAP, 1UF, MF, 50V, 5%
R92
N.S. PIHRN551%
Q2SCC68
.1UF0805
R7547KRES_0 8051%
R84 432
RES_ 0805
1%
R85 301 PIH
RN55
1%
R391KRES_0 85%
R37 301 PIH
RN55
1%
R86 470
RES_0 805 5%Q8
2SC3326
1
23
R441KRES_0 8055%
C69.1UF
0805
R89 470
RES_0 805 5%
R42 301 PIH
RN55
1%
C80 10 UF 25V
~
U19LT1028
3
26
74 1 8
C66
.1UF0805
C76 10 UF 25V
R87 432
RES_ 0805
1%
C302200PF
R88 301 PIH
RN55
1%
RES_ 0805
1%
C81 1UFCAP, 1UF, MF, 50V, 5%
R721KRES_0 8055%
R48 51 PIH
RN55
1
Q2SC
C82 10 UF 25V
R38 51 PIH
RN55
AOUT_ LEFT+
AOUT_RIGHT -
AOUT_RIGH T+
AOUT_L EFT-
MUTE
DSD
Figure 2. Output Filter
CD
B43122
8D
S526D
B1
/MUTE_CNTRL
/MUTE
M4 M3/INT/EXT
PCM/DSD
CM
-12V
+5.5VA
+5.5VA
+5.5VA
VD+3/+5
VD+3/+5
+5.5VA
C11.01UF
CSN_0603
C9.01UF
CSN_0603
C7410UFCSP_3528
C13.01UF
R701.0K
RES_06031%
1K805 5%
R3110K
5%
C15.01UF
R71499
RES_06031%
C1610UF
CSP_3528
R93499
RES_06031%
5
C1410UFCSP_3528
VCC GND
U4NC7SZ125
2
3
4
5
1
-
.
+
.
.
R5 1KRES_0805 5%
C12100UFSMT25V
S145TL50
RESET
24
5
2827262524232221201918171615
VREFFILT +FILT - OUTUT L -UT L+
VAGND1UT R+UT R -GND2UTE C
C/H/MUTE
C10100UFSMT
25V
HDR1
C20.1UF0805
9
R2910K
5%
Q1MMBT2907A L
1
23
0
5%
R3310KRES_06035%
MUT E
AOUT_LEFT-
AOUT_RIGHT-
AOUT_LEFT+
AOUT_RIGHT+
VBIAS
(L=CONNECT)
(L=ENABLE)
(DSD CLK MODE)
LOW = 256fs
HIGH = 384fs
(L=PCM)
- MODE TABLE - AUTO SW ITCHING
PCM
M0 = 1 M1 = 0 M2 = 1 M3 = 1 M4 = 0
DSD
M0 = 1 M1 = DSD_R M2 = 1 M3 = 0 M4 = 1 lrclk = 0 = 256fs lrclk = 1 = 384fs
(DEFAULT = OPEN)
(H=IN2)
(L=PCM)
RESET PIN?
(H= +4.5DB BOOST)
M1
+3V/+5V/MUTE_CNTRL
LRCLK
DSD_R
M2
SCK
/MUTE
M0
M1INT/EXT
/INT/EXT
INT/EXTM4M3
PCM/DSD64/128X
64/128X
MCLK
SDATA
INT/EXT
PCM/DSDPCM/DSDPCM/DSD
INT/EXT
VD+3/+5
VD+3/+5
+5V
VD+3/+5
VD+3/+5
VD+3/+5
VD+3/+5
VD+3/+5
VD+3/+5
VD+3/+5
VD+3/+5
VD+3/+5
VD+3/+5
VD+3/+5
+5V
-12V
+5.5VA+5V
+5V
+5V
C21.1UF0805
R6 10KRES_0603 5%
SCK
U5TORX173
SPDIF IN56 24
1
3
CASE1
CASE2
GND1
GND2
OUT
VCC
VCC GND
U7NC7SZ125
2
3
4
5
1
-
.
+
.
.
LRCLK
J1
1
2
..
R9 10KRES_0603 5%
SDATA
R1675RES_08055%
R4RES_0
R11 10KRES_0603 5%
L347UH
L1 47UH
R12 10KRES_0603 5%
C1810UF
C2 .01UF 0805
R13 10KRES_0603 5%
C19.01UF
C8 .01UF0805
VCCGND
U12 NC7SZ04
2
3
4
5
-+
U10NC7SZ374
123 4
56
CPGNDD Q
VCC/OE
R15 10KRES_0603 5%
R1560RES_08055%
C1
.1UF0805
C22 .1UF
0805
R1710K
RES_06035%
C4 .068UF0805
VCC GND
U9NC7SZ04
2
3
4
5
-
.
+
.
VCC GND
U2NC7SZ125
2
3
4
5
1
-
.
+
.
.
D1
GREEN LEDSPDIF ENABLED
C17
.1UF0805
C3.1UF0805
VCC GND
U22NC7SZ04
2
3
4
5
-
.
+
.
R21N.S.
5%
ON
S212345678
2019181716151413
9 1210 11
R8 470RES_08055%
R22N.S.
5%
Q10MMUN2111LT1
12
3
U6
CS8414-CS
1234567891011121314
2827262524232221201918171615
CCD/F1CC/F0CB/E2CA/E1/C0/E0VDDDGNDRXPRXNFSYNCSCKCS12/FCKU
ERRCE/F2SDATA
ERFM1M0VA+
AGNDFILTMCKM2M3SELCBL
R23N.S.
5%
U11
NC7SZ157
123 4
56
IN2GNDIN1 OUT
VCCSEL
C610UFCSP_3528
R24N.S.
5%
VCC GND
U3NC7SZ12
2
3
4
5
1
-
.
+
.
.
R20N.S.
5%R261K
5%
R9010KRES_06035%
PTS6
DAC
13
R251K
5%
U1
CS43122KS
1234567891011121314
/RSTM4 (AD0/CS)M3 (AD1/CDIN)M2 (SCL/CCLK)M0 (SDA/CDOUT)DGND1VDD1VDD2DGND2MCLKSCLKLR(CLK MODE)SDATA (DSD_L)M1 (DSD_R)
CMAOAO
AAOAOA
/M
JP6
JP7
R2 1KRES_0805 5%
R281K
5%
C5.1UF0805
R271K
5%
SPDIF/DSD
1 2
L2
47UH
S3PTS645TL50DAC MUTE
1 23 4
5
R3 1KRES_0805 5%
JP1
HDR5X2
246810
13579
D7 BAV9
1 2
3
1 2
3
R19N.S.
RES_08055%
R710K
RES_06035%
C23.1UF0805
R600RES_08055%
C7.1UF0805
R30 10
R18 10KRES_0603 5%
R10 100
RES_0603
5%
M1MCLK
U8 QS3384
Input Mux/Level Shifter
478
3
1417182122112
2
24
19
132320
161510
569
11
A1A2A3
A0
A5A6A7A8A9B0-4GND
B0
VCC
B7
B5-9B9B8
B6B5B4
B1B2B3
A4
+3V/+5V
DSD
Figure 3. Input Receiver, DAC
CDB43122
Figure 4. Silkscreen Top
DS526DB1 9
CDB43122
Figure 5. Top Layer
10 DS526DB1
CDB43122
Figure 6. Second Layer
DS526DB1 11
CDB43122
Figure 7. Third Layer
12 DS526DB1
CDB43122
Figure 8. Bottom Layer
DS526DB1 13
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