AT25080B/AT25160B/AT25320B/AT25640BAT25080B/AT25160B/
AT25320B/AT25640B
SPI Automotive Temperature Serial EEPROM 8 Kbits (1,024 x 8), 16
Kbits (2,048 x 8),
32 Kbits (4,096 x 8) and 64 Kbits (8,192 x 8)
Features • Serial Peripheral Interface (SPI) Compatible • Supports
SPI Modes 0 (0,0) and 3 (1,1):
– Data sheet describes mode 0 operation • Low-Voltage and
Medium-Voltage Operation:
– Grade 1, VCC = 2.5V to 5.5V – Grade 3, VCC = 1.7V to 5.5V
• Extended Temperature Range (Grade 1 and Grade 3 as defined in
AEC-Q100): – Grade 1 Temperature Range: -40°C to +125°C – Grade 3
Temperature Range: -40°C to +85°C
• 5 MHz Clock Rate (5V) • 32Byte Page Mode • Block Write
Protection:
– Protect 1/4, 1/2 or entire array • Write-Protect (WP) Pin and
Write Disable Instructions for Both Hardware and Software Data
Protection • Self-Timed Write Cycle within 5 ms Maximum •
Automotive AEC-Q100 Qualified • High Reliability:
– Endurance: 1,000,000 write cycles – Data retention: 100
years
• Green (Lead-free/Halide-free/RoHS Compliant) Package
Options
Packages • 8-Lead SOIC, 8-Lead TSSOP and 8-Pad UDFN
© 2020 Microchip Technology Inc. DS20006310A-page 1
Table of Contents
2. Pin
Description........................................................................................................................................
5
9.1. Package Marking
Information.....................................................................................................24
1. Package Types (not to scale) 8-Lead SOIC/TSSOP
(Top View)
CS 1
AT25080B/AT25160B/AT25320B/AT25640B Package Types (not to
scale)
© 2020 Microchip Technology Inc. DS20006310A-page 4
2. Pin Description The descriptions of the pins are listed in Table
2-1.
Table 2-1. Pin Function Table
Name 8-Lead SOIC 8-Lead TSSOP 8-Pad UDFN(1) Function CS 1 1 1 Chip
Select SO 2 2 2 Serial Data Output
WP(2) 3 3 3 Write-Protect GND 4 4 4 Ground
SI 5 5 5 Serial Data Input SCK 6 6 6 Serial Data Clock
HOLD(2) 7 7 7 Suspends Serial Input VCC 8 8 8 Device Power
Supply
Note: 1. The exposed pad on this package can be connected to GND or
left floating. 2. The Write-Protect (WP) and Hold (HOLD) pins
should be driven high or low as appropriate.
2.1 Chip Select (CS) The AT25080B/AT25160B/AT25320B/AT25640B is
selected when the Chip Select (CS) pin is low. When the device is
not selected, data will not be accepted via the Serial Data Input
(SI) pin, and the Serial Output (SO) pin will remain in a
highimpedance state.
To ensure robust operation, the CS pin should follow VCC upon
power-up. It is therefore recommended to connect CS to VCC using a
pull-up resistor (less than or equal to 10 kΩ). After power-up, a
low level on CS is required prior to any sequence being
initiated.
2.2 Serial Data Output (SO) The Serial Data Output (SO) pin is used
to transfer data out of the AT25080B/AT25160B/AT25320B/AT25640B.
During a read sequence, data is shifted out on this pin after the
falling edge of the Serial Data Clock (SCK).
2.3 Write-Protect (WP) The Write-Protect (WP) pin will allow normal
read/write operations when held high. When the WP pin is brought
low and the WPEN bit is set to a logic ‘1’, all write operations to
the STATUS register are inhibited. WP going low while CS is still
low will interrupt a write operation to the STATUS register. If the
internal write cycle has already been initiated, WP going low will
have no effect on any write operation to the STATUS register. The
WP pin function is blocked when the WPEN bit in the STATUS register
is set to a logic ‘0’. This will allow the user to install the
AT25080B/AT25160B/AT25320B/AT25640B in a system with the WP pin
tied to ground and still be able to write to the STATUS register.
All WP pin functions are enabled when the WPEN bit is set to a
logic ‘1’.
2.4 Ground (GND) The ground reference for the Device Power Supply
(VCC). The Ground (GND) pin should be connected to the system
ground.
AT25080B/AT25160B/AT25320B/AT25640B Pin Description
© 2020 Microchip Technology Inc. DS20006310A-page 5
2.5 Serial Data Input (SI) The Serial Data Input (SI) pin is used
to transfer data into the device. It receives instructions,
addresses and data. Data is latched on the rising edge of the
Serial Data Clock (SCK).
2.6 Serial Data Clock (SCK) The Serial Data Clock (SCK) pin is used
to synchronize the communication between a master and the AT25080B/
AT25160B/AT25320B/AT25640B. Instructions, addresses or data present
on the Serial Data Input (SI) pin is latched in on the rising edge
of SCK, while output on the Serial Data Output (SO) pin is clocked
out on the falling edge of SCK.
2.7 Suspend Serial Input (HOLD) The Suspend Serial Input (HOLD) pin
is used in conjunction with the Chip Select (CS) pin to pause the
AT25080B/ AT25160B/AT25320B/AT25640B. When the device is selected
and a serial sequence is underway, HOLD can be used to pause the
serial communication with the master device without resetting the
serial sequence. To pause, the HOLD pin must be brought low while
the Serial Data Clock (SCK) pin is low. To resume serial
communication, the HOLD pin is brought high while the SCK pin is
low (SCK may still toggle during HOLD). Inputs to the Serial Data
Input (SI) pin will be ignored while the Serial Data Output (SO)
pin will be in the highimpedance state.
2.8 Device Power Supply (VCC) The Device Power Supply (VCC) pin is
used to supply the source voltage to the device. Operations at
invalid VCC voltages may produce spurious results and should not be
attempted.
AT25080B/AT25160B/AT25320B/AT25640B Pin Description
© 2020 Microchip Technology Inc. DS20006310A-page 6
3. Description The AT25080B/AT25160B/AT25320B/AT25640B provides
8,192/16,384/32,768/65,536 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as
1,024/2,048/4,096/8,192 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications
where lowpower and lowvoltage operation are essential. The device
is available in space-saving 8lead SOIC, 8lead TSSOP and 8pad UDFN
packages. All packages operate from 1.7V to 5.5V.
3.1 SPI Bus Master Connections to Serial EEPROMs SPI Master:
Microcontroller
3.2 Block Diagram
4. Electrical Characteristics
4.1 Absolute Maximum Ratings Operating temperature -40°C to
+125°C
Storage temperature -65°C to +150°C
Voltage on any pin with respect to ground -1.0V to +7.0V
VCC 6.25V
ESD protection > 2 kV
Note: Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operation listings of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
4.2 DC and AC Operating Range Table 4-1. DC and AC Operating
Range
AT25080B/AT25160B/AT25320B/AT25640B Automotive Grade 1 Automotive
Grade 3
Operating Temperature (Case) -40°C to +125°C -40°C to +85°C
VCC Power Supply 2.5V to 5.5V 1.7V to 5.5V
4.3 DC Characteristics Table 4-2. DC Characteristics(1)
Parameter Symbol Minimum Typical Maximum Units Conditions
Supply Voltage VCC1 2.5 — 5.5 V Grade 1
Supply Voltage VCC2 1.7 — 5.5 V Grade 3
Supply Current ICC1 — — 6.0 mA VCC = 5.0V at 5 MHz, SO = Open,
Read
Supply Current ICC2 — — 3.0 mA VCC = 5.0V at 1 MHz
Supply Current ICC3 — — 7.0 mA VCC = 5.0V at 5 MHz, SO = Open,
Read, Write
Standby Current ISB1 — 0.1 9.0 µA VCC = 1.7V, CS = VCC
Standby Current ISB2 — 0.2 10.0 µA VCC = 2.5V, CS = VCC
Standby Current ISB3 — 2.0 13.0 µA VCC = 5.0V, CS = VCC
Input Leakage IIL -3.0 — 3.0 µA VIN = 0V to VCC
Output Leakage IOL -3.0 — 3.0 µA VIN = 0V to VCC
Input LowVoltage VIL (2) -0.6 — VCC x 0.3 V
AT25080B/AT25160B/AT25320B/AT25640B Electrical
Characteristics
...........continued Parameter Symbol Minimum Typical Maximum Units
Conditions
Input HighVoltage VIH (2) VCC x 0.7 — VCC + 0.5 V
Output LowVoltage VOL1 — — 0.4 V 2.5V ≤ VCC ≤ 5.5V IOL = 3.0
mA
Output HighVoltage VOH1 VCC - 0.8 — — V 2.5V ≤ VCC ≤ 5.5V IOH =
-1.6 mA
Output LowVoltage VOL2 — — 0.2 V 1.7V ≤ VCC ≤ 5.5V IOL = 0.15
mA
Output HighVoltage VOH2 VCC - 0.2 — — V 1.7V ≤ VCC ≤ 5.5V IOH =
-100 µA
Note: 1. Applicable over recommended operating range from: TA1 =
-40°C to +125°C, VCC1 = 2.5V to 5.5V, TA2 = -40°C
to +85°C, VCC2 = 1.7V to 5.5V. 2. VIL min and VIH max are reference
only and are not tested.
4.4 AC Characteristics Table 4-3. AC Characteristics(1)
Parameter Symbol Minimum Maximum Units Conditions
SCK Clock Frequency fSCK 0 5 MHz
Input Rise Time tRI — 2000 ns
Input Fall Time tFI — 2000 ns
SCK High Time tWH 40 — ns
SCK Low Time tWL 40 — ns
CS High Time tCS 80 — ns
CS Setup Time tCSS 80 — ns
CS Hold Time tCSH 80 — ns
Data In Setup Time tSU 5 — ns
Data In Hold Time tH 20 — ns
HOLD Setup Time tHD 40 — ns
HOLD Hold Time tCD 40 — ns
Output Valid tV 0 40 ns
Output Hold Time tHO 0 — ns
HOLD to Output Low Z tLZ 0 40 ns
HOLD to Output High Z tHZ — 80 ns
Output Disable Time tDIS — 80 ns
Write Cycle Time tWC — 5 ms
Note: 1. Applicable over recommended operating ranges from TA1 =
-40°C to +125°C, VCC1 = 2.5V to 5.5V and
TA2 = -40°C to +85°C, VCC2 = 1.7V to 5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted).
AT25080B/AT25160B/AT25320B/AT25640B Electrical
Characteristics
4.5 SPI Synchronous Data Timing
tDIStHO
tCSH
tCS
tV
tH
VOH
VOL
4.6 Electrical Specifications
4.6.1 Power-Up Requirements and Reset Behavior During a power-up
sequence, the VCC supplied to the
AT25080B/AT25160B/AT25320B/AT25640B should monotonically rise from
GND to the minimum VCC level, as specified in Table 4-1, with a
slew rate no faster than 0.1 V/µs.
4.6.1.1 Device Reset To prevent inadvertent write operations or any
other spurious events from occurring during a power-up sequence,
the AT25080B/AT25160B/AT25320B/AT25640B includes a Power-on Reset
(POR) circuit. Upon power-up, the device will not respond to any
instructions until the VCC level crosses the internal voltage
threshold (VPOR) that brings the device out of Reset and into
Standby mode.
The system designer must ensure the instructions are not sent to
the device until the VCC supply has reached a stable value greater
than or equal to the minimum VCC level. Additionally, once the VCC
is greater than or equal to the minimum VCC level, the bus master
must wait at least tPUP before sending the first instruction to the
device. See Table 4-4 for the values associated with these power-up
parameters.
Table 4-4. Power-Up Conditions(1)
Symbol Parameter Min. Max. Units
tPUP Time required after VCC is stable before the device can accept
instructions 100 µs
VPOR Power-on Reset Threshold Voltage 1.5 V
tPOFF Minimum time at VCC = 0V between power cycles 500 ms
Note: 1. These parameters are characterized but they are not 100%
tested in production.
If an event occurs in the system where the VCC level supplied to
the AT25080B/AT25160B/AT25320B/AT25640B drops below the maximum
VPOR level specified, it is recommended that a full-power cycle
sequence be performed by first driving the VCC pin to GND in less
than 1 ms, waiting at least the minimum tPOFF time and then
performing a new power-up sequence in compliance with the
requirements defined in this section.
AT25080B/AT25160B/AT25320B/AT25640B Electrical
Characteristics
4.6.2 Pin Capacitance Table 4-5. Pin Capacitance(1,2)
Symbol Test Condition Max. Units Conditions
COUT Output Capacitance (SO) 8 pF VOUT = 0V
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V
Note: 1. This parameter is characterized but is not 100% tested in
production. 2. Applicable over recommended operating range from: TA
= 25°C, fSCK = 1.0 MHz, VCC = 5.0V (unless otherwise
noted).
4.6.3 EEPROM Cell Performance Characteristics Table 4-6. EEPROM
Cell Performance Characteristics
Operation Test Condition Min. Max. Units
Write Endurance(1) TA = 25°C, VCC = 3.3V, Page Write mode
1,000,000 — Write Cycles
Note: 1. Performance is determined through characterization and the
qualification process.
4.6.4 Software Reset The SPI interface of the
AT25080B/AT25160B/AT25320B/AT25640B can be reset by toggling the CS
input. If the CS line is already in the Active state, it must
complete a transition from the Inactive state (≥VIH) to the Active
state (≤VIL) and then back to the Inactive state (≥VIH) without
sending clocks on the SCK line. Upon completion of this sequence,
the device will be ready to receive a new opcode on the SI
line.
4.6.5 Device Default State at Power-Up The
AT25080B/AT25160B/AT25320B/AT25640B default state upon power-up
consists of:
• Standby Power mode • A high-to-low-level transition on CS is
required to enter Active state • Write Enable Latch (WEL) bit in
the STATUS register = 0 • Ready/Busy bit in the STATUS register =
0, indicating the device is ready to accept a new command • Device
is not selected • Not in Hold condition • WPEN, BP1 and BP0 bits in
the STATUS register are unchanged from their previous state due to
the fact that
they are nonvolatile values
4.6.6 Device Default Condition The
AT25080B/AT25160B/AT25320B/AT25640B is shipped from Microchip to
the customer with the EEPROM array set to an all FFh data pattern
(logic ‘1’ state). The Write-Protect Enable bit in the STATUS
register is set to logic ‘0’ and the Block WriteProtect bits in the
STATUS register are set to logic ‘0’.
AT25080B/AT25160B/AT25320B/AT25640B Electrical
Characteristics
© 2020 Microchip Technology Inc. DS20006310A-page 12
5. Device Operation The AT25080B/AT25160B/AT25320B/AT25640B is
controlled by a set of instructions that are sent from a host
controller, commonly referred to as the SPI Master. The SPI Master
communicates with the AT25080B/AT25160B/ AT25320B/AT25640B via the
SPI bus which is comprised of four signal lines: Chip Select (CS),
Serial Data Clock (SCK), Serial Data Input (SI) and Serial Data
Output (SO).
The SPI protocol defines a total of four modes of operation (Mode
0, 1, 2 or 3) with each mode differing in respect to the SCK
polarity and phase and how the polarity and phase control the flow
of data on the SPI bus. The AT25080B/ AT25160B/AT25320B/AT25640B
supports the two most common modes, SPI Modes 0 and 3. With SPI
Modes 0 and 3, data is always latched in on the rising edge of SCK
and always output on the falling edge of SCK. The only difference
between SPI Modes 0 and 3 is the polarity of the SCK signal when in
the Inactive state (when the SPI Master is in Standby mode and not
transferring any data). SPI Mode 0 is defined as a low SCK while CS
is not asserted (at VCC) and SPI Mode 3 has SCK high in the
Inactive state. The SCK Idle state must match when the CS is
deasserted both before and after the communication sequence in SPI
Mode 0 and 3. The figures in this document depict Mode 0 with a
solid line on SCK while CS is inactive and Mode 3 with a dotted
line.
Figure 5-1. SPI Mode 0 and Mode 3
SO
SI
SCK
CS
5.1 Interfacing the AT25080B/AT25160B/AT25320B/AT25640B on the SPI
Bus Communication to and from the
AT25080B/AT25160B/AT25320B/AT25640B must be initiated by the SPI
Master device, such as a microcontroller. The SPI Master device
must generate the serial clock for the AT25080B/
AT25160B/AT25320B/AT25640B on the Serial Data Clock (SCK) pin. The
AT25080B/AT25160B/AT25320B/ AT25640B always operates as a slave due
to the fact that the SCK is always an input.
5.1.1 Selecting the Device The AT25080B/AT25160B/AT25320B/AT25640B
is selected when the Chip Select (CS) pin is low. When the device
is not selected, data will not be accepted via the Serial Data
Input (SI) pin, and the Serial Data Output (SO) pin will remain in
a highimpedance state.
5.1.2 Sending Data to the Device The
AT25080B/AT25160B/AT25320B/AT25640B uses the SI pin to receive
information. All instructions, addresses and data input bytes are
clocked into the device with the Most Significant bit (MSb) first.
The SI pin samples on the first rising edge of the SCK line after
the CS has been asserted.
5.1.3 Receiving Data from the Device Data output from the device is
transmitted on the SO pin, with the MSb output first. The SO data
is latched on the first falling edge of SCK after the instruction
has been clocked into the device, such as the Read from Memory
Array (READ) and Read STATUS Register (RDSR) instructions. See Read
Sequence for more details.
AT25080B/AT25160B/AT25320B/AT25640B Device Operation
5.2 Device Opcodes
5.2.1 Serial Opcode After the device is selected by driving CS low,
the first byte will be received on the SI pin. This byte contains
the opcode that defines the operation to be performed. Refer to
Table 6-1 for a list of all opcodes that the AT25080B/
AT25160B/AT25320B/AT25640B will respond to.
5.2.2 Invalid Opcode If an invalid opcode is received, no data will
be shifted into AT25080B/AT25160B/AT25320B/AT25640B and the SO pin
will remain in a high-impedance state until the falling edge of CS
is detected again. This will reinitialize the serial
communication.
5.3 Hold Function The Suspend Serial Input (HOLD) pin is used to
pause the serial communication with the device without having to
stop or reset the clock sequence. The Hold mode, however, does not
have an effect on the internal write cycle. Therefore, if a write
cycle is in progress, asserting the HOLD pin will not pause the
operation and the write cycle will continue to completion.
The Hold mode can only be entered while the CS pin is asserted. The
Hold mode is activated by asserting the HOLD pin during the SCK low
pulse. If the HOLD pin is asserted during the SCK high pulse, then
the Hold mode will not be started until the beginning of the next
SCK low pulse. The device will remain in the Hold mode as long as
the HOLD pin and CS pin are asserted.
While in Hold mode, the SO pin will be in a high-impedance state.
In addition, both the SI pin and the SCK pin will be ignored. The
Write-Protect (WP) pin, however, can still be asserted or
deasserted while in the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin
must be deasserted during the SCK low pulse. If the HOLD pin is
deasserted during the SCK high pulse, then the Hold mode will not
end until the beginning of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted,
then any operation that may have been started will be aborted and
the device will reset the WEL bit in the STATUS register back to
the logic ‘0’ state. Figure 5-2. Hold Mode
HOLD
SCK
CS
Figure 5-3. Hold Timing
tHD
tHD
tLZ
tHZ
5.4 Write Protection The Write-Protect (WP) pin will allow normal
read and write operations when held high. When the WP pin is
brought low and WPEN bit is a logic ‘1’, all write operations to
the STATUS register are inhibited. The WP pin going low while CS is
still low will interrupt a Write STATUS Register (WRSR). If the
internal write cycle has already been initiated, WP going low will
have no effect on any write operation to the STATUS register. The
WP pin function is blocked when the WPEN bit in the STATUS register
is a logic ‘0’. This will allow the user to install the
AT25080B/AT25160B/AT25320B/ AT25640B device in a system with the WP
pin tied to ground and still be able to write to the STATUS
register. All WP pin functions are enabled when the WPEN bit is set
to a logic ‘1’.
AT25080B/AT25160B/AT25320B/AT25640B Device Operation
6. Device Commands and Addressing The
AT25080B/AT25160B/AT25320B/AT25640B is designed to interface
directly with the synchronous Serial Peripheral Interface (SPI).
The AT25080B/AT25160B/AT25320B/AT25640B utilizes an 8bit
instruction register. The list of instructions and their operation
codes are contained in Table 6-1. All instructions, addresses and
data are transferred with the MSb first and start with a hightolow
CS transition.
Table 6-1. Instruction Set for the
AT25080B/AT25160B/AT25320B/AT25640B
Instruction Name Instruction Format Operates On Operation
Description
WREN 0000 X110 STATUS Register Set Write Enable Latch (WEL)
WRDI 0000 X100 STATUS Register Reset Write Enable Latch (WEL)
RDSR 0000 X101 STATUS Register Read STATUS Register
WRSR 0000 X001 STATUS Register Write STATUS Register
READ 0000 X011 Memory Array Read from Memory Array
WRITE 0000 X010 Memory Array Write to Memory Array
6.1 STATUS Register Bit Definition and Function The
AT25080B/AT25160B/AT25320B/AT25640B includes an 8bit STATUS
register. The STATUS register bits modulate various features of the
device as shown in Table 6-2 and Table 6-3. These bits can be
changed by specific instructions that are detailed in the following
sections. Table 6-2. STATUS Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEL RDY/BSY
Table 6-3. STATUS Register Bit Definition
Bit Name Type Description
7 WPEN Write-Protect Enable R/W 0 See Table 6-5 (Factory
Default)
1 See Table 6-5 (Factory Default)
6:4 RFU Reserved for Future Use R 0 Reads as zeros when the device
is not in a write cycle
1 Reads as ones when the device is in a write cycle
3:2 BP1 BP0
Block Write Protection R/W 00 No array write protection (Factory
Default)
01 Quarter array write protection (see Table 6-4)
10 Half array write protection (see Table 6-4)
11 Entire array write protection (see Table 6-4)
1 WEL Write Enable Latch R 0 Device is not write enabled (Power-up
Default)
1 Device is write enabled
0 RDY/BSY Ready/Busy Status R 0 Device is ready for a new
sequence
1 Device is busy with an internal operation
AT25080B/AT25160B/AT25320B/AT25640B Device Commands and
Addressing
© 2020 Microchip Technology Inc. DS20006310A-page 16
6.2 Read STATUS Register (RDSR) The Read STATUS Register (RDSR)
instruction provides access to the STATUS register. The ready/busy
and write enable status of the device can be determined by the RDSR
instruction. Similarly, the Block Write-Protect (BP1, BP0) bits
indicate the extent of memory array protection employed. The STATUS
register is read by asserting the CS pin, followed by sending in a
05h opcode on the SI pin. Upon completion of the opcode, the device
will return the 8bit STATUS register value on the SO pin. Figure
6-1. RDSR Waveform
SO
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
High-Impedance
D7 D6 D5 D4 D3 D2 D1 D0 MSb
STATUS Register Data Out
6.3 Write Enable (WREN) and Write Disable (WRDI) Enabling and
disabling writing to the STATUS register and EEPROM array is
accomplished through the Write Enable (WREN) instruction and the
Write Disable (WRDI) instruction. These functions change the status
of the WEL bit in the STATUS register.
6.3.1 Write Enable Instruction (WREN) The Write Enable Latch (WEL)
bit of the STATUS register must be set to a logic ‘1’ prior to each
Write STATUS Register (WRSR) and Write to Memory Array (WRITE)
instructions. This is accomplished by sending a WREN (06h)
instruction to the AT25080B/AT25160B/AT25320B/AT25640B. First, the
CS pin is driven low to select the device and then a WREN
instruction is clocked in on the SI pin. Then the CS pin can be
driven high and the WEL bit will be updated in the STATUS register
to a logic ‘1’. The device will powerup in the Write Disable state
(WEL = 0).
AT25080B/AT25160B/AT25320B/AT25640B Device Commands and
Addressing
© 2020 Microchip Technology Inc. DS20006310A-page 17
Figure 6-2. WREN Timing
0 0 0 0 0 1 1 0
0 1 2 3 4 5 6 7
6.3.2 Write Disable Instruction (WRDI) To protect the device
against inadvertent writes, the Write Disable (WRDI) instruction
(opcode 04h) disables all programming modes by setting the WEL bit
to a logic ‘0’. The WRDI instruction is independent of the status
of the WP pin. Figure 6-3. WRDI Timing
SO
SCK
CS
High-Impedance
0 0 0 0 0 1 0 0
0 1 2 3 4 5 6 7
6.4 Write STATUS Register (WRSR) The Write STATUS Register (WRSR)
instruction enables the SPI Master to change selected bits of the
STATUS register. Before a WRSR instruction can be initiated, a WREN
instruction must be executed to set the WEL bit to logic ‘1’. Upon
completion of a WREN instruction, a WRSR instruction can be
executed.
Note: The WRSR instruction has no effect on bit 6, bit 5, bit 4,
bit 1 and bit 0 of the STATUS register. Only bit 7, bit 3 and bit 2
can be changed via the WRSR instruction. These modifiable bits are
the Write-Protect Enable (WPEN) and Block Protect (BP1, BP0) bits.
These three bits are nonvolatile bits that have the same properties
and functions as regular EEPROM cells. Their values are retained
while power is removed from the device.
The AT25080B/AT25160B/AT25320B/AT25640B will not respond to
commands other than a RDSR after a WRSR instruction until the
selftimed internal write cycle has completed. When the write cycle
is completed, the WEL bit in the STATUS register is reset to logic
‘0’.
AT25080B/AT25160B/AT25320B/AT25640B Device Commands and
Addressing
© 2020 Microchip Technology Inc. DS20006310A-page 18
Figure 6-4. WRSR Waveform
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
STATUS Register Data In
MSb
SO
SI
tWC (1)
Note: 1. This instruction initiates a self-timed internal write
cycle (tWC) on the rising edge of CS after a valid sequence.
6.4.1 Block Write-Protect Function The WRSR instruction allows the
user to select one of four possible combinations as to how the
memory array will be inhibited from writing through changing the
Block Write-Protect bits (BP1, BP0). The four levels of array
protection are:
• None of the memory array is protected. • Upper quarter (¼)
address range is write-protected meaning the highest order address
bits are read-only. • Upper half (½) address range is
write-protected meaning the highest order address bits are
read-only. • All of the memory array is write-protected meaning all
address bits are read-only.
The Block Write Protection levels and corresponding STATUS register
control bits are shown in Table 6-4. Table 6-4. Block Write-Protect
Bits
Level STATUS Register Bits Write-Protected/ReadOnly Address
Range
BP1 BP0 AT25080B AT25160B AT25320B AT25640B
0 0 0 None None None None
1(1/4) 0 1 0300h-03FFh 0600h-07FFh 0C00h-0FFFh 1800h-1FFFh
2(1/2) 1 0 0200h-03FFh 0400h-07FFh 0800h-0FFFh 1000h-1FFFh
3(All) 1 1 0000h-03FFh 0000h-07FFh 0000h-0FFFh 0000h-1FFFh
6.4.2 Write-Protect Enable Function The WRSR instruction also
allows the user to enable or disable the Write-Protect (WP) pin
through the use of the Write-Protect Enable (WPEN) bit. When the
WPEN bit is set to logic ‘0’, the ability to write the EEPROM array
is dictated by the values of the Block Write-Protect (BP1, BP0)
bits. The ability to write the STATUS register is controlled by the
WEL bit. When the WPEN bit is set to logic ‘1’, the STATUS register
is read-only.
Hardware Write Protection is enabled when both the WP pin is low
and the WPEN bit has been set to a logic ‘1’. When the device is
Hardware WriteProtected, writes to the STATUS register, including
the Block WriteProtect, WEL and WPEN bits and to the sections in
the memory array selected by the Block WriteProtect bits are
disabled. When Hardware Write Protection is enabled, writes are
only allowed to sections of the memory that are not
blockprotected.
Hardware Write Protection is disabled when either the WP pin is
high or the WPEN bit is a logic ‘0’. When Hardware Write Protection
is disabled, writes are only allowed to sections of the memory that
are not blockprotected. Refer to Table 6-5 for additional
information.
AT25080B/AT25160B/AT25320B/AT25640B Device Commands and
Addressing
© 2020 Microchip Technology Inc. DS20006310A-page 19
Note: When the WPEN bit is Hardware WriteProtected, it cannot be
set back to a logic ‘0’ as long as the WP pin is held low.
Table 6-5. WPEN Operation
WPEN WP Pin WEL Protected Blocks Unprotected Blocks STATUS
Register
0 x 0 Protected Protected Protected
0 x 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
x High 0 Protected Protected Protected
x High 1 Protected Writable Writable
AT25080B/AT25160B/AT25320B/AT25640B Device Commands and
Addressing
© 2020 Microchip Technology Inc. DS20006310A-page 20
7. Read Sequence Reading the AT25080B/AT25160B/AT25320B/AT25640B
via the SO pin requires the following sequence. After the CS line
is pulled low to select a device, the READ (03h) instruction is
transmitted via the SI line followed by the 16bit address to be
read. Refer to Table 7-1 for the address bits for
AT25080B/AT25160B/AT25320B/AT25640B. Table 7-1.
AT25080B/AT25160B/AT25320B/AT25640B Address Bits
Address AT25080B AT25160B AT25320B AT25640B
AN A9-A0 A10-A0 A11-A0 A12-A0
Don’t Care Bits A15-A10 A15-A11 A15-A12 A15-A13
Upon completion of the 16bit address, any data on the SI line will
be ignored. The data (D7D0) at the specified address is then
shifted out onto the SO line. If only one byte is to be read, the
CS line should be driven high after the data comes out. The read
sequence can be continued since the byte address is automatically
incremented and data will continue to be shifted out. When the
highestorder address bit is reached, the address counter will
rollover to the lowestorder address bit allowing the entire memory
to be read in one continuous read cycle regardless of the starting
address. Figure 7-1. Read Waveform
SO
SI
SCK
MSb
MSb
0 0 0 0 0 0 1 1
6 754 10 1198 12 27 2823 26252421 2219 20 29 30 31
READ Opcode (03h)
A A A
D D D D D D D D D D
MSb MSb
© 2020 Microchip Technology Inc. DS20006310A-page 21
8. Write Sequence In order to program the
AT25080B/AT25160B/AT25320B/AT25640B, two separate instructions must
be executed. First, the device must be write enabled via the Write
Enable (WREN) instruction. Then, one of the two possible write
sequences described in this section may be executed.
Note: If the device is not Write Enabled (WREN), the device will
ignore the WRITE instruction and will return to the standby state
when CS is brought high. A new CS assertion is required to
reinitiate communication.
The address of the memory location(s) to be programmed must be
outside the protected address field location selected by the block
write protection level. During an internal write cycle, all
commands will be ignored except the RDSR instruction. Refer to
Table 8-1 for the address bits for
AT25080B/AT25160B/AT25320B/AT25640B. Table 8-1.
AT25080B/AT25160B/AT25320B/AT25640B Address Bits
Address AT25080B AT25160B AT25320B AT25640B
AN A9-A0 A10-A0 A11-A0 A12-A0
Don’t Care Bits A15-A10 A15-A11 A15-A12 A15-A13
8.1 Byte Write A byte write requires the following sequence and is
depicted in Figure 8-1. After the CS line is pulled low to select
the device, the WRITE (02h) instruction is transmitted via the SI
line followed by the 16bit address and the data (D7D0) to be
programmed. Programming will start after the CS pin is brought
high. The lowtohigh transition of the CS pin must occur during the
SCK low time (Mode 0) and SCK high time (Mode 3) immediately after
clocking in the D0 (LSB) data bit. The
AT25080B/AT25160B/AT25320B/AT25640B is automatically returned to
the Write Disable state (STATUS register bit WEL = 0) at the
completion of a write cycle.
Figure 8-1. Byte Write
2 310
6 754 10 1198 12 3129 3025 28272623 2421 22
WRITE Opcode (02h)
High-Impedance
A A A D7 D6 D5 D4 D3 D2 D1 D0 MSb
Address Bits A15-A0 Data In
tWC (1)
Note: 1. This instruction initiates a self-timed internal write
cycle (tWC) on the rising edge of CS after a valid sequence.
8.2 Page Write A page write sequence allows up to 32 bytes to be
written in the same write cycle, provided that all bytes are in the
same row of the memory array. Partial page writes of less than 32
bytes are allowed. After each byte of data is received, the five
lowest order address bits are internally incremented following the
receipt of each data byte. The higher order address bits are not
incremented and retain the memory array page location. If more
bytes of data are transmitted than will fit to the end of that
memory row, the address counter will rollover to the beginning of
the same row. Nevertheless, creating a rollover event should be
avoided as previously loaded data in the page could become
unintentionally altered. The AT25080B/AT25160B/AT25320B/AT25640B is
automatically returned to the Write Disable state (WEL = 0) at the
completion of a write cycle.
AT25080B/AT25160B/AT25320B/AT25640B Write Sequence
Figure 8-2. Page Write
WRITE Opcode (02h)
High-Impedance
A A A A AA D D D D D D D D MSb
Address Bits A15-A0 Data In Byte 1
D D D D D D D D MSb
Data In Byte 64
CS tWC (1)
Note: 1. This instruction initiates a selftimed internal write
cycle (tWC) on the rising edge of CS after a valid sequence.
8.3 Polling Routine A polling routine can be implemented to
optimize timesensitive applications that would not prefer to wait
the fixed maximum write cycle time (tWC). This method allows the
application to know immediately when the write cycle has completed
to start a subsequent operation.
Once the internally-timed write cycle has started, a polling
routine can be initiated. This involves repeatedly sending a Read
STATUS Register (RDSR) instruction to determine if the device has
completed its self-timed internal write cycle. If the RDY/BSY bit
(bit 0 of STATUS register) = 1, the write cycle is still in
progress. If bit 0 = 0, the write cycle has ended. If the RDY/BSY
bit = 1, repeated RDSR commands can be executed until the RDY/BSY
bit = 0, signaling that the device is ready to execute a new
instruction. Only the Read STATUS Register (RDSR) instruction is
enabled during the write cycle. Figure 8-3. Polling Flowchart
Send Valid Write
Initiate a Write Cycle
9. Packaging Information
Catalog Number Truncation AT25080B Truncation Code ###: 58B
AT25160B Truncation Code ###: 5AB AT25320B Truncation Code ###: 5BB
AT25640B Truncation Code ###: 5CB
Date Codes Product Variantion YY = Year Y = Year WW = Work Week of
Assembly %% = Product Variantion 16: 2016 20: 2020 6: 2016 0: 2020
02: Week 2 GV: GV Product Variation 17: 2017 21: 2021 7: 2017 1:
2021 04: Week 4 18: 2018 22: 2022 8: 2018 2: 2022 ... 19: 2019 23:
2023 9: 2019 3: 2023 52: Week 52
Country of Origin $ = Device Grade Atmel Truncation CO = Country of
Origin P: Automotive Grade 1, 2.5V min. AT: Atmel 9: Automotive
Grade 3, 1.7V min. ATM: Atmel ATML: Atmel
Lot Number or Trace Code NNN = Alphanumeric Trace Code (2
Characters for Small Packages)
YYWWNNN ###%% CO ATML$YWW
YYWWNNN ###%% AT$YWW
Note 2: Package drawings are not to scale Note 1: designates pin
1
8-Pad UDFN
AT25080B/AT25160B/AT25320B/AT25640B Packaging Information
0.25 C A–B D
C
0.10 C
0.10 C
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of
2
8X
For the most current package drawings, please see the Microchip
Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body
[SOIC]
© 2020 Microchip Technology Inc.
H 0.23
AT25080B/AT25160B/AT25320B/AT25640B Packaging Information
© 2020 Microchip Technology Inc. DS20006310A-page 25
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of
2
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body
[SOIC]
For the most current package drawings, please see the Microchip
Packaging Specification located at
http://www.microchip.com/packaging
Note:
Foot Angle 0° - 8°
15°-5°Mold Draft Angle Bottom 15°-5°Mold Draft Angle Top
0.51-0.31bLead Width 0.25-0.17cLead Thickness
1.27-0.40LFoot Length 0.50-0.25hChamfer (Optional)
4.90 BSCDOverall Length 3.90 BSCE1Molded Package Width 6.00
BSCEOverall Width
0.25-0.10A1Standoff --1.25A2Molded Package Thickness
1.75--AOverall Height 1.27 BSCePitch
MILLIMETERSUnits
protrusions shall not exceed 0.15mm per side. 3. Dimensions D and
E1 do not include mold flash or protrusions. Mold flash or
REF: Reference Dimension, usually without tolerance, for
information purposes only. BSC: Basic Dimension. Theoretically
exact value shown without tolerances.
1. Pin 1 visual index feature may vary, but must be located within
the hatched area. 2. § Significant Characteristic
4. Dimensioning and tolerancing per ASME Y14.5M
Notes:
5. Datums A & B to be determined at Datum H.
AT25080B/AT25160B/AT25320B/AT25640B Packaging Information
RECOMMENDED LAND PATTERN
BSC: Basic Dimension. Theoretically exact value shown without
tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip
Packaging Specification located at
http://www.microchip.com/packaging
Note:
MILLIMETERS
Y1 X1
1.55 0.60
SILK SCREEN
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body
[SOIC]
AT25080B/AT25160B/AT25320B/AT25640B Packaging Information
M Packaging Diagrams and Parameters
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body
[TSSOP]
Notes: 1. Pin 1 visual index feature may vary, but must be located
within the hatched area. 2. Dimensions D and E1 do not include mold
flash or protrusions. Mold flash or protrusions shall not exceed
0.15 mm per side. 3. Dimensioning and tolerancing per ASME
Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without
tolerances. REF: Reference Dimension, usually without tolerance,
for information purposes only.
Note: For the most current package drawings, please see the
Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS Dimension Limits MIN NOM MAX
Number of Pins N 8 Pitch e 0.65 BSC Overall Height A – – 1.20
Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15
Overall Width E 6.40 BSC Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 2.90 3.00 3.10 Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 –
0.20 Lead Width b 0.19 – 0.30
D
N
E
E1
M Packaging Diagrams and Parameters
Note: For the most current package drawings, please see the
Microchip Packaging Specification located at
http://www.microchip.com/packaging
AT25080B/AT25160B/AT25320B/AT25640B Packaging Information
BA
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 1 of 2
2X
8X
For the most current package drawings, please see the Microchip
Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm
Body [UDFN] Atmel Legacy YNZ Package
© 2017 Microchip Technology Inc.
REF: Reference Dimension, usually without tolerance, for
information purposes only. BSC: Basic Dimension. Theoretically
exact value shown without tolerances.
1. 2. 3.
Notes:
Pin 1 visual index feature may vary, but must be located within the
hatched area. Package is saw singulated Dimensioning and
tolerancing per ASME Y14.5M
For the most current package drawings, please see the Microchip
Packaging Specification located at
http://www.microchip.com/packaging
Note:
D D2 1.40
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 2 of 2
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm
Body [UDFN] Atmel Legacy YNZ Package
AT25080B/AT25160B/AT25320B/AT25640B Packaging Information
RECOMMENDED LAND PATTERN
Dimension Limits Units
Contact Pitch
Y2 X2
1.40 1.60
Y1 X1
0.85 0.30
0.30 1.00
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled
or tented to avoid solder loss during reflow process
1.
2.
For the most current package drawings, please see the Microchip
Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing C04-21355-Q4B Rev A
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm
Body [UDFN] Atmel Legacy YNZ Package
X2
Y2
Y1
AT25080B/AT25160B/AT25320B/AT25640B Packaging Information
10. Revision History
Revision A (February 2020) Updated to Microchip template. Microchip
DS20006310 replaces Atmel document 8803. Updated Part Marking
Information. Added ESD rating. Removed lead finish designation.
Removed the Automotive Grade 2 option. Corrected operating ranges
for Table 4-3. Updated POR recommendations section. Updated trace
code format in package markings. Updated formatting throughout for
clarification. Updated the SOIC, TSSOP and UDFN package drawings to
the Microchip equivalents.
Atmel Document 8803 Revision E (September 2016) Added the
Automotive Grade 2 and 3 options and UDFN options.
Atmel Document 8803 Revision D (June 2015) Updated ordering codes
tables and Section 7.1, part marking information, 8S1 and 8X
package drawings, footers and reorganized the document.
Atmel Document 8803 Revision C (December 2012) Condensed and
updated ordering code table.
Atmel Document 8803 Revision B (August 2012) Removed preliminary
status. Updated Atmel logos and disclaimer/copy page.
Atmel Document 8803 Revision A (February 2012) Initial document
release.
AT25080B/AT25160B/AT25320B/AT25640B Revision History
© 2020 Microchip Technology Inc. DS20006310A-page 33
The Microchip Website Microchip provides online support via our
website at http://www.microchip.com/. This website is used to make
files and information easily available to customers. Some of the
content available includes:
• Product Support – Data sheets and errata, application notes and
sample programs, design resources, user’s guides and hardware
support documents, latest software releases and archived
software
• General Technical Support – Frequently Asked Questions (FAQs),
technical support requests, online discussion groups, Microchip
design partner program member listing
• Business of Microchip – Product selector and ordering guides,
latest Microchip press releases, listing of seminars and events,
listings of Microchip sales offices, distributors and factory
representatives
Product Change Notification Service Microchip’s product change
notification service helps keep customers current on Microchip
products. Subscribers will receive email notification whenever
there are changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, go to http://www.microchip.com/pcn and follow the
registration instructions.
Customer Support Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative • Local Sales Office • Embedded
Solutions Engineer (ESE) • Technical Support
Customers should contact their distributor, representative or ESE
for support. Local sales offices are also available to help
customers. A listing of sales offices and locations is included in
this document.
Technical support is available through the website at:
http://www.microchip.com/support
AT25080B/AT25160B/AT25320B/AT25640B
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer
to the factory or the listed sales office.
Product Family 25 = Standard SPI
Serial EEPROM
Device Density
080 = 8-Kilobit 160 = 16-Kilobit 320 = 32-Kilobit 640 =
64-Kilobit
T = Tape and Reel, Standard Quantity Option E = Tape and Reel,
Extended Quantity Option
Operating Voltage M = 1.7V to 5.5V D = 2.5V to 5.5V
P = Automotive Grade 1 (-40°C to +125°C) 9 = Automotive Grade 3
(-40°C to +85°C)
SS = SOIC X = TSSOP MA = 2.0mm x 3.0mm UDFN
A T 2 5 0 8 0 B - S S P D x x - T
Device Revision
Examples:
Automotive Grade
AT25080BSSPDGVT SOIC SN SS Tape and Reel Grade 1
AT25160BSSPDGVT SOIC SN SS Tape and Reel Grade 1
AT25320BSS9MGVT SOIC SN SS Tape and Reel Grade 3
AT25640BSS9MGVT SOIC SN SS Tape and Reel Grade 3
AT25320BXPDGVT TSSOP ST X Tape and Reel Grade 1
AT25640BXPDGVT TSSOP ST X Tape and Reel Grade 1
AT25080BX9MGVT TSSOP ST X Tape and Reel Grade 3
AT25160BX9MGVT TSSOP ST X Tape and Reel Grade 3
AT25160BMAPDGVT UDFN Q4B MA Tape and Reel Grade 1
AT25320BMAPDGVT UDFN Q4B MA Tape and Reel Grade 1
AT25640BMAPDGVE UDFN Q4B MA Extended Qty. Tape and Reel
Grade 1
AT25080BMA9MGVT UDFN Q4B MA Tape and Reel Grade 3
AT25320BMA9MGVE UDFN Q4B MA Extended Qty. Tape and Reel
Grade 3
AT25640BMA9MGVT UDFN Q4B MA Tape and Reel Grade 3
AT25080B/AT25160B/AT25320B/AT25640B
© 2020 Microchip Technology Inc. DS20006310A-page 35
Microchip Devices Code Protection Feature Note the following
details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their
particular Microchip Data Sheet. • Microchip believes that its
family of products is one of the most secure families of its kind
on the market today,
when used in the intended manner and under normal conditions. •
There are dishonest and possibly illegal methods used to breach the
code protection feature. All of these
methods, to our knowledge, require using the Microchip products in
a manner outside the operating specifications contained in
Microchip’s Data Sheets. Most likely, the person doing so is
engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned
about the integrity of their code. • Neither Microchip nor any
other semiconductor manufacturer can guarantee the security of
their code. Code
protection does not mean that we are guaranteeing the product as
“unbreakable.”
Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of
our products. Attempts to break Microchip’s code protection feature
may be a violation of the Digital Millennium Copyright Act. If such
acts allow unauthorized access to your software or other
copyrighted work, you may have a right to sue for relief under that
Act.
Legal Notice Information contained in this publication regarding
device applications and the like is provided only for your
convenience and may be superseded by updates. It is your
responsibility to ensure that your application meets with your
specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF
ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO
ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR
PURPOSE. Microchip disclaims all liability arising from this
information and its use. Use of Microchip devices in life support
and/or safety applications is entirely at the buyer’s risk, and the
buyer agrees to defend, indemnify and hold harmless Microchip from
any and all damages, claims, suits, or expenses resulting from such
use. No licenses are conveyed, implicitly or otherwise, under any
Microchip intellectual property rights unless otherwise
stated.
Trademarks The Microchip name and logo, the Microchip logo,
Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud,
chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD,
maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo,
MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower,
PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA,
SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom,
SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O,
Vectron, and XMEGA are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra,
TimeProvider, Vite, WinPath, and ZL are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching,
DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP,
INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet
logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance,
TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the
U.S.A.
AT25080B/AT25160B/AT25320B/AT25640B
© 2020 Microchip Technology Inc. DS20006310A-page 36
The Adaptec logo, Frequency on Demand, Silicon Storage Technology,
and Symmcom are registered trademarks of Microchip Technology Inc.
in other countries.
GestIC is a registered trademark of Microchip Technology Germany II
GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies. © 2020, Microchip Technology Incorporated,
Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-5686-5
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE,
Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle,
Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore,
Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS,
ULINKpro, µVision, Versatile are trademarks or registered
trademarks of Arm Limited (or its subsidiaries) in the US and/or
elsewhere.
Quality Management System For information regarding Microchip’s
Quality Management Systems, please visit
http://www.microchip.com/quality.
AT25080B/AT25160B/AT25320B/AT25640B
Australia - Sydney Tel: 61-2-9868-6733 China - Beijing Tel:
86-10-8569-7000 China - Chengdu Tel: 86-28-8665-5511 China -
Chongqing Tel: 86-23-8980-9588 China - Dongguan Tel:
86-769-8702-9880 China - Guangzhou Tel: 86-20-8755-8029 China -
Hangzhou Tel: 86-571-8792-8115 China - Hong Kong SAR Tel:
852-2943-5100 China - Nanjing Tel: 86-25-8473-2460 China - Qingdao
Tel: 86-532-8502-7355 China - Shanghai Tel: 86-21-3326-8000 China -
Shenyang Tel: 86-24-2334-2829 China - Shenzhen Tel:
86-755-8864-2200 China - Suzhou Tel: 86-186-6233-1526 China - Wuhan
Tel: 86-27-5980-5300 China - Xian Tel: 86-29-8833-7252 China -
Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040
India - Bangalore Tel: 91-80-3090-4444 India - New Delhi Tel:
91-11-4160-8631 India - Pune Tel: 91-20-4121-0141 Japan - Osaka
Tel: 81-6-6152-7160 Japan - Tokyo Tel: 81-3-6880- 3770 Korea -
Daegu Tel: 82-53-744-4301 Korea - Seoul Tel: 82-2-554-7200 Malaysia
- Kuala Lumpur Tel: 60-3-7651-7906 Malaysia - Penang Tel:
60-4-227-8870 Philippines - Manila Tel: 63-2-634-9065 Singapore
Tel: 65-6334-8870 Taiwan - Hsin Chu Tel: 886-3-577-8366 Taiwan -
Kaohsiung Tel: 886-7-213-7830 Taiwan - Taipei Tel: 886-2-2508-8600
Thailand - Bangkok Tel: 66-2-694-1351 Vietnam - Ho Chi Minh Tel:
84-28-5448-2100
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark -
Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 Finland - Espoo Tel:
358-9-4520-820 France - Paris Tel: 33-1-69-53-63-20 Fax:
33-1-69-30-90-79 Germany - Garching Tel: 49-8931-9700 Germany -
Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-72400
Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel:
49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel:
49-8031-354-560 Israel - Ra’anana Tel: 972-9-744-7705 Italy - Milan
Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Tel:
39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax:
31-416-690340 Norway - Trondheim Tel: 47-72884388 Poland - Warsaw
Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain -
Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden -
Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel:
46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax:
44-118-921-5820
Worldwide Sales and Service
2. Pin Description
2.3. Write-Protect (WP)
2.4. Ground (GND)
3. Description
3.2. Block Diagram
4. Electrical Characteristics
4.3. DC Characteristics
4.4. AC Characteristics
4.6. Electrical Specifications
4.6.1.1. Device Reset
4.6.2. Pin Capacitance
4.6.4. Software Reset
4.6.6. Device Default Condition
5.1.1. Selecting the Device
5.2. Device Opcodes
5.2.1. Serial Opcode
5.2.2. Invalid Opcode
5.3. Hold Function
5.4. Write Protection
6.1. STATUS Register Bit Definition and Function
6.2. Read STATUS Register (RDSR)
6.3. Write Enable (WREN) and Write Disable (WRDI)
6.3.1. Write Enable Instruction (WREN)
6.3.2. Write Disable Instruction (WRDI)
6.4. Write STATUS Register (WRSR)
6.4.1. Block Write-Protect Function
6.4.2. Write-Protect Enable Function
Legal Notice